1 // SPDX-License-Identifier: MIT
3 * Copyright © 2014 Intel Corporation
6 #include "gem/i915_gem_lmem.h"
8 #include "gen8_engine_cs.h"
10 #include "i915_perf.h"
11 #include "intel_engine.h"
12 #include "intel_gpu_commands.h"
14 #include "intel_lrc.h"
15 #include "intel_lrc_reg.h"
16 #include "intel_ring.h"
17 #include "shmem_utils.h"
19 static void set_offsets(u32 *regs,
21 const struct intel_engine_cs *engine,
23 #define NOP(x) (BIT(7) | (x))
24 #define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6)))
26 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
28 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \
32 const u32 base = engine->mmio_base;
37 if (*data & BIT(7)) { /* skip */
38 count = *data++ & ~BIT(7);
47 *regs = MI_LOAD_REGISTER_IMM(count);
49 *regs |= MI_LRI_FORCE_POSTED;
50 if (GRAPHICS_VER(engine->i915) >= 11)
51 *regs |= MI_LRI_LRM_CS_MMIO;
62 offset |= v & ~BIT(7);
65 regs[0] = base + (offset << 2);
71 /* Close the batch; used mainly by live_lrc_layout() */
72 *regs = MI_BATCH_BUFFER_END;
73 if (GRAPHICS_VER(engine->i915) >= 11)
78 static const u8 gen8_xcs_offsets[] = {
113 static const u8 gen9_xcs_offsets[] = {
197 static const u8 gen12_xcs_offsets[] = {
229 static const u8 gen8_rcs_offsets[] = {
266 static const u8 gen9_rcs_offsets[] = {
350 static const u8 gen11_rcs_offsets[] = {
391 static const u8 gen12_rcs_offsets[] = {
487 static const u8 xehp_rcs_offsets[] = {
534 static const u8 *reg_offsets(const struct intel_engine_cs *engine)
537 * The gen12+ lists only have the registers we program in the basic
538 * default state. We rely on the context image using relative
539 * addressing to automatic fixup the register state between the
540 * physical engines for virtual engine.
542 GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
543 !intel_engine_has_relative_mmio(engine));
545 if (engine->class == RENDER_CLASS) {
546 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
547 return xehp_rcs_offsets;
548 else if (GRAPHICS_VER(engine->i915) >= 12)
549 return gen12_rcs_offsets;
550 else if (GRAPHICS_VER(engine->i915) >= 11)
551 return gen11_rcs_offsets;
552 else if (GRAPHICS_VER(engine->i915) >= 9)
553 return gen9_rcs_offsets;
555 return gen8_rcs_offsets;
557 if (GRAPHICS_VER(engine->i915) >= 12)
558 return gen12_xcs_offsets;
559 else if (GRAPHICS_VER(engine->i915) >= 9)
560 return gen9_xcs_offsets;
562 return gen8_xcs_offsets;
566 static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
568 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
570 else if (GRAPHICS_VER(engine->i915) >= 12)
572 else if (GRAPHICS_VER(engine->i915) >= 9)
574 else if (engine->class == RENDER_CLASS)
580 static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
582 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
584 else if (GRAPHICS_VER(engine->i915) >= 12)
586 else if (GRAPHICS_VER(engine->i915) >= 9)
588 else if (engine->class == RENDER_CLASS)
594 static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
596 if (GRAPHICS_VER(engine->i915) >= 12)
598 else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
604 static int lrc_ring_indirect_ptr(const struct intel_engine_cs *engine)
608 x = lrc_ring_wa_bb_per_ctx(engine);
615 static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
619 x = lrc_ring_indirect_ptr(engine);
626 static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
629 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
631 * Note that the CSFE context has a dummy slot for CMD_BUF_CCTL
632 * simply to match the RCS context image layout.
635 else if (engine->class != RENDER_CLASS)
637 else if (GRAPHICS_VER(engine->i915) >= 12)
639 else if (GRAPHICS_VER(engine->i915) >= 11)
646 lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
648 switch (GRAPHICS_VER(engine->i915)) {
650 MISSING_CASE(GRAPHICS_VER(engine->i915));
653 return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
655 return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
657 return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
659 return GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
664 lrc_setup_indirect_ctx(u32 *regs,
665 const struct intel_engine_cs *engine,
666 u32 ctx_bb_ggtt_addr,
670 GEM_BUG_ON(!IS_ALIGNED(size, CACHELINE_BYTES));
671 GEM_BUG_ON(lrc_ring_indirect_ptr(engine) == -1);
672 regs[lrc_ring_indirect_ptr(engine) + 1] =
673 ctx_bb_ggtt_addr | (size / CACHELINE_BYTES);
675 GEM_BUG_ON(lrc_ring_indirect_offset(engine) == -1);
676 regs[lrc_ring_indirect_offset(engine) + 1] =
677 lrc_ring_indirect_offset_default(engine) << 6;
680 static void init_common_regs(u32 * const regs,
681 const struct intel_context *ce,
682 const struct intel_engine_cs *engine,
687 ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
688 ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
690 ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
691 if (GRAPHICS_VER(engine->i915) < 11)
692 ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
693 CTX_CTRL_RS_CTX_ENABLE);
694 regs[CTX_CONTEXT_CONTROL] = ctl;
696 regs[CTX_TIMESTAMP] = ce->runtime.last;
699 static void init_wa_bb_regs(u32 * const regs,
700 const struct intel_engine_cs *engine)
702 const struct i915_ctx_workarounds * const wa_ctx = &engine->wa_ctx;
704 if (wa_ctx->per_ctx.size) {
705 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
707 GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);
708 regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =
709 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
712 if (wa_ctx->indirect_ctx.size) {
713 lrc_setup_indirect_ctx(regs, engine,
714 i915_ggtt_offset(wa_ctx->vma) +
715 wa_ctx->indirect_ctx.offset,
716 wa_ctx->indirect_ctx.size);
720 static void init_ppgtt_regs(u32 *regs, const struct i915_ppgtt *ppgtt)
722 if (i915_vm_is_4lvl(&ppgtt->vm)) {
723 /* 64b PPGTT (48bit canonical)
724 * PDP0_DESCRIPTOR contains the base address to PML4 and
725 * other PDP Descriptors are ignored.
727 ASSIGN_CTX_PML4(ppgtt, regs);
729 ASSIGN_CTX_PDP(ppgtt, regs, 3);
730 ASSIGN_CTX_PDP(ppgtt, regs, 2);
731 ASSIGN_CTX_PDP(ppgtt, regs, 1);
732 ASSIGN_CTX_PDP(ppgtt, regs, 0);
736 static struct i915_ppgtt *vm_alias(struct i915_address_space *vm)
738 if (i915_is_ggtt(vm))
739 return i915_vm_to_ggtt(vm)->alias;
741 return i915_vm_to_ppgtt(vm);
744 static void __reset_stop_ring(u32 *regs, const struct intel_engine_cs *engine)
748 x = lrc_ring_mi_mode(engine);
750 regs[x + 1] &= ~STOP_RING;
751 regs[x + 1] |= STOP_RING << 16;
755 static void __lrc_init_regs(u32 *regs,
756 const struct intel_context *ce,
757 const struct intel_engine_cs *engine,
761 * A context is actually a big batch buffer with several
762 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
763 * values we are setting here are only for the first context restore:
764 * on a subsequent save, the GPU will recreate this batchbuffer with new
765 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
766 * we are not initializing here).
768 * Must keep consistent with virtual_update_register_offsets().
772 memset(regs, 0, PAGE_SIZE);
774 set_offsets(regs, reg_offsets(engine), engine, inhibit);
776 init_common_regs(regs, ce, engine, inhibit);
777 init_ppgtt_regs(regs, vm_alias(ce->vm));
779 init_wa_bb_regs(regs, engine);
781 __reset_stop_ring(regs, engine);
784 void lrc_init_regs(const struct intel_context *ce,
785 const struct intel_engine_cs *engine,
788 __lrc_init_regs(ce->lrc_reg_state, ce, engine, inhibit);
791 void lrc_reset_regs(const struct intel_context *ce,
792 const struct intel_engine_cs *engine)
794 __reset_stop_ring(ce->lrc_reg_state, engine);
798 set_redzone(void *vaddr, const struct intel_engine_cs *engine)
800 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
803 vaddr += engine->context_size;
805 memset(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE);
809 check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
811 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
814 vaddr += engine->context_size;
816 if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))
817 drm_err_once(&engine->i915->drm,
818 "%s context redzone overwritten!\n",
822 void lrc_init_state(struct intel_context *ce,
823 struct intel_engine_cs *engine,
828 set_redzone(state, engine);
830 if (engine->default_state) {
831 shmem_read(engine->default_state, 0,
832 state, engine->context_size);
833 __set_bit(CONTEXT_VALID_BIT, &ce->flags);
837 /* Clear the ppHWSP (inc. per-context counters) */
838 memset(state, 0, PAGE_SIZE);
841 * The second page of the context object contains some registers which
842 * must be set up prior to the first execution.
844 __lrc_init_regs(state + LRC_STATE_OFFSET, ce, engine, inhibit);
847 static struct i915_vma *
848 __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
850 struct drm_i915_gem_object *obj;
851 struct i915_vma *vma;
854 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
856 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
857 context_size += I915_GTT_PAGE_SIZE; /* for redzone */
859 if (GRAPHICS_VER(engine->i915) == 12) {
860 ce->wa_bb_page = context_size / PAGE_SIZE;
861 context_size += PAGE_SIZE;
864 obj = i915_gem_object_create_lmem(engine->i915, context_size, 0);
866 obj = i915_gem_object_create_shmem(engine->i915, context_size);
868 return ERR_CAST(obj);
870 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
872 i915_gem_object_put(obj);
879 static struct intel_timeline *
880 pinned_timeline(struct intel_context *ce, struct intel_engine_cs *engine)
882 struct intel_timeline *tl = fetch_and_zero(&ce->timeline);
884 return intel_timeline_create_from_engine(engine, page_unmask_bits(tl));
887 int lrc_alloc(struct intel_context *ce, struct intel_engine_cs *engine)
889 struct intel_ring *ring;
890 struct i915_vma *vma;
893 GEM_BUG_ON(ce->state);
895 vma = __lrc_alloc_state(ce, engine);
899 ring = intel_engine_create_ring(engine, ce->ring_size);
905 if (!page_mask_bits(ce->timeline)) {
906 struct intel_timeline *tl;
909 * Use the static global HWSP for the kernel context, and
910 * a dynamically allocated cacheline for everyone else.
912 if (unlikely(ce->timeline))
913 tl = pinned_timeline(ce, engine);
915 tl = intel_timeline_create(engine->gt);
930 intel_ring_put(ring);
936 void lrc_reset(struct intel_context *ce)
938 GEM_BUG_ON(!intel_context_is_pinned(ce));
940 intel_ring_reset(ce->ring, ce->ring->emit);
942 /* Scrub away the garbage */
943 lrc_init_regs(ce, ce->engine, true);
944 ce->lrc.lrca = lrc_update_regs(ce, ce->engine, ce->ring->tail);
948 lrc_pre_pin(struct intel_context *ce,
949 struct intel_engine_cs *engine,
950 struct i915_gem_ww_ctx *ww,
953 GEM_BUG_ON(!ce->state);
954 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
956 *vaddr = i915_gem_object_pin_map(ce->state->obj,
957 i915_coherent_map_type(ce->engine->i915,
962 return PTR_ERR_OR_ZERO(*vaddr);
966 lrc_pin(struct intel_context *ce,
967 struct intel_engine_cs *engine,
970 ce->lrc_reg_state = vaddr + LRC_STATE_OFFSET;
972 if (!__test_and_set_bit(CONTEXT_INIT_BIT, &ce->flags))
973 lrc_init_state(ce, engine, vaddr);
975 ce->lrc.lrca = lrc_update_regs(ce, engine, ce->ring->tail);
979 void lrc_unpin(struct intel_context *ce)
981 check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
985 void lrc_post_unpin(struct intel_context *ce)
987 i915_gem_object_unpin_map(ce->state->obj);
990 void lrc_fini(struct intel_context *ce)
995 intel_ring_put(fetch_and_zero(&ce->ring));
996 i915_vma_put(fetch_and_zero(&ce->state));
999 void lrc_destroy(struct kref *kref)
1001 struct intel_context *ce = container_of(kref, typeof(*ce), ref);
1003 GEM_BUG_ON(!i915_active_is_idle(&ce->active));
1004 GEM_BUG_ON(intel_context_is_pinned(ce));
1008 intel_context_fini(ce);
1009 intel_context_free(ce);
1013 gen12_emit_timestamp_wa(const struct intel_context *ce, u32 *cs)
1015 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 |
1016 MI_SRM_LRM_GLOBAL_GTT |
1018 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1019 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
1020 CTX_TIMESTAMP * sizeof(u32);
1023 *cs++ = MI_LOAD_REGISTER_REG |
1024 MI_LRR_SOURCE_CS_MMIO |
1026 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1027 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));
1029 *cs++ = MI_LOAD_REGISTER_REG |
1030 MI_LRR_SOURCE_CS_MMIO |
1032 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1033 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));
1039 gen12_emit_restore_scratch(const struct intel_context *ce, u32 *cs)
1041 GEM_BUG_ON(lrc_ring_gpr0(ce->engine) == -1);
1043 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 |
1044 MI_SRM_LRM_GLOBAL_GTT |
1046 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1047 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
1048 (lrc_ring_gpr0(ce->engine) + 1) * sizeof(u32);
1055 gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs)
1057 GEM_BUG_ON(lrc_ring_cmd_buf_cctl(ce->engine) == -1);
1059 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 |
1060 MI_SRM_LRM_GLOBAL_GTT |
1062 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1063 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
1064 (lrc_ring_cmd_buf_cctl(ce->engine) + 1) * sizeof(u32);
1067 *cs++ = MI_LOAD_REGISTER_REG |
1068 MI_LRR_SOURCE_CS_MMIO |
1070 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1071 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));
1077 gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
1079 cs = gen12_emit_timestamp_wa(ce, cs);
1080 cs = gen12_emit_cmd_buf_wa(ce, cs);
1081 cs = gen12_emit_restore_scratch(ce, cs);
1087 gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)
1089 cs = gen12_emit_timestamp_wa(ce, cs);
1090 cs = gen12_emit_restore_scratch(ce, cs);
1095 static u32 context_wa_bb_offset(const struct intel_context *ce)
1097 return PAGE_SIZE * ce->wa_bb_page;
1100 static u32 *context_indirect_bb(const struct intel_context *ce)
1104 GEM_BUG_ON(!ce->wa_bb_page);
1106 ptr = ce->lrc_reg_state;
1107 ptr -= LRC_STATE_OFFSET; /* back to start of context image */
1108 ptr += context_wa_bb_offset(ce);
1114 setup_indirect_ctx_bb(const struct intel_context *ce,
1115 const struct intel_engine_cs *engine,
1116 u32 *(*emit)(const struct intel_context *, u32 *))
1118 u32 * const start = context_indirect_bb(ce);
1121 cs = emit(ce, start);
1122 GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs));
1123 while ((unsigned long)cs % CACHELINE_BYTES)
1126 lrc_setup_indirect_ctx(ce->lrc_reg_state, engine,
1127 i915_ggtt_offset(ce->state) +
1128 context_wa_bb_offset(ce),
1129 (cs - start) * sizeof(*cs));
1133 * The context descriptor encodes various attributes of a context,
1134 * including its GTT address and some flags. Because it's fairly
1135 * expensive to calculate, we'll just do it once and cache the result,
1136 * which remains valid until the context is unpinned.
1138 * This is what a descriptor looks like, from LSB to MSB::
1140 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
1141 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
1142 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
1143 * bits 53-54: mbz, reserved for use by hardware
1144 * bits 55-63: group ID, currently unused and set to 0
1146 * Starting from Gen11, the upper dword of the descriptor has a new format:
1148 * bits 32-36: reserved
1149 * bits 37-47: SW context ID
1150 * bits 48:53: engine instance
1151 * bit 54: mbz, reserved for use by hardware
1152 * bits 55-60: SW counter
1153 * bits 61-63: engine class
1155 * On Xe_HP, the upper dword of the descriptor has a new format:
1157 * bits 32-37: virtual function number
1158 * bit 38: mbz, reserved for use by hardware
1159 * bits 39-54: SW context ID
1160 * bits 55-57: reserved
1161 * bits 58-63: SW counter
1163 * engine info, SW context ID and SW counter need to form a unique number
1164 * (Context ID) per lrc.
1166 static u32 lrc_descriptor(const struct intel_context *ce)
1170 desc = INTEL_LEGACY_32B_CONTEXT;
1171 if (i915_vm_is_4lvl(ce->vm))
1172 desc = INTEL_LEGACY_64B_CONTEXT;
1173 desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
1175 desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
1176 if (GRAPHICS_VER(ce->vm->i915) == 8)
1177 desc |= GEN8_CTX_L3LLC_COHERENT;
1179 return i915_ggtt_offset(ce->state) | desc;
1182 u32 lrc_update_regs(const struct intel_context *ce,
1183 const struct intel_engine_cs *engine,
1186 struct intel_ring *ring = ce->ring;
1187 u32 *regs = ce->lrc_reg_state;
1189 GEM_BUG_ON(!intel_ring_offset_valid(ring, head));
1190 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
1192 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
1193 regs[CTX_RING_HEAD] = head;
1194 regs[CTX_RING_TAIL] = ring->tail;
1195 regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
1198 if (engine->class == RENDER_CLASS) {
1199 regs[CTX_R_PWR_CLK_STATE] =
1200 intel_sseu_make_rpcs(engine->gt, &ce->sseu);
1202 i915_oa_init_reg_state(ce, engine);
1205 if (ce->wa_bb_page) {
1206 u32 *(*fn)(const struct intel_context *ce, u32 *cs);
1208 fn = gen12_emit_indirect_ctx_xcs;
1209 if (ce->engine->class == RENDER_CLASS)
1210 fn = gen12_emit_indirect_ctx_rcs;
1212 /* Mutually exclusive wrt to global indirect bb */
1213 GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size);
1214 setup_indirect_ctx_bb(ce, engine, fn);
1217 return lrc_descriptor(ce) | CTX_DESC_FORCE_RESTORE;
1220 void lrc_update_offsets(struct intel_context *ce,
1221 struct intel_engine_cs *engine)
1223 set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false);
1226 void lrc_check_regs(const struct intel_context *ce,
1227 const struct intel_engine_cs *engine,
1230 const struct intel_ring *ring = ce->ring;
1231 u32 *regs = ce->lrc_reg_state;
1235 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {
1236 pr_err("%s: context submitted with incorrect RING_START [%08x], expected %08x\n",
1238 regs[CTX_RING_START],
1239 i915_ggtt_offset(ring->vma));
1240 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
1244 if ((regs[CTX_RING_CTL] & ~(RING_WAIT | RING_WAIT_SEMAPHORE)) !=
1245 (RING_CTL_SIZE(ring->size) | RING_VALID)) {
1246 pr_err("%s: context submitted with incorrect RING_CTL [%08x], expected %08x\n",
1249 (u32)(RING_CTL_SIZE(ring->size) | RING_VALID));
1250 regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
1254 x = lrc_ring_mi_mode(engine);
1255 if (x != -1 && regs[x + 1] & (regs[x + 1] >> 16) & STOP_RING) {
1256 pr_err("%s: context submitted with STOP_RING [%08x] in RING_MI_MODE\n",
1257 engine->name, regs[x + 1]);
1258 regs[x + 1] &= ~STOP_RING;
1259 regs[x + 1] |= STOP_RING << 16;
1263 WARN_ONCE(!valid, "Invalid lrc state found %s submission\n", when);
1267 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1268 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1269 * but there is a slight complication as this is applied in WA batch where the
1270 * values are only initialized once so we cannot take register value at the
1271 * beginning and reuse it further; hence we save its value to memory, upload a
1272 * constant value with bit21 set and then we restore it back with the saved value.
1273 * To simplify the WA, a constant value is formed by using the default value
1274 * of this register. This shouldn't be a problem because we are only modifying
1275 * it for a short period and this batch in non-premptible. We can ofcourse
1276 * use additional instructions that read the actual value of the register
1277 * at that time and set our bit of interest but it makes the WA complicated.
1279 * This WA is also required for Gen9 so extracting as a function avoids
1283 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1285 /* NB no one else is allowed to scribble over scratch + 256! */
1286 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1287 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1288 *batch++ = intel_gt_scratch_offset(engine->gt,
1289 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
1292 *batch++ = MI_LOAD_REGISTER_IMM(1);
1293 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1294 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1296 batch = gen8_emit_pipe_control(batch,
1297 PIPE_CONTROL_CS_STALL |
1298 PIPE_CONTROL_DC_FLUSH_ENABLE,
1301 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1302 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1303 *batch++ = intel_gt_scratch_offset(engine->gt,
1304 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
1311 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1312 * initialized at the beginning and shared across all contexts but this field
1313 * helps us to have multiple batches at different offsets and select them based
1314 * on a criteria. At the moment this batch always start at the beginning of the page
1315 * and at this point we don't have multiple wa_ctx batch buffers.
1317 * The number of WA applied are not known at the beginning; we use this field
1318 * to return the no of DWORDS written.
1320 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1321 * so it adds NOOPs as padding to make it cacheline aligned.
1322 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1323 * makes a complete batch buffer.
1325 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1327 /* WaDisableCtxRestoreArbitration:bdw,chv */
1328 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1330 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1331 if (IS_BROADWELL(engine->i915))
1332 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1334 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1335 /* Actual scratch location is at 128 bytes offset */
1336 batch = gen8_emit_pipe_control(batch,
1337 PIPE_CONTROL_FLUSH_L3 |
1338 PIPE_CONTROL_STORE_DATA_INDEX |
1339 PIPE_CONTROL_CS_STALL |
1340 PIPE_CONTROL_QW_WRITE,
1341 LRC_PPHWSP_SCRATCH_ADDR);
1343 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1345 /* Pad to end of cacheline */
1346 while ((unsigned long)batch % CACHELINE_BYTES)
1350 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1351 * execution depends on the length specified in terms of cache lines
1352 * in the register CTX_RCS_INDIRECT_CTX
1363 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1365 GEM_BUG_ON(!count || count > 63);
1367 *batch++ = MI_LOAD_REGISTER_IMM(count);
1369 *batch++ = i915_mmio_reg_offset(lri->reg);
1370 *batch++ = lri->value;
1371 } while (lri++, --count);
1377 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1379 static const struct lri lri[] = {
1380 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1382 COMMON_SLICE_CHICKEN2,
1383 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1390 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1391 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1397 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1398 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1402 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1404 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1405 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1407 /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */
1408 batch = gen8_emit_pipe_control(batch,
1409 PIPE_CONTROL_FLUSH_L3 |
1410 PIPE_CONTROL_STORE_DATA_INDEX |
1411 PIPE_CONTROL_CS_STALL |
1412 PIPE_CONTROL_QW_WRITE,
1413 LRC_PPHWSP_SCRATCH_ADDR);
1415 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1417 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1418 if (HAS_POOLED_EU(engine->i915)) {
1420 * EU pool configuration is setup along with golden context
1421 * during context initialization. This value depends on
1422 * device type (2x6 or 3x6) and needs to be updated based
1423 * on which subslice is disabled especially for 2x6
1424 * devices, however it is safe to load default
1425 * configuration of 3x6 device instead of masking off
1426 * corresponding bits because HW ignores bits of a disabled
1427 * subslice and drops down to appropriate config. Please
1428 * see render_state_setup() in i915_gem_render_state.c for
1429 * possible configurations, to avoid duplication they are
1430 * not shown here again.
1432 *batch++ = GEN9_MEDIA_POOL_STATE;
1433 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1434 *batch++ = 0x00777000;
1440 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1442 /* Pad to end of cacheline */
1443 while ((unsigned long)batch % CACHELINE_BYTES)
1449 #define CTX_WA_BB_SIZE (PAGE_SIZE)
1451 static int lrc_create_wa_ctx(struct intel_engine_cs *engine)
1453 struct drm_i915_gem_object *obj;
1454 struct i915_vma *vma;
1457 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_SIZE);
1459 return PTR_ERR(obj);
1461 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1467 engine->wa_ctx.vma = vma;
1471 i915_gem_object_put(obj);
1475 void lrc_fini_wa_ctx(struct intel_engine_cs *engine)
1477 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1480 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1482 void lrc_init_wa_ctx(struct intel_engine_cs *engine)
1484 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1485 struct i915_wa_ctx_bb *wa_bb[] = {
1486 &wa_ctx->indirect_ctx, &wa_ctx->per_ctx
1488 wa_bb_func_t wa_bb_fn[ARRAY_SIZE(wa_bb)];
1489 struct i915_gem_ww_ctx ww;
1490 void *batch, *batch_ptr;
1494 if (engine->class != RENDER_CLASS)
1497 switch (GRAPHICS_VER(engine->i915)) {
1502 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1506 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1510 MISSING_CASE(GRAPHICS_VER(engine->i915));
1514 err = lrc_create_wa_ctx(engine);
1517 * We continue even if we fail to initialize WA batch
1518 * because we only expect rare glitches but nothing
1519 * critical to prevent us from using GPU
1521 drm_err(&engine->i915->drm,
1522 "Ignoring context switch w/a allocation error:%d\n",
1527 if (!engine->wa_ctx.vma)
1530 i915_gem_ww_ctx_init(&ww, true);
1532 err = i915_gem_object_lock(wa_ctx->vma->obj, &ww);
1534 err = i915_ggtt_pin(wa_ctx->vma, &ww, 0, PIN_HIGH);
1538 batch = i915_gem_object_pin_map(wa_ctx->vma->obj, I915_MAP_WB);
1539 if (IS_ERR(batch)) {
1540 err = PTR_ERR(batch);
1545 * Emit the two workaround batch buffers, recording the offset from the
1546 * start of the workaround batch buffer object for each and their
1550 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1551 wa_bb[i]->offset = batch_ptr - batch;
1552 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1553 CACHELINE_BYTES))) {
1558 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1559 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1561 GEM_BUG_ON(batch_ptr - batch > CTX_WA_BB_SIZE);
1563 __i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch);
1564 __i915_gem_object_release_map(wa_ctx->vma->obj);
1566 /* Verify that we can handle failure to setup the wa_ctx */
1568 err = i915_inject_probe_error(engine->i915, -ENODEV);
1572 i915_vma_unpin(wa_ctx->vma);
1574 if (err == -EDEADLK) {
1575 err = i915_gem_ww_ctx_backoff(&ww);
1579 i915_gem_ww_ctx_fini(&ww);
1582 i915_vma_put(engine->wa_ctx.vma);
1584 /* Clear all flags to prevent further use */
1585 memset(wa_ctx, 0, sizeof(*wa_ctx));
1589 static void st_update_runtime_underflow(struct intel_context *ce, s32 dt)
1591 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1592 ce->runtime.num_underflow++;
1593 ce->runtime.max_underflow = max_t(u32, ce->runtime.max_underflow, -dt);
1597 void lrc_update_runtime(struct intel_context *ce)
1602 if (intel_context_is_barrier(ce))
1605 old = ce->runtime.last;
1606 ce->runtime.last = lrc_get_runtime(ce);
1607 dt = ce->runtime.last - old;
1609 if (unlikely(dt < 0)) {
1610 CE_TRACE(ce, "runtime underflow: last=%u, new=%u, delta=%d\n",
1611 old, ce->runtime.last, dt);
1612 st_update_runtime_underflow(ce, dt);
1616 ewma_runtime_add(&ce->runtime.avg, dt);
1617 ce->runtime.total += dt;
1620 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1621 #include "selftest_lrc.c"