1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2020 Intel Corporation
5 * Please try to maintain the following order within this file unless it makes
6 * sense to do otherwise. From top to bottom:
8 * 2. #defines, and macros
9 * 3. structure definitions
10 * 4. function prototypes
12 * Within each section, please try to order by generation in ascending order,
13 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
16 #ifndef __INTEL_GTT_H__
17 #define __INTEL_GTT_H__
19 #include <linux/io-mapping.h>
20 #include <linux/kref.h>
22 #include <linux/pagevec.h>
23 #include <linux/scatterlist.h>
24 #include <linux/workqueue.h>
26 #include <drm/drm_mm.h>
28 #include "gt/intel_reset.h"
29 #include "i915_selftest.h"
30 #include "i915_vma_types.h"
32 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
34 #if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT)
35 #define DBG(...) trace_printk(__VA_ARGS__)
40 #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation */
42 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
43 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
44 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
46 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
47 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
49 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
51 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
53 #define I915_FENCE_REG_NONE -1
54 #define I915_MAX_NUM_FENCES 32
55 /* 32 fences + sign bit for FENCE_REG_NONE */
56 #define I915_MAX_NUM_FENCE_BITS 6
58 typedef u32 gen6_pte_t;
59 typedef u64 gen8_pte_t;
61 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
63 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
64 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
66 #define I915_PDE_MASK (I915_PDES - 1)
68 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
69 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
70 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
71 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
72 #define GEN6_PTE_CACHE_LLC (2 << 1)
73 #define GEN6_PTE_UNCACHED (1 << 1)
74 #define GEN6_PTE_VALID REG_BIT(0)
76 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
77 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
78 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
79 #define GEN6_PDE_SHIFT 22
80 #define GEN6_PDE_VALID REG_BIT(0)
81 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
83 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
85 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
86 #define BYT_PTE_WRITEABLE REG_BIT(1)
88 #define GEN12_PPGTT_PTE_LM BIT_ULL(11)
91 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
92 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
94 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
95 (((bits) & 0x8) << (11 - 3)))
96 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
97 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
98 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
99 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
100 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
101 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
102 #define HSW_PTE_UNCACHED (0)
103 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
104 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
107 * GEN8 32b style address is defined as a 3 level page table:
108 * 31:30 | 29:21 | 20:12 | 11:0
109 * PDPE | PDE | PTE | offset
110 * The difference as compared to normal x86 3 level page table is the PDPEs are
111 * programmed via register.
113 * GEN8 48b style address is defined as a 4 level page table:
114 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
115 * PML4E | PDPE | PDE | PTE | offset
117 #define GEN8_3LVL_PDPES 4
119 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
120 #define PPAT_CACHED_PDE 0 /* WB LLC */
121 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
122 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
124 #define CHV_PPAT_SNOOP REG_BIT(6)
125 #define GEN8_PPAT_AGE(x) ((x)<<4)
126 #define GEN8_PPAT_LLCeLLC (3<<2)
127 #define GEN8_PPAT_LLCELLC (2<<2)
128 #define GEN8_PPAT_LLC (1<<2)
129 #define GEN8_PPAT_WB (3<<0)
130 #define GEN8_PPAT_WT (2<<0)
131 #define GEN8_PPAT_WC (1<<0)
132 #define GEN8_PPAT_UC (0<<0)
133 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
134 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
136 #define GEN8_PDE_IPS_64K BIT(11)
137 #define GEN8_PDE_PS_2M BIT(7)
139 enum i915_cache_level;
141 struct drm_i915_file_private;
142 struct drm_i915_gem_object;
143 struct i915_fence_reg;
147 #define for_each_sgt_daddr(__dp, __iter, __sgt) \
148 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
150 struct i915_page_table {
151 struct drm_i915_gem_object *base;
154 struct i915_page_table *stash;
158 struct i915_page_directory {
159 struct i915_page_table pt;
164 #define __px_choose_expr(x, type, expr, other) \
165 __builtin_choose_expr( \
166 __builtin_types_compatible_p(typeof(x), type) || \
167 __builtin_types_compatible_p(typeof(x), const type), \
168 ({ type __x = (type)(x); expr; }), \
171 #define px_base(px) \
172 __px_choose_expr(px, struct drm_i915_gem_object *, __x, \
173 __px_choose_expr(px, struct i915_page_table *, __x->base, \
174 __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \
177 struct page *__px_page(struct drm_i915_gem_object *p);
178 dma_addr_t __px_dma(struct drm_i915_gem_object *p);
179 #define px_dma(px) (__px_dma(px_base(px)))
182 __px_choose_expr(px, struct i915_page_table *, __x, \
183 __px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
185 #define px_used(px) (&px_pt(px)->used)
187 struct i915_vm_pt_stash {
188 /* preallocated chains of page tables/directories */
189 struct i915_page_table *pt[2];
192 struct i915_vma_ops {
193 /* Map an object into an address space with the given cache flags. */
194 void (*bind_vma)(struct i915_address_space *vm,
195 struct i915_vm_pt_stash *stash,
196 struct i915_vma *vma,
197 enum i915_cache_level cache_level,
200 * Unmap an object from an address space. This usually consists of
201 * setting the valid PTE entries to a reserved scratch page.
203 void (*unbind_vma)(struct i915_address_space *vm,
204 struct i915_vma *vma);
206 int (*set_pages)(struct i915_vma *vma);
207 void (*clear_pages)(struct i915_vma *vma);
210 struct i915_address_space {
216 struct drm_i915_private *i915;
219 * Every address space belongs to a struct file - except for the global
220 * GTT that is owned by the driver (and so @file is set to NULL). In
221 * principle, no information should leak from one context to another
222 * (or between files/processes etc) unless explicitly shared by the
223 * owner. Tracking the owner is important in order to free up per-file
224 * objects along with the file, to aide resource tracking, and to
227 struct drm_i915_file_private *file;
228 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
229 u64 reserved; /* size addr space reserved */
231 unsigned int bind_async_flags;
234 * Each active user context has its own address space (in full-ppgtt).
235 * Since the vm may be shared between multiple contexts, we count how
236 * many contexts keep us "open". Once open hits zero, we are closed
237 * and do not allow any new attachments, and proceed to shutdown our
238 * vma and page directories.
242 struct mutex mutex; /* protects vma and our lists */
243 #define VM_CLASS_GGTT 0
244 #define VM_CLASS_PPGTT 1
246 struct drm_i915_gem_object *scratch[4];
248 * List of vma currently bound.
250 struct list_head bound_list;
255 /* Some systems support read-only mappings for GGTT and/or PPGTT */
256 bool has_read_only:1;
262 struct drm_i915_gem_object *
263 (*alloc_pt_dma)(struct i915_address_space *vm, int sz);
265 u64 (*pte_encode)(dma_addr_t addr,
266 enum i915_cache_level level,
267 u32 flags); /* Create a valid PTE */
268 #define PTE_READ_ONLY BIT(0)
269 #define PTE_LM BIT(1)
271 void (*allocate_va_range)(struct i915_address_space *vm,
272 struct i915_vm_pt_stash *stash,
273 u64 start, u64 length);
274 void (*clear_range)(struct i915_address_space *vm,
275 u64 start, u64 length);
276 void (*insert_page)(struct i915_address_space *vm,
279 enum i915_cache_level cache_level,
281 void (*insert_entries)(struct i915_address_space *vm,
282 struct i915_vma *vma,
283 enum i915_cache_level cache_level,
285 void (*cleanup)(struct i915_address_space *vm);
287 struct i915_vma_ops vma_ops;
289 I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
290 I915_SELFTEST_DECLARE(bool scrub_64K);
294 * The Graphics Translation Table is the way in which GEN hardware translates a
295 * Graphics Virtual Address into a Physical Address. In addition to the normal
296 * collateral associated with any va->pa translations GEN hardware also has a
297 * portion of the GTT which can be mapped by the CPU and remain both coherent
298 * and correct (in cases like swizzling). That region is referred to as GMADR in
302 struct i915_address_space vm;
304 struct io_mapping iomap; /* Mapping to our CPU mappable region */
305 struct resource gmadr; /* GMADR resource */
306 resource_size_t mappable_end; /* End offset that we can CPU map */
308 /** "Graphics Stolen Memory" holds the global PTEs */
310 void (*invalidate)(struct i915_ggtt *ggtt);
312 /** PPGTT used for aliasing the PPGTT with the GTT */
313 struct i915_ppgtt *alias;
319 /** Bit 6 swizzling required for X tiling */
321 /** Bit 6 swizzling required for Y tiling */
326 unsigned int num_fences;
327 struct i915_fence_reg *fence_regs;
328 struct list_head fence_list;
331 * List of all objects in gtt_space, currently mmaped by userspace.
332 * All objects within this list must also be on bound_list.
334 struct list_head userfault_list;
336 /* Manual runtime pm autosuspend delay for user GGTT mmaps */
337 struct intel_wakeref_auto userfault_wakeref;
339 struct mutex error_mutex;
340 struct drm_mm_node error_capture;
341 struct drm_mm_node uc_fw;
345 struct i915_address_space vm;
347 struct i915_page_directory *pd;
350 #define i915_is_ggtt(vm) ((vm)->is_ggtt)
353 i915_vm_is_4lvl(const struct i915_address_space *vm)
355 return (vm->total - 1) >> 32;
359 i915_vm_has_scratch_64K(struct i915_address_space *vm)
361 return vm->scratch_order == get_order(I915_GTT_PAGE_SIZE_64K);
365 i915_vm_has_cache_coloring(struct i915_address_space *vm)
367 return i915_is_ggtt(vm) && vm->mm.color_adjust;
370 static inline struct i915_ggtt *
371 i915_vm_to_ggtt(struct i915_address_space *vm)
373 BUILD_BUG_ON(offsetof(struct i915_ggtt, vm));
374 GEM_BUG_ON(!i915_is_ggtt(vm));
375 return container_of(vm, struct i915_ggtt, vm);
378 static inline struct i915_ppgtt *
379 i915_vm_to_ppgtt(struct i915_address_space *vm)
381 BUILD_BUG_ON(offsetof(struct i915_ppgtt, vm));
382 GEM_BUG_ON(i915_is_ggtt(vm));
383 return container_of(vm, struct i915_ppgtt, vm);
386 static inline struct i915_address_space *
387 i915_vm_get(struct i915_address_space *vm)
393 void i915_vm_release(struct kref *kref);
395 static inline void i915_vm_put(struct i915_address_space *vm)
397 kref_put(&vm->ref, i915_vm_release);
400 static inline struct i915_address_space *
401 i915_vm_open(struct i915_address_space *vm)
403 GEM_BUG_ON(!atomic_read(&vm->open));
404 atomic_inc(&vm->open);
405 return i915_vm_get(vm);
409 i915_vm_tryopen(struct i915_address_space *vm)
411 if (atomic_add_unless(&vm->open, 1, 0))
412 return i915_vm_get(vm);
417 void __i915_vm_close(struct i915_address_space *vm);
420 i915_vm_close(struct i915_address_space *vm)
422 GEM_BUG_ON(!atomic_read(&vm->open));
428 void i915_address_space_init(struct i915_address_space *vm, int subclass);
429 void i915_address_space_fini(struct i915_address_space *vm);
431 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
433 const u32 mask = NUM_PTE(pde_shift) - 1;
435 return (address >> PAGE_SHIFT) & mask;
439 * Helper to counts the number of PTEs within the given length. This count
440 * does not cross a page table boundary, so the max value would be
441 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
443 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
445 const u64 mask = ~((1ULL << pde_shift) - 1);
448 GEM_BUG_ON(length == 0);
449 GEM_BUG_ON(offset_in_page(addr | length));
453 if ((addr & mask) != (end & mask))
454 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
456 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
459 static inline u32 i915_pde_index(u64 addr, u32 shift)
461 return (addr >> shift) & I915_PDE_MASK;
464 static inline struct i915_page_table *
465 i915_pt_entry(const struct i915_page_directory * const pd,
466 const unsigned short n)
471 static inline struct i915_page_directory *
472 i915_pd_entry(const struct i915_page_directory * const pdp,
473 const unsigned short n)
475 return pdp->entry[n];
478 static inline dma_addr_t
479 i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
481 struct i915_page_table *pt = ppgtt->pd->entry[n];
483 return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
486 void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
488 int i915_ggtt_probe_hw(struct drm_i915_private *i915);
489 int i915_ggtt_init_hw(struct drm_i915_private *i915);
490 int i915_ggtt_enable_hw(struct drm_i915_private *i915);
491 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
492 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
493 int i915_init_ggtt(struct drm_i915_private *i915);
494 void i915_ggtt_driver_release(struct drm_i915_private *i915);
496 static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
498 return ggtt->mappable_end > 0;
501 int i915_ppgtt_init_hw(struct intel_gt *gt);
503 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
505 void i915_ggtt_suspend(struct i915_ggtt *gtt);
506 void i915_ggtt_resume(struct i915_ggtt *ggtt);
508 #define kmap_atomic_px(px) kmap_atomic(__px_page(px_base(px)))
511 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count);
513 #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
514 #define fill32_px(px, v) do { \
515 u64 v__ = lower_32_bits(v); \
516 fill_px((px), v__ << 32 | v__); \
519 int setup_scratch_page(struct i915_address_space *vm);
520 void free_scratch(struct i915_address_space *vm);
522 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz);
523 struct i915_page_table *alloc_pt(struct i915_address_space *vm);
524 struct i915_page_directory *alloc_pd(struct i915_address_space *vm);
525 struct i915_page_directory *__alloc_pd(int npde);
527 int pin_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj);
529 void free_px(struct i915_address_space *vm,
530 struct i915_page_table *pt, int lvl);
531 #define free_pt(vm, px) free_px(vm, px, 0)
532 #define free_pd(vm, px) free_px(vm, px_pt(px), 1)
535 __set_pd_entry(struct i915_page_directory * const pd,
536 const unsigned short idx,
537 struct i915_page_table *pt,
538 u64 (*encode)(const dma_addr_t, const enum i915_cache_level));
540 #define set_pd_entry(pd, idx, to) \
541 __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode)
544 clear_pd_entry(struct i915_page_directory * const pd,
545 const unsigned short idx,
546 const struct drm_i915_gem_object * const scratch);
549 release_pd_entry(struct i915_page_directory * const pd,
550 const unsigned short idx,
551 struct i915_page_table * const pt,
552 const struct drm_i915_gem_object * const scratch);
553 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt);
555 int ggtt_set_pages(struct i915_vma *vma);
556 int ppgtt_set_pages(struct i915_vma *vma);
557 void clear_pages(struct i915_vma *vma);
559 void ppgtt_bind_vma(struct i915_address_space *vm,
560 struct i915_vm_pt_stash *stash,
561 struct i915_vma *vma,
562 enum i915_cache_level cache_level,
564 void ppgtt_unbind_vma(struct i915_address_space *vm,
565 struct i915_vma *vma);
567 void gtt_write_workarounds(struct intel_gt *gt);
569 void setup_private_pat(struct intel_uncore *uncore);
571 int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
572 struct i915_vm_pt_stash *stash,
574 int i915_vm_pin_pt_stash(struct i915_address_space *vm,
575 struct i915_vm_pt_stash *stash);
576 void i915_vm_free_pt_stash(struct i915_address_space *vm,
577 struct i915_vm_pt_stash *stash);
580 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size);
582 static inline struct sgt_dma {
583 struct scatterlist *sg;
585 } sgt_dma(struct i915_vma *vma) {
586 struct scatterlist *sg = vma->pages->sgl;
587 dma_addr_t addr = sg_dma_address(sg);
589 return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };