1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include <linux/slab.h> /* fault-inject.h is not standalone! */
8 #include <linux/fault-inject.h>
10 #include "gem/i915_gem_lmem.h"
11 #include "i915_trace.h"
13 #include "intel_gtt.h"
15 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
17 struct drm_i915_gem_object *obj;
20 * To avoid severe over-allocation when dealing with min_page_size
21 * restrictions, we override that behaviour here by allowing an object
22 * size and page layout which can be smaller. In practice this should be
23 * totally fine, since GTT paging structures are not typically inserted
26 * Note that we also hit this path for the scratch page, and for this
27 * case it might need to be 64K, but that should work fine here since we
28 * used the passed in size for the page size, which should ensure it
29 * also has the same alignment.
31 obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
33 * Ensure all paging structures for this vm share the same dma-resv
34 * object underneath, with the idea that one object_lock() will lock
38 obj->base.resv = i915_vm_resv_get(vm);
39 obj->shares_resv_from = vm;
45 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)
47 struct drm_i915_gem_object *obj;
49 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
50 i915_gem_shrink_all(vm->i915);
52 obj = i915_gem_object_create_internal(vm->i915, sz);
54 * Ensure all paging structures for this vm share the same dma-resv
55 * object underneath, with the idea that one object_lock() will lock
59 obj->base.resv = i915_vm_resv_get(vm);
60 obj->shares_resv_from = vm;
66 int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
68 enum i915_map_type type;
71 type = i915_coherent_map_type(vm->i915, obj, true);
72 vaddr = i915_gem_object_pin_map_unlocked(obj, type);
74 return PTR_ERR(vaddr);
76 i915_gem_object_make_unshrinkable(obj);
80 int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
82 enum i915_map_type type;
85 type = i915_coherent_map_type(vm->i915, obj, true);
86 vaddr = i915_gem_object_pin_map(obj, type);
88 return PTR_ERR(vaddr);
90 i915_gem_object_make_unshrinkable(obj);
94 void __i915_vm_close(struct i915_address_space *vm)
96 struct i915_vma *vma, *vn;
98 if (!atomic_dec_and_mutex_lock(&vm->open, &vm->mutex))
101 list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
102 struct drm_i915_gem_object *obj = vma->obj;
104 /* Keep the obj (and hence the vma) alive as _we_ destroy it */
105 if (!kref_get_unless_zero(&obj->base.refcount))
108 atomic_and(~I915_VMA_PIN_MASK, &vma->flags);
109 WARN_ON(__i915_vma_unbind(vma));
112 i915_gem_object_put(obj);
114 GEM_BUG_ON(!list_empty(&vm->bound_list));
116 mutex_unlock(&vm->mutex);
119 /* lock the vm into the current ww, if we lock one, we lock all */
120 int i915_vm_lock_objects(struct i915_address_space *vm,
121 struct i915_gem_ww_ctx *ww)
123 if (vm->scratch[0]->base.resv == &vm->_resv) {
124 return i915_gem_object_lock(vm->scratch[0], ww);
126 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
128 /* We borrowed the scratch page from ggtt, take the top level object */
129 return i915_gem_object_lock(ppgtt->pd->pt.base, ww);
133 void i915_address_space_fini(struct i915_address_space *vm)
135 drm_mm_takedown(&vm->mm);
136 mutex_destroy(&vm->mutex);
140 * i915_vm_resv_release - Final struct i915_address_space destructor
141 * @kref: Pointer to the &i915_address_space.resv_ref member.
143 * This function is called when the last lock sharer no longer shares the
144 * &i915_address_space._resv lock.
146 void i915_vm_resv_release(struct kref *kref)
148 struct i915_address_space *vm =
149 container_of(kref, typeof(*vm), resv_ref);
151 dma_resv_fini(&vm->_resv);
155 static void __i915_vm_release(struct work_struct *work)
157 struct i915_address_space *vm =
158 container_of(work, struct i915_address_space, rcu.work);
161 i915_address_space_fini(vm);
163 i915_vm_resv_put(vm);
166 void i915_vm_release(struct kref *kref)
168 struct i915_address_space *vm =
169 container_of(kref, struct i915_address_space, ref);
171 GEM_BUG_ON(i915_is_ggtt(vm));
172 trace_i915_ppgtt_release(vm);
174 queue_rcu_work(vm->i915->wq, &vm->rcu);
177 void i915_address_space_init(struct i915_address_space *vm, int subclass)
182 * Special case for GGTT that has already done an early
185 if (!kref_read(&vm->resv_ref))
186 kref_init(&vm->resv_ref);
188 INIT_RCU_WORK(&vm->rcu, __i915_vm_release);
189 atomic_set(&vm->open, 1);
192 * The vm->mutex must be reclaim safe (for use in the shrinker).
193 * Do a dummy acquire now under fs_reclaim so that any allocation
194 * attempt holding the lock is immediately reported by lockdep.
196 mutex_init(&vm->mutex);
197 lockdep_set_subclass(&vm->mutex, subclass);
199 if (!intel_vm_no_concurrent_access_wa(vm->i915)) {
200 i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex);
203 * CHV + BXT VTD workaround use stop_machine(),
204 * which is allowed to allocate memory. This means &vm->mutex
205 * is the outer lock, and in theory we can allocate memory inside
206 * it through stop_machine().
208 * Add the annotation for this, we use trylock in shrinker.
210 mutex_acquire(&vm->mutex.dep_map, 0, 0, _THIS_IP_);
211 might_alloc(GFP_KERNEL);
212 mutex_release(&vm->mutex.dep_map, _THIS_IP_);
214 dma_resv_init(&vm->_resv);
216 GEM_BUG_ON(!vm->total);
217 drm_mm_init(&vm->mm, 0, vm->total);
218 vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
220 INIT_LIST_HEAD(&vm->bound_list);
223 void clear_pages(struct i915_vma *vma)
225 GEM_BUG_ON(!vma->pages);
227 if (vma->pages != vma->obj->mm.pages) {
228 sg_free_table(vma->pages);
233 memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
236 void *__px_vaddr(struct drm_i915_gem_object *p)
238 enum i915_map_type type;
240 GEM_BUG_ON(!i915_gem_object_has_pages(p));
241 return page_unpack_bits(p->mm.mapping, &type);
244 dma_addr_t __px_dma(struct drm_i915_gem_object *p)
246 GEM_BUG_ON(!i915_gem_object_has_pages(p));
247 return sg_dma_address(p->mm.pages->sgl);
250 struct page *__px_page(struct drm_i915_gem_object *p)
252 GEM_BUG_ON(!i915_gem_object_has_pages(p));
253 return sg_page(p->mm.pages->sgl);
257 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
259 void *vaddr = __px_vaddr(p);
261 memset64(vaddr, val, count);
262 clflush_cache_range(vaddr, PAGE_SIZE);
265 static void poison_scratch_page(struct drm_i915_gem_object *scratch)
267 void *vaddr = __px_vaddr(scratch);
271 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
274 memset(vaddr, val, scratch->base.size);
277 int setup_scratch_page(struct i915_address_space *vm)
282 * In order to utilize 64K pages for an object with a size < 2M, we will
283 * need to support a 64K scratch page, given that every 16th entry for a
284 * page-table operating in 64K mode must point to a properly aligned 64K
285 * region, including any PTEs which happen to point to scratch.
287 * This is only relevant for the 48b PPGTT where we support
288 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the
289 * scratch (read-only) between all vm, we create one 64k scratch page
292 size = I915_GTT_PAGE_SIZE_4K;
293 if (i915_vm_is_4lvl(vm) &&
294 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K))
295 size = I915_GTT_PAGE_SIZE_64K;
298 struct drm_i915_gem_object *obj;
300 obj = vm->alloc_pt_dma(vm, size);
304 if (map_pt_dma(vm, obj))
307 /* We need a single contiguous page for our scratch */
308 if (obj->mm.page_sizes.sg < size)
311 /* And it needs to be correspondingly aligned */
312 if (__px_dma(obj) & (size - 1))
316 * Use a non-zero scratch page for debugging.
318 * We want a value that should be reasonably obvious
319 * to spot in the error state, while also causing a GPU hang
320 * if executed. We prefer using a clear page in production, so
321 * should it ever be accidentally used, the effect should be
324 poison_scratch_page(obj);
326 vm->scratch[0] = obj;
327 vm->scratch_order = get_order(size);
331 i915_gem_object_put(obj);
333 if (size == I915_GTT_PAGE_SIZE_4K)
336 size = I915_GTT_PAGE_SIZE_4K;
340 void free_scratch(struct i915_address_space *vm)
344 for (i = 0; i <= vm->top; i++)
345 i915_gem_object_put(vm->scratch[i]);
348 void gtt_write_workarounds(struct intel_gt *gt)
350 struct drm_i915_private *i915 = gt->i915;
351 struct intel_uncore *uncore = gt->uncore;
354 * This function is for gtt related workarounds. This function is
355 * called on driver load and after a GPU reset, so you can place
356 * workarounds here even if they get overwritten by GPU reset.
358 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
359 if (IS_BROADWELL(i915))
360 intel_uncore_write(uncore,
362 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
363 else if (IS_CHERRYVIEW(i915))
364 intel_uncore_write(uncore,
366 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
367 else if (IS_GEN9_LP(i915))
368 intel_uncore_write(uncore,
370 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
371 else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11)
372 intel_uncore_write(uncore,
374 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
377 * To support 64K PTEs we need to first enable the use of the
378 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical
379 * mmio, otherwise the page-walker will simply ignore the IPS bit. This
380 * shouldn't be needed after GEN10.
382 * 64K pages were first introduced from BDW+, although technically they
383 * only *work* from gen9+. For pre-BDW we instead have the option for
384 * 32K pages, but we don't currently have any support for it in our
387 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
388 GRAPHICS_VER(i915) <= 10)
389 intel_uncore_rmw(uncore,
390 GEN8_GAMW_ECO_DEV_RW_IA,
392 GAMW_ECO_ENABLE_64K_IPS_FIELD);
394 if (IS_GRAPHICS_VER(i915, 8, 11)) {
395 bool can_use_gtt_cache = true;
398 * According to the BSpec if we use 2M/1G pages then we also
399 * need to disable the GTT cache. At least on BDW we can see
400 * visual corruption when using 2M pages, and not disabling the
403 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M))
404 can_use_gtt_cache = false;
406 /* WaGttCachingOffByDefault */
407 intel_uncore_write(uncore,
409 can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
410 drm_WARN_ON_ONCE(&i915->drm, can_use_gtt_cache &&
411 intel_uncore_read(uncore,
412 HSW_GTT_CACHE_EN) == 0);
416 static void tgl_setup_private_ppat(struct intel_uncore *uncore)
418 /* TGL doesn't support LLC or AGE settings */
419 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
420 intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
421 intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
422 intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
423 intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
424 intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
425 intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
426 intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
429 static void cnl_setup_private_ppat(struct intel_uncore *uncore)
431 intel_uncore_write(uncore,
433 GEN8_PPAT_WB | GEN8_PPAT_LLC);
434 intel_uncore_write(uncore,
436 GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
437 intel_uncore_write(uncore,
439 GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
440 intel_uncore_write(uncore,
443 intel_uncore_write(uncore,
445 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
446 intel_uncore_write(uncore,
448 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
449 intel_uncore_write(uncore,
451 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
452 intel_uncore_write(uncore,
454 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
458 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
459 * bits. When using advanced contexts each context stores its own PAT, but
460 * writing this data shouldn't be harmful even in those cases.
462 static void bdw_setup_private_ppat(struct intel_uncore *uncore)
464 struct drm_i915_private *i915 = uncore->i915;
467 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
468 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
469 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
470 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
471 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
472 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
473 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
475 /* for scanout with eLLC */
476 if (GRAPHICS_VER(i915) >= 9)
477 pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
479 pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
481 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
482 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
485 static void chv_setup_private_ppat(struct intel_uncore *uncore)
490 * Map WB on BDW to snooped on CHV.
492 * Only the snoop bit has meaning for CHV, the rest is
495 * The hardware will never snoop for certain types of accesses:
496 * - CPU GTT (GMADR->GGTT->no snoop->memory)
497 * - PPGTT page tables
498 * - some other special cycles
500 * As with BDW, we also need to consider the following for GT accesses:
501 * "For GGTT, there is NO pat_sel[2:0] from the entry,
502 * so RTL will always use the value corresponding to
504 * Which means we must set the snoop bit in PAT entry 0
505 * in order to keep the global status page working.
508 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
512 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
513 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
514 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
515 GEN8_PPAT(7, CHV_PPAT_SNOOP);
517 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
518 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
521 void setup_private_pat(struct intel_uncore *uncore)
523 struct drm_i915_private *i915 = uncore->i915;
525 GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
527 if (GRAPHICS_VER(i915) >= 12)
528 tgl_setup_private_ppat(uncore);
529 else if (GRAPHICS_VER(i915) >= 10)
530 cnl_setup_private_ppat(uncore);
531 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
532 chv_setup_private_ppat(uncore);
534 bdw_setup_private_ppat(uncore);
538 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size)
540 struct drm_i915_gem_object *obj;
541 struct i915_vma *vma;
543 obj = i915_gem_object_create_internal(vm->i915, PAGE_ALIGN(size));
545 return ERR_CAST(obj);
547 i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
549 vma = i915_vma_instance(obj, vm, NULL);
551 i915_gem_object_put(obj);
559 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size)
561 struct i915_vma *vma;
564 vma = __vm_create_scratch_for_read(vm, size);
568 err = i915_vma_pin(vma, 0, 0,
569 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
578 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
579 #include "selftests/mock_gtt.c"