1 // SPDX-License-Identifier: MIT
3 * Copyright © 2019 Intel Corporation
6 #include <linux/suspend.h>
9 #include "i915_globals.h"
10 #include "i915_params.h"
11 #include "intel_context.h"
12 #include "intel_engine_pm.h"
14 #include "intel_gt_clock_utils.h"
15 #include "intel_gt_pm.h"
16 #include "intel_gt_requests.h"
17 #include "intel_llc.h"
19 #include "intel_rc6.h"
20 #include "intel_rps.h"
21 #include "intel_wakeref.h"
23 static void user_forcewake(struct intel_gt *gt, bool suspend)
25 int count = atomic_read(>->user_wakeref);
27 /* Inside suspend/resume so single threaded, no races to worry about. */
33 GEM_BUG_ON(count > atomic_read(>->wakeref.count));
34 atomic_sub(count, >->wakeref.count);
36 atomic_add(count, >->wakeref.count);
41 static void runtime_begin(struct intel_gt *gt)
44 write_seqcount_begin(>->stats.lock);
45 gt->stats.start = ktime_get();
46 gt->stats.active = true;
47 write_seqcount_end(>->stats.lock);
51 static void runtime_end(struct intel_gt *gt)
54 write_seqcount_begin(>->stats.lock);
55 gt->stats.active = false;
57 ktime_add(gt->stats.total,
58 ktime_sub(ktime_get(), gt->stats.start));
59 write_seqcount_end(>->stats.lock);
63 static int __gt_unpark(struct intel_wakeref *wf)
65 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
66 struct drm_i915_private *i915 = gt->i915;
70 i915_globals_unpark();
73 * It seems that the DMC likes to transition between the DC states a lot
74 * when there are no connected displays (no active power domains) during
77 * This activity has negative impact on the performance of the chip with
78 * huge latencies observed in the interrupt handler and elsewhere.
80 * Work around it by grabbing a GT IRQ power domain whilst there is any
81 * GT activity, preventing any DC state transitions.
83 gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
84 GEM_BUG_ON(!gt->awake);
86 intel_rc6_unpark(>->rc6);
87 intel_rps_unpark(>->rps);
88 i915_pmu_gt_unparked(i915);
90 intel_gt_unpark_requests(gt);
96 static int __gt_park(struct intel_wakeref *wf)
98 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
99 intel_wakeref_t wakeref = fetch_and_zero(>->awake);
100 struct drm_i915_private *i915 = gt->i915;
105 intel_gt_park_requests(gt);
108 i915_pmu_gt_parked(i915);
109 intel_rps_park(>->rps);
110 intel_rc6_park(>->rc6);
112 /* Everything switched off, flush any residual interrupt just in case */
113 intel_synchronize_irq(i915);
115 /* Defer dropping the display power well for 100ms, it's slow! */
116 GEM_BUG_ON(!wakeref);
117 intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref);
124 static const struct intel_wakeref_ops wf_ops = {
129 void intel_gt_pm_init_early(struct intel_gt *gt)
131 intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
132 seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
135 void intel_gt_pm_init(struct intel_gt *gt)
138 * Enabling power-management should be "self-healing". If we cannot
139 * enable a feature, simply leave it disabled with a notice to the
142 intel_rc6_init(>->rc6);
143 intel_rps_init(>->rps);
146 static bool reset_engines(struct intel_gt *gt)
148 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
151 return __intel_gt_reset(gt, ALL_ENGINES) == 0;
154 static void gt_sanitize(struct intel_gt *gt, bool force)
156 struct intel_engine_cs *engine;
157 enum intel_engine_id id;
158 intel_wakeref_t wakeref;
160 GT_TRACE(gt, "force:%s", yesno(force));
162 /* Use a raw wakeref to avoid calling intel_display_power_get early */
163 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
164 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
166 intel_gt_check_clock_frequency(gt);
169 * As we have just resumed the machine and woken the device up from
170 * deep PCI sleep (presumably D3_cold), assume the HW has been reset
171 * back to defaults, recovering from whatever wedged state we left it
172 * in and so worth trying to use the device once more.
174 if (intel_gt_is_wedged(gt))
175 intel_gt_unset_wedged(gt);
177 intel_uc_sanitize(>->uc);
179 for_each_engine(engine, gt, id)
180 if (engine->reset.prepare)
181 engine->reset.prepare(engine);
183 intel_uc_reset_prepare(>->uc);
185 for_each_engine(engine, gt, id)
186 if (engine->sanitize)
187 engine->sanitize(engine);
189 if (reset_engines(gt) || force) {
190 for_each_engine(engine, gt, id)
191 __intel_engine_reset(engine, false);
194 for_each_engine(engine, gt, id)
195 if (engine->reset.finish)
196 engine->reset.finish(engine);
198 intel_rps_sanitize(>->rps);
200 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
201 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
204 void intel_gt_pm_fini(struct intel_gt *gt)
206 intel_rc6_fini(>->rc6);
209 int intel_gt_resume(struct intel_gt *gt)
211 struct intel_engine_cs *engine;
212 enum intel_engine_id id;
215 err = intel_gt_has_unrecoverable_error(gt);
222 * After resume, we may need to poke into the pinned kernel
223 * contexts to paper over any damage caused by the sudden suspend.
224 * Only the kernel contexts should remain pinned over suspend,
225 * allowing us to fixup the user contexts on their first pin.
227 gt_sanitize(gt, true);
231 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
232 intel_rc6_sanitize(>->rc6);
233 if (intel_gt_is_wedged(gt)) {
238 /* Only when the HW is re-initialised, can we replay the requests */
239 err = intel_gt_init_hw(gt);
241 i915_probe_error(gt->i915,
242 "Failed to initialize GPU, declaring it wedged!\n");
246 intel_rps_enable(>->rps);
247 intel_llc_enable(>->llc);
249 for_each_engine(engine, gt, id) {
250 intel_engine_pm_get(engine);
252 engine->serial++; /* kernel context lost */
253 err = intel_engine_resume(engine);
255 intel_engine_pm_put(engine);
257 drm_err(>->i915->drm,
258 "Failed to restart %s (%d)\n",
264 intel_rc6_enable(>->rc6);
266 intel_uc_resume(>->uc);
268 user_forcewake(gt, false);
271 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
276 intel_gt_set_wedged(gt);
280 static void wait_for_suspend(struct intel_gt *gt)
282 if (!intel_gt_pm_is_awake(gt))
285 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
287 * Forcibly cancel outstanding work and leave
290 intel_gt_set_wedged(gt);
291 intel_gt_retire_requests(gt);
294 intel_gt_pm_wait_for_idle(gt);
297 void intel_gt_suspend_prepare(struct intel_gt *gt)
299 user_forcewake(gt, true);
300 wait_for_suspend(gt);
302 intel_uc_suspend(>->uc);
305 static suspend_state_t pm_suspend_target(void)
307 #if IS_ENABLED(CONFIG_SUSPEND) && IS_ENABLED(CONFIG_PM_SLEEP)
308 return pm_suspend_target_state;
310 return PM_SUSPEND_TO_IDLE;
314 void intel_gt_suspend_late(struct intel_gt *gt)
316 intel_wakeref_t wakeref;
318 /* We expect to be idle already; but also want to be independent */
319 wait_for_suspend(gt);
324 GEM_BUG_ON(gt->awake);
327 * On disabling the device, we want to turn off HW access to memory
328 * that we no longer own.
330 * However, not all suspend-states disable the device. S0 (s2idle)
331 * is effectively runtime-suspend, the device is left powered on
332 * but needs to be put into a low power state. We need to keep
333 * powermanagement enabled, but we also retain system state and so
334 * it remains safe to keep on using our allocated memory.
336 if (pm_suspend_target() == PM_SUSPEND_TO_IDLE)
339 with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
340 intel_rps_disable(>->rps);
341 intel_rc6_disable(>->rc6);
342 intel_llc_disable(>->llc);
345 gt_sanitize(gt, false);
350 void intel_gt_runtime_suspend(struct intel_gt *gt)
352 intel_uc_runtime_suspend(>->uc);
357 int intel_gt_runtime_resume(struct intel_gt *gt)
360 intel_gt_init_swizzling(gt);
361 intel_ggtt_restore_fences(gt->ggtt);
363 return intel_uc_runtime_resume(>->uc);
366 static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
368 ktime_t total = gt->stats.total;
370 if (gt->stats.active)
371 total = ktime_add(total,
372 ktime_sub(ktime_get(), gt->stats.start));
377 ktime_t intel_gt_get_awake_time(const struct intel_gt *gt)
383 seq = read_seqcount_begin(>->stats.lock);
384 total = __intel_gt_get_awake_time(gt);
385 } while (read_seqcount_retry(>->stats.lock, seq));
390 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
391 #include "selftest_gt_pm.c"