drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include <drm/intel-gtt.h>
   7
   8 #include "intel_gt_debugfs.h"
   9
  10 #include "gem/i915_gem_lmem.h"
  11 #include "i915_drv.h"
  12 #include "intel_context.h"
  13 #include "intel_gt.h"
  14 #include "intel_gt_buffer_pool.h"
  15 #include "intel_gt_clock_utils.h"
  16 #include "intel_gt_pm.h"
  17 #include "intel_gt_requests.h"
  18 #include "intel_migrate.h"
  19 #include "intel_mocs.h"
  20 #include "intel_pm.h"
  21 #include "intel_rc6.h"
  22 #include "intel_renderstate.h"
  23 #include "intel_rps.h"
  24 #include "intel_uncore.h"
  25 #include "shmem_utils.h"
  26 #include "pxp/intel_pxp.h"
  27
  28 void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  29 {
  30         spin_lock_init(&gt->irq_lock);
  31
  32         mutex_init(&gt->tlb_invalidate_lock);
  33
  34         INIT_LIST_HEAD(&gt->closed_vma);
  35         spin_lock_init(&gt->closed_lock);
  36
  37         init_llist_head(&gt->watchdog.list);
  38         INIT_WORK(&gt->watchdog.work, intel_gt_watchdog_work);
  39
  40         intel_gt_init_buffer_pool(gt);
  41         intel_gt_init_reset(gt);
  42         intel_gt_init_requests(gt);
  43         intel_gt_init_timelines(gt);
  44         intel_gt_pm_init_early(gt);
  45
  46         intel_uc_init_early(&gt->uc);
  47         intel_rps_init_early(&gt->rps);
  48 }
  49
  50 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  51 {
  52         gt->i915 = i915;
  53         gt->uncore = &i915->uncore;
  54 }
  55
  56 int intel_gt_probe_lmem(struct intel_gt *gt)
  57 {
  58         struct drm_i915_private *i915 = gt->i915;
  59         struct intel_memory_region *mem;
  60         int id;
  61         int err;
  62
  63         mem = intel_gt_setup_lmem(gt);
  64         if (mem == ERR_PTR(-ENODEV))
  65                 mem = intel_gt_setup_fake_lmem(gt);
  66         if (IS_ERR(mem)) {
  67                 err = PTR_ERR(mem);
  68                 if (err == -ENODEV)
  69                         return 0;
  70
  71                 drm_err(&i915->drm,
  72                         "Failed to setup region(%d) type=%d\n",
  73                         err, INTEL_MEMORY_LOCAL);
  74                 return err;
  75         }
  76
  77         id = INTEL_REGION_LMEM;
  78
  79         mem->id = id;
  80
  81         intel_memory_region_set_name(mem, "local%u", mem->instance);
  82
  83         GEM_BUG_ON(!HAS_REGION(i915, id));
  84         GEM_BUG_ON(i915->mm.regions[id]);
  85         i915->mm.regions[id] = mem;
  86
  87         return 0;
  88 }
  89
  90 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
  91 {
  92         gt->ggtt = ggtt;
  93 }
  94
  95 static const struct intel_mmio_range icl_l3bank_steering_table[] = {
  96         { 0x00B100, 0x00B3FF },
  97         {},
  98 };
  99
 100 static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
 101         { 0x004000, 0x004AFF },
 102         { 0x00C800, 0x00CFFF },
 103         { 0x00DD00, 0x00DDFF },
 104         { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
 105         {},
 106 };
 107
 108 static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
 109         { 0x00B000, 0x00B0FF },
 110         { 0x00D800, 0x00D8FF },
 111         {},
 112 };
 113
 114 static const struct intel_mmio_range dg2_lncf_steering_table[] = {
 115         { 0x00B000, 0x00B0FF },
 116         { 0x00D880, 0x00D8FF },
 117         {},
 118 };
 119
 120 static u16 slicemask(struct intel_gt *gt, int count)
 121 {
 122         u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
 123
 124         return intel_slicemask_from_dssmask(dss_mask, count);
 125 }
 126
 127 int intel_gt_init_mmio(struct intel_gt *gt)
 128 {
 129         struct drm_i915_private *i915 = gt->i915;
 130
 131         intel_gt_init_clock_frequency(gt);
 132
 133         intel_uc_init_mmio(&gt->uc);
 134         intel_sseu_info_init(gt);
 135
 136         /*
 137          * An mslice is unavailable only if both the meml3 for the slice is
 138          * disabled *and* all of the DSS in the slice (quadrant) are disabled.
 139          */
 140         if (HAS_MSLICES(i915))
 141                 gt->info.mslice_mask =
 142                         slicemask(gt, GEN_DSS_PER_MSLICE) |
 143                         (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 144                          GEN12_MEML3_EN_MASK);
 145
 146         if (IS_DG2(i915)) {
 147                 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 148                 gt->steering_table[LNCF] = dg2_lncf_steering_table;
 149         } else if (IS_XEHPSDV(i915)) {
 150                 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 151                 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
 152         } else if (GRAPHICS_VER(i915) >= 11 &&
 153                    GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
 154                 gt->steering_table[L3BANK] = icl_l3bank_steering_table;
 155                 gt->info.l3bank_mask =
 156                         ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 157                         GEN10_L3BANK_MASK;
 158         } else if (HAS_MSLICES(i915)) {
 159                 MISSING_CASE(INTEL_INFO(i915)->platform);
 160         }
 161
 162         return intel_engines_init_mmio(gt);
 163 }
 164
 165 static void init_unused_ring(struct intel_gt *gt, u32 base)
 166 {
 167         struct intel_uncore *uncore = gt->uncore;
 168
 169         intel_uncore_write(uncore, RING_CTL(base), 0);
 170         intel_uncore_write(uncore, RING_HEAD(base), 0);
 171         intel_uncore_write(uncore, RING_TAIL(base), 0);
 172         intel_uncore_write(uncore, RING_START(base), 0);
 173 }
 174
 175 static void init_unused_rings(struct intel_gt *gt)
 176 {
 177         struct drm_i915_private *i915 = gt->i915;
 178
 179         if (IS_I830(i915)) {
 180                 init_unused_ring(gt, PRB1_BASE);
 181                 init_unused_ring(gt, SRB0_BASE);
 182                 init_unused_ring(gt, SRB1_BASE);
 183                 init_unused_ring(gt, SRB2_BASE);
 184                 init_unused_ring(gt, SRB3_BASE);
 185         } else if (GRAPHICS_VER(i915) == 2) {
 186                 init_unused_ring(gt, SRB0_BASE);
 187                 init_unused_ring(gt, SRB1_BASE);
 188         } else if (GRAPHICS_VER(i915) == 3) {
 189                 init_unused_ring(gt, PRB1_BASE);
 190                 init_unused_ring(gt, PRB2_BASE);
 191         }
 192 }
 193
 194 int intel_gt_init_hw(struct intel_gt *gt)
 195 {
 196         struct drm_i915_private *i915 = gt->i915;
 197         struct intel_uncore *uncore = gt->uncore;
 198         int ret;
 199
 200         gt->last_init_time = ktime_get();
 201
 202         /* Double layer security blanket, see i915_gem_init() */
 203         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 204
 205         if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
 206                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 207
 208         if (IS_HASWELL(i915))
 209                 intel_uncore_write(uncore,
 210                                    MI_PREDICATE_RESULT_2,
 211                                    IS_HSW_GT3(i915) ?
 212                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 213
 214         /* Apply the GT workarounds... */
 215         intel_gt_apply_workarounds(gt);
 216         /* ...and determine whether they are sticking. */
 217         intel_gt_verify_workarounds(gt, "init");
 218
 219         intel_gt_init_swizzling(gt);
 220
 221         /*
 222          * At least 830 can leave some of the unused rings
 223          * "active" (ie. head != tail) after resume which
 224          * will prevent c3 entry. Makes sure all unused rings
 225          * are totally idle.
 226          */
 227         init_unused_rings(gt);
 228
 229         ret = i915_ppgtt_init_hw(gt);
 230         if (ret) {
 231                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 232                 goto out;
 233         }
 234
 235         /* We can't enable contexts until all firmware is loaded */
 236         ret = intel_uc_init_hw(&gt->uc);
 237         if (ret) {
 238                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 239                 goto out;
 240         }
 241
 242         intel_mocs_init(gt);
 243
 244 out:
 245         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 246         return ret;
 247 }
 248
 249 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 250 {
 251         intel_uncore_rmw(uncore, reg, 0, set);
 252 }
 253
 254 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
 255 {
 256         intel_uncore_rmw(uncore, reg, clr, 0);
 257 }
 258
 259 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 260 {
 261         intel_uncore_rmw(uncore, reg, 0, 0);
 262 }
 263
 264 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
 265 {
 266         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 267         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 268 }
 269
 270 void
 271 intel_gt_clear_error_registers(struct intel_gt *gt,
 272                                intel_engine_mask_t engine_mask)
 273 {
 274         struct drm_i915_private *i915 = gt->i915;
 275         struct intel_uncore *uncore = gt->uncore;
 276         u32 eir;
 277
 278         if (GRAPHICS_VER(i915) != 2)
 279                 clear_register(uncore, PGTBL_ER);
 280
 281         if (GRAPHICS_VER(i915) < 4)
 282                 clear_register(uncore, IPEIR(RENDER_RING_BASE));
 283         else
 284                 clear_register(uncore, IPEIR_I965);
 285
 286         clear_register(uncore, EIR);
 287         eir = intel_uncore_read(uncore, EIR);
 288         if (eir) {
 289                 /*
 290                  * some errors might have become stuck,
 291                  * mask them.
 292                  */
 293                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
 294                 rmw_set(uncore, EMR, eir);
 295                 intel_uncore_write(uncore, GEN2_IIR,
 296                                    I915_MASTER_ERROR_INTERRUPT);
 297         }
 298
 299         if (GRAPHICS_VER(i915) >= 12) {
 300                 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
 301                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 302         } else if (GRAPHICS_VER(i915) >= 8) {
 303                 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
 304                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 305         } else if (GRAPHICS_VER(i915) >= 6) {
 306                 struct intel_engine_cs *engine;
 307                 enum intel_engine_id id;
 308
 309                 for_each_engine_masked(engine, gt, engine_mask, id)
 310                         gen6_clear_engine_error_register(engine);
 311         }
 312 }
 313
 314 static void gen6_check_faults(struct intel_gt *gt)
 315 {
 316         struct intel_engine_cs *engine;
 317         enum intel_engine_id id;
 318         u32 fault;
 319
 320         for_each_engine(engine, gt, id) {
 321                 fault = GEN6_RING_FAULT_REG_READ(engine);
 322                 if (fault & RING_FAULT_VALID) {
 323                         drm_dbg(&engine->i915->drm, "Unexpected fault\n"
 324                                 "\tAddr: 0x%08lx\n"
 325                                 "\tAddress space: %s\n"
 326                                 "\tSource ID: %d\n"
 327                                 "\tType: %d\n",
 328                                 fault & PAGE_MASK,
 329                                 fault & RING_FAULT_GTTSEL_MASK ?
 330                                 "GGTT" : "PPGTT",
 331                                 RING_FAULT_SRCID(fault),
 332                                 RING_FAULT_FAULT_TYPE(fault));
 333                 }
 334         }
 335 }
 336
 337 static void gen8_check_faults(struct intel_gt *gt)
 338 {
 339         struct intel_uncore *uncore = gt->uncore;
 340         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 341         u32 fault;
 342
 343         if (GRAPHICS_VER(gt->i915) >= 12) {
 344                 fault_reg = GEN12_RING_FAULT_REG;
 345                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 346                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 347         } else {
 348                 fault_reg = GEN8_RING_FAULT_REG;
 349                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 350                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 351         }
 352
 353         fault = intel_uncore_read(uncore, fault_reg);
 354         if (fault & RING_FAULT_VALID) {
 355                 u32 fault_data0, fault_data1;
 356                 u64 fault_addr;
 357
 358                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 359                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 360
 361                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 362                              ((u64)fault_data0 << 12);
 363
 364                 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
 365                         "\tAddr: 0x%08x_%08x\n"
 366                         "\tAddress space: %s\n"
 367                         "\tEngine ID: %d\n"
 368                         "\tSource ID: %d\n"
 369                         "\tType: %d\n",
 370                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 371                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 372                         GEN8_RING_FAULT_ENGINE_ID(fault),
 373                         RING_FAULT_SRCID(fault),
 374                         RING_FAULT_FAULT_TYPE(fault));
 375         }
 376 }
 377
 378 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 379 {
 380         struct drm_i915_private *i915 = gt->i915;
 381
 382         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 383         if (GRAPHICS_VER(i915) >= 8)
 384                 gen8_check_faults(gt);
 385         else if (GRAPHICS_VER(i915) >= 6)
 386                 gen6_check_faults(gt);
 387         else
 388                 return;
 389
 390         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 391 }
 392
 393 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 394 {
 395         struct intel_uncore *uncore = gt->uncore;
 396         intel_wakeref_t wakeref;
 397
 398         /*
 399          * No actual flushing is required for the GTT write domain for reads
 400          * from the GTT domain. Writes to it "immediately" go to main memory
 401          * as far as we know, so there's no chipset flush. It also doesn't
 402          * land in the GPU render cache.
 403          *
 404          * However, we do have to enforce the order so that all writes through
 405          * the GTT land before any writes to the device, such as updates to
 406          * the GATT itself.
 407          *
 408          * We also have to wait a bit for the writes to land from the GTT.
 409          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 410          * timing. This issue has only been observed when switching quickly
 411          * between GTT writes and CPU reads from inside the kernel on recent hw,
 412          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 413          * system agents we cannot reproduce this behaviour, until Cannonlake
 414          * that was!).
 415          */
 416
 417         wmb();
 418
 419         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 420                 return;
 421
 422         intel_gt_chipset_flush(gt);
 423
 424         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 425                 unsigned long flags;
 426
 427                 spin_lock_irqsave(&uncore->lock, flags);
 428                 intel_uncore_posting_read_fw(uncore,
 429                                              RING_HEAD(RENDER_RING_BASE));
 430                 spin_unlock_irqrestore(&uncore->lock, flags);
 431         }
 432 }
 433
 434 void intel_gt_chipset_flush(struct intel_gt *gt)
 435 {
 436         wmb();
 437         if (GRAPHICS_VER(gt->i915) < 6)
 438                 intel_gtt_chipset_flush();
 439 }
 440
 441 void intel_gt_driver_register(struct intel_gt *gt)
 442 {
 443         intel_rps_driver_register(&gt->rps);
 444
 445         intel_gt_debugfs_register(gt);
 446 }
 447
 448 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 449 {
 450         struct drm_i915_private *i915 = gt->i915;
 451         struct drm_i915_gem_object *obj;
 452         struct i915_vma *vma;
 453         int ret;
 454
 455         obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
 456         if (IS_ERR(obj))
 457                 obj = i915_gem_object_create_stolen(i915, size);
 458         if (IS_ERR(obj))
 459                 obj = i915_gem_object_create_internal(i915, size);
 460         if (IS_ERR(obj)) {
 461                 drm_err(&i915->drm, "Failed to allocate scratch page\n");
 462                 return PTR_ERR(obj);
 463         }
 464
 465         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 466         if (IS_ERR(vma)) {
 467                 ret = PTR_ERR(vma);
 468                 goto err_unref;
 469         }
 470
 471         ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
 472         if (ret)
 473                 goto err_unref;
 474
 475         gt->scratch = i915_vma_make_unshrinkable(vma);
 476
 477         return 0;
 478
 479 err_unref:
 480         i915_gem_object_put(obj);
 481         return ret;
 482 }
 483
 484 static void intel_gt_fini_scratch(struct intel_gt *gt)
 485 {
 486         i915_vma_unpin_and_release(&gt->scratch, 0);
 487 }
 488
 489 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 490 {
 491         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 492                 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
 493         else
 494                 return i915_vm_get(&gt->ggtt->vm);
 495 }
 496
 497 static int __engines_record_defaults(struct intel_gt *gt)
 498 {
 499         struct i915_request *requests[I915_NUM_ENGINES] = {};
 500         struct intel_engine_cs *engine;
 501         enum intel_engine_id id;
 502         int err = 0;
 503
 504         /*
 505          * As we reset the gpu during very early sanitisation, the current
 506          * register state on the GPU should reflect its defaults values.
 507          * We load a context onto the hw (with restore-inhibit), then switch
 508          * over to a second context to save that default register state. We
 509          * can then prime every new context with that state so they all start
 510          * from the same default HW values.
 511          */
 512
 513         for_each_engine(engine, gt, id) {
 514                 struct intel_renderstate so;
 515                 struct intel_context *ce;
 516                 struct i915_request *rq;
 517
 518                 /* We must be able to switch to something! */
 519                 GEM_BUG_ON(!engine->kernel_context);
 520
 521                 ce = intel_context_create(engine);
 522                 if (IS_ERR(ce)) {
 523                         err = PTR_ERR(ce);
 524                         goto out;
 525                 }
 526
 527                 err = intel_renderstate_init(&so, ce);
 528                 if (err)
 529                         goto err;
 530
 531                 rq = i915_request_create(ce);
 532                 if (IS_ERR(rq)) {
 533                         err = PTR_ERR(rq);
 534                         goto err_fini;
 535                 }
 536
 537                 err = intel_engine_emit_ctx_wa(rq);
 538                 if (err)
 539                         goto err_rq;
 540
 541                 err = intel_renderstate_emit(&so, rq);
 542                 if (err)
 543                         goto err_rq;
 544
 545 err_rq:
 546                 requests[id] = i915_request_get(rq);
 547                 i915_request_add(rq);
 548 err_fini:
 549                 intel_renderstate_fini(&so, ce);
 550 err:
 551                 if (err) {
 552                         intel_context_put(ce);
 553                         goto out;
 554                 }
 555         }
 556
 557         /* Flush the default context image to memory, and enable powersaving. */
 558         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 559                 err = -EIO;
 560                 goto out;
 561         }
 562
 563         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 564                 struct i915_request *rq;
 565                 struct file *state;
 566
 567                 rq = requests[id];
 568                 if (!rq)
 569                         continue;
 570
 571                 if (rq->fence.error) {
 572                         err = -EIO;
 573                         goto out;
 574                 }
 575
 576                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 577                 if (!rq->context->state)
 578                         continue;
 579
 580                 /* Keep a copy of the state's backing pages; free the obj */
 581                 state = shmem_create_from_object(rq->context->state->obj);
 582                 if (IS_ERR(state)) {
 583                         err = PTR_ERR(state);
 584                         goto out;
 585                 }
 586                 rq->engine->default_state = state;
 587         }
 588
 589 out:
 590         /*
 591          * If we have to abandon now, we expect the engines to be idle
 592          * and ready to be torn-down. The quickest way we can accomplish
 593          * this is by declaring ourselves wedged.
 594          */
 595         if (err)
 596                 intel_gt_set_wedged(gt);
 597
 598         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 599                 struct intel_context *ce;
 600                 struct i915_request *rq;
 601
 602                 rq = requests[id];
 603                 if (!rq)
 604                         continue;
 605
 606                 ce = rq->context;
 607                 i915_request_put(rq);
 608                 intel_context_put(ce);
 609         }
 610         return err;
 611 }
 612
 613 static int __engines_verify_workarounds(struct intel_gt *gt)
 614 {
 615         struct intel_engine_cs *engine;
 616         enum intel_engine_id id;
 617         int err = 0;
 618
 619         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 620                 return 0;
 621
 622         for_each_engine(engine, gt, id) {
 623                 if (intel_engine_verify_workarounds(engine, "load"))
 624                         err = -EIO;
 625         }
 626
 627         /* Flush and restore the kernel context for safety */
 628         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
 629                 err = -EIO;
 630
 631         return err;
 632 }
 633
 634 static void __intel_gt_disable(struct intel_gt *gt)
 635 {
 636         intel_gt_set_wedged_on_fini(gt);
 637
 638         intel_gt_suspend_prepare(gt);
 639         intel_gt_suspend_late(gt);
 640
 641         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 642 }
 643
 644 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
 645 {
 646         long remaining_timeout;
 647
 648         /* If the device is asleep, we have no requests outstanding */
 649         if (!intel_gt_pm_is_awake(gt))
 650                 return 0;
 651
 652         while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
 653                                                            &remaining_timeout)) > 0) {
 654                 cond_resched();
 655                 if (signal_pending(current))
 656                         return -EINTR;
 657         }
 658
 659         return timeout ? timeout : intel_uc_wait_for_idle(&gt->uc,
 660                                                           remaining_timeout);
 661 }
 662
 663 int intel_gt_init(struct intel_gt *gt)
 664 {
 665         int err;
 666
 667         err = i915_inject_probe_error(gt->i915, -ENODEV);
 668         if (err)
 669                 return err;
 670
 671         intel_gt_init_workarounds(gt);
 672
 673         /*
 674          * This is just a security blanket to placate dragons.
 675          * On some systems, we very sporadically observe that the first TLBs
 676          * used by the CS may be stale, despite us poking the TLB reset. If
 677          * we hold the forcewake during initialisation these problems
 678          * just magically go away.
 679          */
 680         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 681
 682         err = intel_gt_init_scratch(gt,
 683                                     GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
 684         if (err)
 685                 goto out_fw;
 686
 687         intel_gt_pm_init(gt);
 688
 689         gt->vm = kernel_vm(gt);
 690         if (!gt->vm) {
 691                 err = -ENOMEM;
 692                 goto err_pm;
 693         }
 694
 695         intel_set_mocs_index(gt);
 696
 697         err = intel_engines_init(gt);
 698         if (err)
 699                 goto err_engines;
 700
 701         err = intel_uc_init(&gt->uc);
 702         if (err)
 703                 goto err_engines;
 704
 705         err = intel_gt_resume(gt);
 706         if (err)
 707                 goto err_uc_init;
 708
 709         err = __engines_record_defaults(gt);
 710         if (err)
 711                 goto err_gt;
 712
 713         err = __engines_verify_workarounds(gt);
 714         if (err)
 715                 goto err_gt;
 716
 717         intel_uc_init_late(&gt->uc);
 718
 719         err = i915_inject_probe_error(gt->i915, -EIO);
 720         if (err)
 721                 goto err_gt;
 722
 723         intel_migrate_init(&gt->migrate, gt);
 724
 725         intel_pxp_init(&gt->pxp);
 726
 727         goto out_fw;
 728 err_gt:
 729         __intel_gt_disable(gt);
 730         intel_uc_fini_hw(&gt->uc);
 731 err_uc_init:
 732         intel_uc_fini(&gt->uc);
 733 err_engines:
 734         intel_engines_release(gt);
 735         i915_vm_put(fetch_and_zero(&gt->vm));
 736 err_pm:
 737         intel_gt_pm_fini(gt);
 738         intel_gt_fini_scratch(gt);
 739 out_fw:
 740         if (err)
 741                 intel_gt_set_wedged_on_init(gt);
 742         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 743         return err;
 744 }
 745
 746 void intel_gt_driver_remove(struct intel_gt *gt)
 747 {
 748         __intel_gt_disable(gt);
 749
 750         intel_migrate_fini(&gt->migrate);
 751         intel_uc_driver_remove(&gt->uc);
 752
 753         intel_engines_release(gt);
 754
 755         intel_gt_flush_buffer_pool(gt);
 756 }
 757
 758 void intel_gt_driver_unregister(struct intel_gt *gt)
 759 {
 760         intel_wakeref_t wakeref;
 761
 762         intel_rps_driver_unregister(&gt->rps);
 763
 764         intel_pxp_fini(&gt->pxp);
 765
 766         /*
 767          * Upon unregistering the device to prevent any new users, cancel
 768          * all in-flight requests so that we can quickly unbind the active
 769          * resources.
 770          */
 771         intel_gt_set_wedged_on_fini(gt);
 772
 773         /* Scrub all HW state upon release */
 774         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 775                 __intel_gt_reset(gt, ALL_ENGINES);
 776 }
 777
 778 void intel_gt_driver_release(struct intel_gt *gt)
 779 {
 780         struct i915_address_space *vm;
 781
 782         vm = fetch_and_zero(&gt->vm);
 783         if (vm) /* FIXME being called twice on error paths :( */
 784                 i915_vm_put(vm);
 785
 786         intel_wa_list_free(&gt->wa_list);
 787         intel_gt_pm_fini(gt);
 788         intel_gt_fini_scratch(gt);
 789         intel_gt_fini_buffer_pool(gt);
 790 }
 791
 792 void intel_gt_driver_late_release(struct intel_gt *gt)
 793 {
 794         /* We need to wait for inflight RCU frees to release their grip */
 795         rcu_barrier();
 796
 797         intel_uc_driver_late_release(&gt->uc);
 798         intel_gt_fini_requests(gt);
 799         intel_gt_fini_reset(gt);
 800         intel_gt_fini_timelines(gt);
 801         intel_engines_free(gt);
 802 }
 803
 804 /**
 805  * intel_gt_reg_needs_read_steering - determine whether a register read
 806  *     requires explicit steering
 807  * @gt: GT structure
 808  * @reg: the register to check steering requirements for
 809  * @type: type of multicast steering to check
 810  *
 811  * Determines whether @reg needs explicit steering of a specific type for
 812  * reads.
 813  *
 814  * Returns false if @reg does not belong to a register range of the given
 815  * steering type, or if the default (subslice-based) steering IDs are suitable
 816  * for @type steering too.
 817  */
 818 static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
 819                                              i915_reg_t reg,
 820                                              enum intel_steering_type type)
 821 {
 822         const u32 offset = i915_mmio_reg_offset(reg);
 823         const struct intel_mmio_range *entry;
 824
 825         if (likely(!intel_gt_needs_read_steering(gt, type)))
 826                 return false;
 827
 828         for (entry = gt->steering_table[type]; entry->end; entry++) {
 829                 if (offset >= entry->start && offset <= entry->end)
 830                         return true;
 831         }
 832
 833         return false;
 834 }
 835
 836 /**
 837  * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering
 838  * @gt: GT structure
 839  * @type: multicast register type
 840  * @sliceid: Slice ID returned
 841  * @subsliceid: Subslice ID returned
 842  *
 843  * Determines sliceid and subsliceid values that will steer reads
 844  * of a specific multicast register class to a valid value.
 845  */
 846 static void intel_gt_get_valid_steering(struct intel_gt *gt,
 847                                         enum intel_steering_type type,
 848                                         u8 *sliceid, u8 *subsliceid)
 849 {
 850         switch (type) {
 851         case L3BANK:
 852                 GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
 853
 854                 *sliceid = 0;           /* unused */
 855                 *subsliceid = __ffs(gt->info.l3bank_mask);
 856                 break;
 857         case MSLICE:
 858                 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
 859
 860                 *sliceid = __ffs(gt->info.mslice_mask);
 861                 *subsliceid = 0;        /* unused */
 862                 break;
 863         case LNCF:
 864                 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
 865
 866                 /*
 867                  * An LNCF is always present if its mslice is present, so we
 868                  * can safely just steer to LNCF 0 in all cases.
 869                  */
 870                 *sliceid = __ffs(gt->info.mslice_mask) << 1;
 871                 *subsliceid = 0;        /* unused */
 872                 break;
 873         default:
 874                 MISSING_CASE(type);
 875                 *sliceid = 0;
 876                 *subsliceid = 0;
 877         }
 878 }
 879
 880 /**
 881  * intel_gt_read_register_fw - reads a GT register with support for multicast
 882  * @gt: GT structure
 883  * @reg: register to read
 884  *
 885  * This function will read a GT register.  If the register is a multicast
 886  * register, the read will be steered to a valid instance (i.e., one that
 887  * isn't fused off or powered down by power gating).
 888  *
 889  * Returns the value from a valid instance of @reg.
 890  */
 891 u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
 892 {
 893         int type;
 894         u8 sliceid, subsliceid;
 895
 896         for (type = 0; type < NUM_STEERING_TYPES; type++) {
 897                 if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
 898                         intel_gt_get_valid_steering(gt, type, &sliceid,
 899                                                     &subsliceid);
 900                         return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
 901                                                                       reg,
 902                                                                       sliceid,
 903                                                                       subsliceid);
 904                 }
 905         }
 906
 907         return intel_uncore_read_fw(gt->uncore, reg);
 908 }
 909
 910 void intel_gt_info_print(const struct intel_gt_info *info,
 911                          struct drm_printer *p)
 912 {
 913         drm_printf(p, "available engines: %x\n", info->engine_mask);
 914
 915         intel_sseu_dump(&info->sseu, p);
 916 }
 917
 918 struct reg_and_bit {
 919         i915_reg_t reg;
 920         u32 bit;
 921 };
 922
 923 static struct reg_and_bit
 924 get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
 925                 const i915_reg_t *regs, const unsigned int num)
 926 {
 927         const unsigned int class = engine->class;
 928         struct reg_and_bit rb = { };
 929
 930         if (drm_WARN_ON_ONCE(&engine->i915->drm,
 931                              class >= num || !regs[class].reg))
 932                 return rb;
 933
 934         rb.reg = regs[class];
 935         if (gen8 && class == VIDEO_DECODE_CLASS)
 936                 rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */
 937         else
 938                 rb.bit = engine->instance;
 939
 940         rb.bit = BIT(rb.bit);
 941
 942         return rb;
 943 }
 944
 945 void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 946 {
 947         static const i915_reg_t gen8_regs[] = {
 948                 [RENDER_CLASS]                  = GEN8_RTCR,
 949                 [VIDEO_DECODE_CLASS]            = GEN8_M1TCR, /* , GEN8_M2TCR */
 950                 [VIDEO_ENHANCEMENT_CLASS]       = GEN8_VTCR,
 951                 [COPY_ENGINE_CLASS]             = GEN8_BTCR,
 952         };
 953         static const i915_reg_t gen12_regs[] = {
 954                 [RENDER_CLASS]                  = GEN12_GFX_TLB_INV_CR,
 955                 [VIDEO_DECODE_CLASS]            = GEN12_VD_TLB_INV_CR,
 956                 [VIDEO_ENHANCEMENT_CLASS]       = GEN12_VE_TLB_INV_CR,
 957                 [COPY_ENGINE_CLASS]             = GEN12_BLT_TLB_INV_CR,
 958         };
 959         struct drm_i915_private *i915 = gt->i915;
 960         struct intel_uncore *uncore = gt->uncore;
 961         struct intel_engine_cs *engine;
 962         enum intel_engine_id id;
 963         const i915_reg_t *regs;
 964         unsigned int num = 0;
 965
 966         if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
 967                 return;
 968
 969         if (GRAPHICS_VER(i915) == 12) {
 970                 regs = gen12_regs;
 971                 num = ARRAY_SIZE(gen12_regs);
 972         } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
 973                 regs = gen8_regs;
 974                 num = ARRAY_SIZE(gen8_regs);
 975         } else if (GRAPHICS_VER(i915) < 8) {
 976                 return;
 977         }
 978
 979         if (drm_WARN_ONCE(&i915->drm, !num,
 980                           "Platform does not implement TLB invalidation!"))
 981                 return;
 982
 983         GEM_TRACE("\n");
 984
 985         assert_rpm_wakelock_held(&i915->runtime_pm);
 986
 987         mutex_lock(&gt->tlb_invalidate_lock);
 988         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 989
 990         for_each_engine(engine, gt, id) {
 991                 /*
 992                  * HW architecture suggest typical invalidation time at 40us,
 993                  * with pessimistic cases up to 100us and a recommendation to
 994                  * cap at 1ms. We go a bit higher just in case.
 995                  */
 996                 const unsigned int timeout_us = 100;
 997                 const unsigned int timeout_ms = 4;
 998                 struct reg_and_bit rb;
 999
1000                 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
1001                 if (!i915_mmio_reg_offset(rb.reg))
1002                         continue;
1003
1004                 intel_uncore_write_fw(uncore, rb.reg, rb.bit);
1005                 if (__intel_wait_for_register_fw(uncore,
1006                                                  rb.reg, rb.bit, 0,
1007                                                  timeout_us, timeout_ms,
1008                                                  NULL))
1009                         drm_err_ratelimited(&gt->i915->drm,
1010                                             "%s TLB invalidation did not complete in %ums!\n",
1011                                             engine->name, timeout_ms);
1012         }
1013
1014         /*
1015          * Use delayed put since a) we mostly expect a flurry of TLB
1016          * invalidations so it is good to avoid paying the forcewake cost and
1017          * b) it works around a bug in Icelake which cannot cope with too rapid
1018          * transitions.
1019          */
1020         intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
1021         mutex_unlock(&gt->tlb_invalidate_lock);
1022 }