1 // SPDX-License-Identifier: MIT
3 * Copyright © 2019 Intel Corporation
6 #include <drm/intel-gtt.h>
8 #include "intel_gt_debugfs.h"
10 #include "gem/i915_gem_lmem.h"
12 #include "intel_context.h"
14 #include "intel_gt_buffer_pool.h"
15 #include "intel_gt_clock_utils.h"
16 #include "intel_gt_pm.h"
17 #include "intel_gt_requests.h"
18 #include "intel_migrate.h"
19 #include "intel_mocs.h"
21 #include "intel_rc6.h"
22 #include "intel_renderstate.h"
23 #include "intel_rps.h"
24 #include "intel_uncore.h"
25 #include "shmem_utils.h"
26 #include "pxp/intel_pxp.h"
28 void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
30 spin_lock_init(>->irq_lock);
32 mutex_init(>->tlb_invalidate_lock);
34 INIT_LIST_HEAD(>->closed_vma);
35 spin_lock_init(>->closed_lock);
37 init_llist_head(>->watchdog.list);
38 INIT_WORK(>->watchdog.work, intel_gt_watchdog_work);
40 intel_gt_init_buffer_pool(gt);
41 intel_gt_init_reset(gt);
42 intel_gt_init_requests(gt);
43 intel_gt_init_timelines(gt);
44 intel_gt_pm_init_early(gt);
46 intel_uc_init_early(>->uc);
47 intel_rps_init_early(>->rps);
50 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
53 gt->uncore = &i915->uncore;
56 int intel_gt_probe_lmem(struct intel_gt *gt)
58 struct drm_i915_private *i915 = gt->i915;
59 struct intel_memory_region *mem;
63 mem = intel_gt_setup_lmem(gt);
64 if (mem == ERR_PTR(-ENODEV))
65 mem = intel_gt_setup_fake_lmem(gt);
72 "Failed to setup region(%d) type=%d\n",
73 err, INTEL_MEMORY_LOCAL);
77 id = INTEL_REGION_LMEM;
81 intel_memory_region_set_name(mem, "local%u", mem->instance);
83 GEM_BUG_ON(!HAS_REGION(i915, id));
84 GEM_BUG_ON(i915->mm.regions[id]);
85 i915->mm.regions[id] = mem;
90 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
95 static const struct intel_mmio_range icl_l3bank_steering_table[] = {
96 { 0x00B100, 0x00B3FF },
100 static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
101 { 0x004000, 0x004AFF },
102 { 0x00C800, 0x00CFFF },
103 { 0x00DD00, 0x00DDFF },
104 { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
108 static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
109 { 0x00B000, 0x00B0FF },
110 { 0x00D800, 0x00D8FF },
114 static const struct intel_mmio_range dg2_lncf_steering_table[] = {
115 { 0x00B000, 0x00B0FF },
116 { 0x00D880, 0x00D8FF },
120 static u16 slicemask(struct intel_gt *gt, int count)
122 u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
124 return intel_slicemask_from_dssmask(dss_mask, count);
127 int intel_gt_init_mmio(struct intel_gt *gt)
129 struct drm_i915_private *i915 = gt->i915;
131 intel_gt_init_clock_frequency(gt);
133 intel_uc_init_mmio(>->uc);
134 intel_sseu_info_init(gt);
137 * An mslice is unavailable only if both the meml3 for the slice is
138 * disabled *and* all of the DSS in the slice (quadrant) are disabled.
140 if (HAS_MSLICES(i915))
141 gt->info.mslice_mask =
142 slicemask(gt, GEN_DSS_PER_MSLICE) |
143 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
144 GEN12_MEML3_EN_MASK);
147 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
148 gt->steering_table[LNCF] = dg2_lncf_steering_table;
149 } else if (IS_XEHPSDV(i915)) {
150 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
151 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
152 } else if (GRAPHICS_VER(i915) >= 11 &&
153 GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
154 gt->steering_table[L3BANK] = icl_l3bank_steering_table;
155 gt->info.l3bank_mask =
156 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
158 } else if (HAS_MSLICES(i915)) {
159 MISSING_CASE(INTEL_INFO(i915)->platform);
162 return intel_engines_init_mmio(gt);
165 static void init_unused_ring(struct intel_gt *gt, u32 base)
167 struct intel_uncore *uncore = gt->uncore;
169 intel_uncore_write(uncore, RING_CTL(base), 0);
170 intel_uncore_write(uncore, RING_HEAD(base), 0);
171 intel_uncore_write(uncore, RING_TAIL(base), 0);
172 intel_uncore_write(uncore, RING_START(base), 0);
175 static void init_unused_rings(struct intel_gt *gt)
177 struct drm_i915_private *i915 = gt->i915;
180 init_unused_ring(gt, PRB1_BASE);
181 init_unused_ring(gt, SRB0_BASE);
182 init_unused_ring(gt, SRB1_BASE);
183 init_unused_ring(gt, SRB2_BASE);
184 init_unused_ring(gt, SRB3_BASE);
185 } else if (GRAPHICS_VER(i915) == 2) {
186 init_unused_ring(gt, SRB0_BASE);
187 init_unused_ring(gt, SRB1_BASE);
188 } else if (GRAPHICS_VER(i915) == 3) {
189 init_unused_ring(gt, PRB1_BASE);
190 init_unused_ring(gt, PRB2_BASE);
194 int intel_gt_init_hw(struct intel_gt *gt)
196 struct drm_i915_private *i915 = gt->i915;
197 struct intel_uncore *uncore = gt->uncore;
200 gt->last_init_time = ktime_get();
202 /* Double layer security blanket, see i915_gem_init() */
203 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
205 if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
206 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
208 if (IS_HASWELL(i915))
209 intel_uncore_write(uncore,
210 MI_PREDICATE_RESULT_2,
212 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
214 /* Apply the GT workarounds... */
215 intel_gt_apply_workarounds(gt);
216 /* ...and determine whether they are sticking. */
217 intel_gt_verify_workarounds(gt, "init");
219 intel_gt_init_swizzling(gt);
222 * At least 830 can leave some of the unused rings
223 * "active" (ie. head != tail) after resume which
224 * will prevent c3 entry. Makes sure all unused rings
227 init_unused_rings(gt);
229 ret = i915_ppgtt_init_hw(gt);
231 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
235 /* We can't enable contexts until all firmware is loaded */
236 ret = intel_uc_init_hw(>->uc);
238 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
245 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
249 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
251 intel_uncore_rmw(uncore, reg, 0, set);
254 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
256 intel_uncore_rmw(uncore, reg, clr, 0);
259 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
261 intel_uncore_rmw(uncore, reg, 0, 0);
264 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
266 GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
267 GEN6_RING_FAULT_REG_POSTING_READ(engine);
271 intel_gt_clear_error_registers(struct intel_gt *gt,
272 intel_engine_mask_t engine_mask)
274 struct drm_i915_private *i915 = gt->i915;
275 struct intel_uncore *uncore = gt->uncore;
278 if (GRAPHICS_VER(i915) != 2)
279 clear_register(uncore, PGTBL_ER);
281 if (GRAPHICS_VER(i915) < 4)
282 clear_register(uncore, IPEIR(RENDER_RING_BASE));
284 clear_register(uncore, IPEIR_I965);
286 clear_register(uncore, EIR);
287 eir = intel_uncore_read(uncore, EIR);
290 * some errors might have become stuck,
293 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
294 rmw_set(uncore, EMR, eir);
295 intel_uncore_write(uncore, GEN2_IIR,
296 I915_MASTER_ERROR_INTERRUPT);
299 if (GRAPHICS_VER(i915) >= 12) {
300 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
301 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
302 } else if (GRAPHICS_VER(i915) >= 8) {
303 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
304 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
305 } else if (GRAPHICS_VER(i915) >= 6) {
306 struct intel_engine_cs *engine;
307 enum intel_engine_id id;
309 for_each_engine_masked(engine, gt, engine_mask, id)
310 gen6_clear_engine_error_register(engine);
314 static void gen6_check_faults(struct intel_gt *gt)
316 struct intel_engine_cs *engine;
317 enum intel_engine_id id;
320 for_each_engine(engine, gt, id) {
321 fault = GEN6_RING_FAULT_REG_READ(engine);
322 if (fault & RING_FAULT_VALID) {
323 drm_dbg(&engine->i915->drm, "Unexpected fault\n"
325 "\tAddress space: %s\n"
329 fault & RING_FAULT_GTTSEL_MASK ?
331 RING_FAULT_SRCID(fault),
332 RING_FAULT_FAULT_TYPE(fault));
337 static void gen8_check_faults(struct intel_gt *gt)
339 struct intel_uncore *uncore = gt->uncore;
340 i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
343 if (GRAPHICS_VER(gt->i915) >= 12) {
344 fault_reg = GEN12_RING_FAULT_REG;
345 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
346 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
348 fault_reg = GEN8_RING_FAULT_REG;
349 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
350 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
353 fault = intel_uncore_read(uncore, fault_reg);
354 if (fault & RING_FAULT_VALID) {
355 u32 fault_data0, fault_data1;
358 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
359 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
361 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
362 ((u64)fault_data0 << 12);
364 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
365 "\tAddr: 0x%08x_%08x\n"
366 "\tAddress space: %s\n"
370 upper_32_bits(fault_addr), lower_32_bits(fault_addr),
371 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
372 GEN8_RING_FAULT_ENGINE_ID(fault),
373 RING_FAULT_SRCID(fault),
374 RING_FAULT_FAULT_TYPE(fault));
378 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
380 struct drm_i915_private *i915 = gt->i915;
382 /* From GEN8 onwards we only have one 'All Engine Fault Register' */
383 if (GRAPHICS_VER(i915) >= 8)
384 gen8_check_faults(gt);
385 else if (GRAPHICS_VER(i915) >= 6)
386 gen6_check_faults(gt);
390 intel_gt_clear_error_registers(gt, ALL_ENGINES);
393 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
395 struct intel_uncore *uncore = gt->uncore;
396 intel_wakeref_t wakeref;
399 * No actual flushing is required for the GTT write domain for reads
400 * from the GTT domain. Writes to it "immediately" go to main memory
401 * as far as we know, so there's no chipset flush. It also doesn't
402 * land in the GPU render cache.
404 * However, we do have to enforce the order so that all writes through
405 * the GTT land before any writes to the device, such as updates to
408 * We also have to wait a bit for the writes to land from the GTT.
409 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
410 * timing. This issue has only been observed when switching quickly
411 * between GTT writes and CPU reads from inside the kernel on recent hw,
412 * and it appears to only affect discrete GTT blocks (i.e. on LLC
413 * system agents we cannot reproduce this behaviour, until Cannonlake
419 if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
422 intel_gt_chipset_flush(gt);
424 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
427 spin_lock_irqsave(&uncore->lock, flags);
428 intel_uncore_posting_read_fw(uncore,
429 RING_HEAD(RENDER_RING_BASE));
430 spin_unlock_irqrestore(&uncore->lock, flags);
434 void intel_gt_chipset_flush(struct intel_gt *gt)
437 if (GRAPHICS_VER(gt->i915) < 6)
438 intel_gtt_chipset_flush();
441 void intel_gt_driver_register(struct intel_gt *gt)
443 intel_rps_driver_register(>->rps);
445 intel_gt_debugfs_register(gt);
448 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
450 struct drm_i915_private *i915 = gt->i915;
451 struct drm_i915_gem_object *obj;
452 struct i915_vma *vma;
455 obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
457 obj = i915_gem_object_create_stolen(i915, size);
459 obj = i915_gem_object_create_internal(i915, size);
461 drm_err(&i915->drm, "Failed to allocate scratch page\n");
465 vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
471 ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
475 gt->scratch = i915_vma_make_unshrinkable(vma);
480 i915_gem_object_put(obj);
484 static void intel_gt_fini_scratch(struct intel_gt *gt)
486 i915_vma_unpin_and_release(>->scratch, 0);
489 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
491 if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
492 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
494 return i915_vm_get(>->ggtt->vm);
497 static int __engines_record_defaults(struct intel_gt *gt)
499 struct i915_request *requests[I915_NUM_ENGINES] = {};
500 struct intel_engine_cs *engine;
501 enum intel_engine_id id;
505 * As we reset the gpu during very early sanitisation, the current
506 * register state on the GPU should reflect its defaults values.
507 * We load a context onto the hw (with restore-inhibit), then switch
508 * over to a second context to save that default register state. We
509 * can then prime every new context with that state so they all start
510 * from the same default HW values.
513 for_each_engine(engine, gt, id) {
514 struct intel_renderstate so;
515 struct intel_context *ce;
516 struct i915_request *rq;
518 /* We must be able to switch to something! */
519 GEM_BUG_ON(!engine->kernel_context);
521 ce = intel_context_create(engine);
527 err = intel_renderstate_init(&so, ce);
531 rq = i915_request_create(ce);
537 err = intel_engine_emit_ctx_wa(rq);
541 err = intel_renderstate_emit(&so, rq);
546 requests[id] = i915_request_get(rq);
547 i915_request_add(rq);
549 intel_renderstate_fini(&so, ce);
552 intel_context_put(ce);
557 /* Flush the default context image to memory, and enable powersaving. */
558 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
563 for (id = 0; id < ARRAY_SIZE(requests); id++) {
564 struct i915_request *rq;
571 if (rq->fence.error) {
576 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
577 if (!rq->context->state)
580 /* Keep a copy of the state's backing pages; free the obj */
581 state = shmem_create_from_object(rq->context->state->obj);
583 err = PTR_ERR(state);
586 rq->engine->default_state = state;
591 * If we have to abandon now, we expect the engines to be idle
592 * and ready to be torn-down. The quickest way we can accomplish
593 * this is by declaring ourselves wedged.
596 intel_gt_set_wedged(gt);
598 for (id = 0; id < ARRAY_SIZE(requests); id++) {
599 struct intel_context *ce;
600 struct i915_request *rq;
607 i915_request_put(rq);
608 intel_context_put(ce);
613 static int __engines_verify_workarounds(struct intel_gt *gt)
615 struct intel_engine_cs *engine;
616 enum intel_engine_id id;
619 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
622 for_each_engine(engine, gt, id) {
623 if (intel_engine_verify_workarounds(engine, "load"))
627 /* Flush and restore the kernel context for safety */
628 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
634 static void __intel_gt_disable(struct intel_gt *gt)
636 intel_gt_set_wedged_on_fini(gt);
638 intel_gt_suspend_prepare(gt);
639 intel_gt_suspend_late(gt);
641 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
644 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
646 long remaining_timeout;
648 /* If the device is asleep, we have no requests outstanding */
649 if (!intel_gt_pm_is_awake(gt))
652 while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
653 &remaining_timeout)) > 0) {
655 if (signal_pending(current))
659 return timeout ? timeout : intel_uc_wait_for_idle(>->uc,
663 int intel_gt_init(struct intel_gt *gt)
667 err = i915_inject_probe_error(gt->i915, -ENODEV);
671 intel_gt_init_workarounds(gt);
674 * This is just a security blanket to placate dragons.
675 * On some systems, we very sporadically observe that the first TLBs
676 * used by the CS may be stale, despite us poking the TLB reset. If
677 * we hold the forcewake during initialisation these problems
678 * just magically go away.
680 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
682 err = intel_gt_init_scratch(gt,
683 GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
687 intel_gt_pm_init(gt);
689 gt->vm = kernel_vm(gt);
695 intel_set_mocs_index(gt);
697 err = intel_engines_init(gt);
701 err = intel_uc_init(>->uc);
705 err = intel_gt_resume(gt);
709 err = __engines_record_defaults(gt);
713 err = __engines_verify_workarounds(gt);
717 intel_uc_init_late(>->uc);
719 err = i915_inject_probe_error(gt->i915, -EIO);
723 intel_migrate_init(>->migrate, gt);
725 intel_pxp_init(>->pxp);
729 __intel_gt_disable(gt);
730 intel_uc_fini_hw(>->uc);
732 intel_uc_fini(>->uc);
734 intel_engines_release(gt);
735 i915_vm_put(fetch_and_zero(>->vm));
737 intel_gt_pm_fini(gt);
738 intel_gt_fini_scratch(gt);
741 intel_gt_set_wedged_on_init(gt);
742 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
746 void intel_gt_driver_remove(struct intel_gt *gt)
748 __intel_gt_disable(gt);
750 intel_migrate_fini(>->migrate);
751 intel_uc_driver_remove(>->uc);
753 intel_engines_release(gt);
755 intel_gt_flush_buffer_pool(gt);
758 void intel_gt_driver_unregister(struct intel_gt *gt)
760 intel_wakeref_t wakeref;
762 intel_rps_driver_unregister(>->rps);
764 intel_pxp_fini(>->pxp);
767 * Upon unregistering the device to prevent any new users, cancel
768 * all in-flight requests so that we can quickly unbind the active
771 intel_gt_set_wedged_on_fini(gt);
773 /* Scrub all HW state upon release */
774 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
775 __intel_gt_reset(gt, ALL_ENGINES);
778 void intel_gt_driver_release(struct intel_gt *gt)
780 struct i915_address_space *vm;
782 vm = fetch_and_zero(>->vm);
783 if (vm) /* FIXME being called twice on error paths :( */
786 intel_wa_list_free(>->wa_list);
787 intel_gt_pm_fini(gt);
788 intel_gt_fini_scratch(gt);
789 intel_gt_fini_buffer_pool(gt);
792 void intel_gt_driver_late_release(struct intel_gt *gt)
794 /* We need to wait for inflight RCU frees to release their grip */
797 intel_uc_driver_late_release(>->uc);
798 intel_gt_fini_requests(gt);
799 intel_gt_fini_reset(gt);
800 intel_gt_fini_timelines(gt);
801 intel_engines_free(gt);
805 * intel_gt_reg_needs_read_steering - determine whether a register read
806 * requires explicit steering
808 * @reg: the register to check steering requirements for
809 * @type: type of multicast steering to check
811 * Determines whether @reg needs explicit steering of a specific type for
814 * Returns false if @reg does not belong to a register range of the given
815 * steering type, or if the default (subslice-based) steering IDs are suitable
816 * for @type steering too.
818 static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
820 enum intel_steering_type type)
822 const u32 offset = i915_mmio_reg_offset(reg);
823 const struct intel_mmio_range *entry;
825 if (likely(!intel_gt_needs_read_steering(gt, type)))
828 for (entry = gt->steering_table[type]; entry->end; entry++) {
829 if (offset >= entry->start && offset <= entry->end)
837 * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering
839 * @type: multicast register type
840 * @sliceid: Slice ID returned
841 * @subsliceid: Subslice ID returned
843 * Determines sliceid and subsliceid values that will steer reads
844 * of a specific multicast register class to a valid value.
846 static void intel_gt_get_valid_steering(struct intel_gt *gt,
847 enum intel_steering_type type,
848 u8 *sliceid, u8 *subsliceid)
852 GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
854 *sliceid = 0; /* unused */
855 *subsliceid = __ffs(gt->info.l3bank_mask);
858 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
860 *sliceid = __ffs(gt->info.mslice_mask);
861 *subsliceid = 0; /* unused */
864 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
867 * An LNCF is always present if its mslice is present, so we
868 * can safely just steer to LNCF 0 in all cases.
870 *sliceid = __ffs(gt->info.mslice_mask) << 1;
871 *subsliceid = 0; /* unused */
881 * intel_gt_read_register_fw - reads a GT register with support for multicast
883 * @reg: register to read
885 * This function will read a GT register. If the register is a multicast
886 * register, the read will be steered to a valid instance (i.e., one that
887 * isn't fused off or powered down by power gating).
889 * Returns the value from a valid instance of @reg.
891 u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
894 u8 sliceid, subsliceid;
896 for (type = 0; type < NUM_STEERING_TYPES; type++) {
897 if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
898 intel_gt_get_valid_steering(gt, type, &sliceid,
900 return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
907 return intel_uncore_read_fw(gt->uncore, reg);
910 void intel_gt_info_print(const struct intel_gt_info *info,
911 struct drm_printer *p)
913 drm_printf(p, "available engines: %x\n", info->engine_mask);
915 intel_sseu_dump(&info->sseu, p);
923 static struct reg_and_bit
924 get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
925 const i915_reg_t *regs, const unsigned int num)
927 const unsigned int class = engine->class;
928 struct reg_and_bit rb = { };
930 if (drm_WARN_ON_ONCE(&engine->i915->drm,
931 class >= num || !regs[class].reg))
934 rb.reg = regs[class];
935 if (gen8 && class == VIDEO_DECODE_CLASS)
936 rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */
938 rb.bit = engine->instance;
940 rb.bit = BIT(rb.bit);
945 void intel_gt_invalidate_tlbs(struct intel_gt *gt)
947 static const i915_reg_t gen8_regs[] = {
948 [RENDER_CLASS] = GEN8_RTCR,
949 [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */
950 [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR,
951 [COPY_ENGINE_CLASS] = GEN8_BTCR,
953 static const i915_reg_t gen12_regs[] = {
954 [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR,
955 [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
956 [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
957 [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
959 struct drm_i915_private *i915 = gt->i915;
960 struct intel_uncore *uncore = gt->uncore;
961 struct intel_engine_cs *engine;
962 enum intel_engine_id id;
963 const i915_reg_t *regs;
964 unsigned int num = 0;
966 if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
969 if (GRAPHICS_VER(i915) == 12) {
971 num = ARRAY_SIZE(gen12_regs);
972 } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
974 num = ARRAY_SIZE(gen8_regs);
975 } else if (GRAPHICS_VER(i915) < 8) {
979 if (drm_WARN_ONCE(&i915->drm, !num,
980 "Platform does not implement TLB invalidation!"))
985 assert_rpm_wakelock_held(&i915->runtime_pm);
987 mutex_lock(>->tlb_invalidate_lock);
988 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
990 for_each_engine(engine, gt, id) {
992 * HW architecture suggest typical invalidation time at 40us,
993 * with pessimistic cases up to 100us and a recommendation to
994 * cap at 1ms. We go a bit higher just in case.
996 const unsigned int timeout_us = 100;
997 const unsigned int timeout_ms = 4;
998 struct reg_and_bit rb;
1000 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
1001 if (!i915_mmio_reg_offset(rb.reg))
1004 intel_uncore_write_fw(uncore, rb.reg, rb.bit);
1005 if (__intel_wait_for_register_fw(uncore,
1007 timeout_us, timeout_ms,
1009 drm_err_ratelimited(>->i915->drm,
1010 "%s TLB invalidation did not complete in %ums!\n",
1011 engine->name, timeout_ms);
1015 * Use delayed put since a) we mostly expect a flurry of TLB
1016 * invalidations so it is good to avoid paying the forcewake cost and
1017 * b) it works around a bug in Icelake which cannot cope with too rapid
1020 intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
1021 mutex_unlock(>->tlb_invalidate_lock);