drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include <drm/intel-gtt.h>
   7
   8 #include "intel_gt_debugfs.h"
   9
  10 #include "gem/i915_gem_lmem.h"
  11 #include "i915_drv.h"
  12 #include "intel_context.h"
  13 #include "intel_gt.h"
  14 #include "intel_gt_buffer_pool.h"
  15 #include "intel_gt_clock_utils.h"
  16 #include "intel_gt_pm.h"
  17 #include "intel_gt_requests.h"
  18 #include "intel_migrate.h"
  19 #include "intel_mocs.h"
  20 #include "intel_pm.h"
  21 #include "intel_rc6.h"
  22 #include "intel_renderstate.h"
  23 #include "intel_rps.h"
  24 #include "intel_uncore.h"
  25 #include "shmem_utils.h"
  26 #include "pxp/intel_pxp.h"
  27
  28 void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  29 {
  30         spin_lock_init(&gt->irq_lock);
  31
  32         INIT_LIST_HEAD(&gt->closed_vma);
  33         spin_lock_init(&gt->closed_lock);
  34
  35         init_llist_head(&gt->watchdog.list);
  36         INIT_WORK(&gt->watchdog.work, intel_gt_watchdog_work);
  37
  38         intel_gt_init_buffer_pool(gt);
  39         intel_gt_init_reset(gt);
  40         intel_gt_init_requests(gt);
  41         intel_gt_init_timelines(gt);
  42         intel_gt_pm_init_early(gt);
  43
  44         intel_uc_init_early(&gt->uc);
  45         intel_rps_init_early(&gt->rps);
  46 }
  47
  48 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  49 {
  50         gt->i915 = i915;
  51         gt->uncore = &i915->uncore;
  52 }
  53
  54 int intel_gt_probe_lmem(struct intel_gt *gt)
  55 {
  56         struct drm_i915_private *i915 = gt->i915;
  57         struct intel_memory_region *mem;
  58         int id;
  59         int err;
  60
  61         mem = intel_gt_setup_lmem(gt);
  62         if (mem == ERR_PTR(-ENODEV))
  63                 mem = intel_gt_setup_fake_lmem(gt);
  64         if (IS_ERR(mem)) {
  65                 err = PTR_ERR(mem);
  66                 if (err == -ENODEV)
  67                         return 0;
  68
  69                 drm_err(&i915->drm,
  70                         "Failed to setup region(%d) type=%d\n",
  71                         err, INTEL_MEMORY_LOCAL);
  72                 return err;
  73         }
  74
  75         id = INTEL_REGION_LMEM;
  76
  77         mem->id = id;
  78
  79         intel_memory_region_set_name(mem, "local%u", mem->instance);
  80
  81         GEM_BUG_ON(!HAS_REGION(i915, id));
  82         GEM_BUG_ON(i915->mm.regions[id]);
  83         i915->mm.regions[id] = mem;
  84
  85         return 0;
  86 }
  87
  88 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
  89 {
  90         gt->ggtt = ggtt;
  91 }
  92
  93 static const struct intel_mmio_range icl_l3bank_steering_table[] = {
  94         { 0x00B100, 0x00B3FF },
  95         {},
  96 };
  97
  98 static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
  99         { 0x004000, 0x004AFF },
 100         { 0x00C800, 0x00CFFF },
 101         { 0x00DD00, 0x00DDFF },
 102         { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
 103         {},
 104 };
 105
 106 static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
 107         { 0x00B000, 0x00B0FF },
 108         { 0x00D800, 0x00D8FF },
 109         {},
 110 };
 111
 112 static const struct intel_mmio_range dg2_lncf_steering_table[] = {
 113         { 0x00B000, 0x00B0FF },
 114         { 0x00D880, 0x00D8FF },
 115         {},
 116 };
 117
 118 static u16 slicemask(struct intel_gt *gt, int count)
 119 {
 120         u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
 121
 122         return intel_slicemask_from_dssmask(dss_mask, count);
 123 }
 124
 125 int intel_gt_init_mmio(struct intel_gt *gt)
 126 {
 127         struct drm_i915_private *i915 = gt->i915;
 128
 129         intel_gt_init_clock_frequency(gt);
 130
 131         intel_uc_init_mmio(&gt->uc);
 132         intel_sseu_info_init(gt);
 133
 134         /*
 135          * An mslice is unavailable only if both the meml3 for the slice is
 136          * disabled *and* all of the DSS in the slice (quadrant) are disabled.
 137          */
 138         if (HAS_MSLICES(i915))
 139                 gt->info.mslice_mask =
 140                         slicemask(gt, GEN_DSS_PER_MSLICE) |
 141                         (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 142                          GEN12_MEML3_EN_MASK);
 143
 144         if (IS_DG2(i915)) {
 145                 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 146                 gt->steering_table[LNCF] = dg2_lncf_steering_table;
 147         } else if (IS_XEHPSDV(i915)) {
 148                 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 149                 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
 150         } else if (GRAPHICS_VER(i915) >= 11 &&
 151                    GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
 152                 gt->steering_table[L3BANK] = icl_l3bank_steering_table;
 153                 gt->info.l3bank_mask =
 154                         ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 155                         GEN10_L3BANK_MASK;
 156         } else if (HAS_MSLICES(i915)) {
 157                 MISSING_CASE(INTEL_INFO(i915)->platform);
 158         }
 159
 160         return intel_engines_init_mmio(gt);
 161 }
 162
 163 static void init_unused_ring(struct intel_gt *gt, u32 base)
 164 {
 165         struct intel_uncore *uncore = gt->uncore;
 166
 167         intel_uncore_write(uncore, RING_CTL(base), 0);
 168         intel_uncore_write(uncore, RING_HEAD(base), 0);
 169         intel_uncore_write(uncore, RING_TAIL(base), 0);
 170         intel_uncore_write(uncore, RING_START(base), 0);
 171 }
 172
 173 static void init_unused_rings(struct intel_gt *gt)
 174 {
 175         struct drm_i915_private *i915 = gt->i915;
 176
 177         if (IS_I830(i915)) {
 178                 init_unused_ring(gt, PRB1_BASE);
 179                 init_unused_ring(gt, SRB0_BASE);
 180                 init_unused_ring(gt, SRB1_BASE);
 181                 init_unused_ring(gt, SRB2_BASE);
 182                 init_unused_ring(gt, SRB3_BASE);
 183         } else if (GRAPHICS_VER(i915) == 2) {
 184                 init_unused_ring(gt, SRB0_BASE);
 185                 init_unused_ring(gt, SRB1_BASE);
 186         } else if (GRAPHICS_VER(i915) == 3) {
 187                 init_unused_ring(gt, PRB1_BASE);
 188                 init_unused_ring(gt, PRB2_BASE);
 189         }
 190 }
 191
 192 int intel_gt_init_hw(struct intel_gt *gt)
 193 {
 194         struct drm_i915_private *i915 = gt->i915;
 195         struct intel_uncore *uncore = gt->uncore;
 196         int ret;
 197
 198         gt->last_init_time = ktime_get();
 199
 200         /* Double layer security blanket, see i915_gem_init() */
 201         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 202
 203         if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
 204                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 205
 206         if (IS_HASWELL(i915))
 207                 intel_uncore_write(uncore,
 208                                    MI_PREDICATE_RESULT_2,
 209                                    IS_HSW_GT3(i915) ?
 210                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 211
 212         /* Apply the GT workarounds... */
 213         intel_gt_apply_workarounds(gt);
 214         /* ...and determine whether they are sticking. */
 215         intel_gt_verify_workarounds(gt, "init");
 216
 217         intel_gt_init_swizzling(gt);
 218
 219         /*
 220          * At least 830 can leave some of the unused rings
 221          * "active" (ie. head != tail) after resume which
 222          * will prevent c3 entry. Makes sure all unused rings
 223          * are totally idle.
 224          */
 225         init_unused_rings(gt);
 226
 227         ret = i915_ppgtt_init_hw(gt);
 228         if (ret) {
 229                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 230                 goto out;
 231         }
 232
 233         /* We can't enable contexts until all firmware is loaded */
 234         ret = intel_uc_init_hw(&gt->uc);
 235         if (ret) {
 236                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 237                 goto out;
 238         }
 239
 240         intel_mocs_init(gt);
 241
 242 out:
 243         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 244         return ret;
 245 }
 246
 247 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 248 {
 249         intel_uncore_rmw(uncore, reg, 0, set);
 250 }
 251
 252 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
 253 {
 254         intel_uncore_rmw(uncore, reg, clr, 0);
 255 }
 256
 257 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 258 {
 259         intel_uncore_rmw(uncore, reg, 0, 0);
 260 }
 261
 262 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
 263 {
 264         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 265         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 266 }
 267
 268 void
 269 intel_gt_clear_error_registers(struct intel_gt *gt,
 270                                intel_engine_mask_t engine_mask)
 271 {
 272         struct drm_i915_private *i915 = gt->i915;
 273         struct intel_uncore *uncore = gt->uncore;
 274         u32 eir;
 275
 276         if (GRAPHICS_VER(i915) != 2)
 277                 clear_register(uncore, PGTBL_ER);
 278
 279         if (GRAPHICS_VER(i915) < 4)
 280                 clear_register(uncore, IPEIR(RENDER_RING_BASE));
 281         else
 282                 clear_register(uncore, IPEIR_I965);
 283
 284         clear_register(uncore, EIR);
 285         eir = intel_uncore_read(uncore, EIR);
 286         if (eir) {
 287                 /*
 288                  * some errors might have become stuck,
 289                  * mask them.
 290                  */
 291                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
 292                 rmw_set(uncore, EMR, eir);
 293                 intel_uncore_write(uncore, GEN2_IIR,
 294                                    I915_MASTER_ERROR_INTERRUPT);
 295         }
 296
 297         if (GRAPHICS_VER(i915) >= 12) {
 298                 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
 299                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 300         } else if (GRAPHICS_VER(i915) >= 8) {
 301                 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
 302                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 303         } else if (GRAPHICS_VER(i915) >= 6) {
 304                 struct intel_engine_cs *engine;
 305                 enum intel_engine_id id;
 306
 307                 for_each_engine_masked(engine, gt, engine_mask, id)
 308                         gen6_clear_engine_error_register(engine);
 309         }
 310 }
 311
 312 static void gen6_check_faults(struct intel_gt *gt)
 313 {
 314         struct intel_engine_cs *engine;
 315         enum intel_engine_id id;
 316         u32 fault;
 317
 318         for_each_engine(engine, gt, id) {
 319                 fault = GEN6_RING_FAULT_REG_READ(engine);
 320                 if (fault & RING_FAULT_VALID) {
 321                         drm_dbg(&engine->i915->drm, "Unexpected fault\n"
 322                                 "\tAddr: 0x%08lx\n"
 323                                 "\tAddress space: %s\n"
 324                                 "\tSource ID: %d\n"
 325                                 "\tType: %d\n",
 326                                 fault & PAGE_MASK,
 327                                 fault & RING_FAULT_GTTSEL_MASK ?
 328                                 "GGTT" : "PPGTT",
 329                                 RING_FAULT_SRCID(fault),
 330                                 RING_FAULT_FAULT_TYPE(fault));
 331                 }
 332         }
 333 }
 334
 335 static void gen8_check_faults(struct intel_gt *gt)
 336 {
 337         struct intel_uncore *uncore = gt->uncore;
 338         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 339         u32 fault;
 340
 341         if (GRAPHICS_VER(gt->i915) >= 12) {
 342                 fault_reg = GEN12_RING_FAULT_REG;
 343                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 344                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 345         } else {
 346                 fault_reg = GEN8_RING_FAULT_REG;
 347                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 348                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 349         }
 350
 351         fault = intel_uncore_read(uncore, fault_reg);
 352         if (fault & RING_FAULT_VALID) {
 353                 u32 fault_data0, fault_data1;
 354                 u64 fault_addr;
 355
 356                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 357                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 358
 359                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 360                              ((u64)fault_data0 << 12);
 361
 362                 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
 363                         "\tAddr: 0x%08x_%08x\n"
 364                         "\tAddress space: %s\n"
 365                         "\tEngine ID: %d\n"
 366                         "\tSource ID: %d\n"
 367                         "\tType: %d\n",
 368                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 369                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 370                         GEN8_RING_FAULT_ENGINE_ID(fault),
 371                         RING_FAULT_SRCID(fault),
 372                         RING_FAULT_FAULT_TYPE(fault));
 373         }
 374 }
 375
 376 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 377 {
 378         struct drm_i915_private *i915 = gt->i915;
 379
 380         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 381         if (GRAPHICS_VER(i915) >= 8)
 382                 gen8_check_faults(gt);
 383         else if (GRAPHICS_VER(i915) >= 6)
 384                 gen6_check_faults(gt);
 385         else
 386                 return;
 387
 388         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 389 }
 390
 391 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 392 {
 393         struct intel_uncore *uncore = gt->uncore;
 394         intel_wakeref_t wakeref;
 395
 396         /*
 397          * No actual flushing is required for the GTT write domain for reads
 398          * from the GTT domain. Writes to it "immediately" go to main memory
 399          * as far as we know, so there's no chipset flush. It also doesn't
 400          * land in the GPU render cache.
 401          *
 402          * However, we do have to enforce the order so that all writes through
 403          * the GTT land before any writes to the device, such as updates to
 404          * the GATT itself.
 405          *
 406          * We also have to wait a bit for the writes to land from the GTT.
 407          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 408          * timing. This issue has only been observed when switching quickly
 409          * between GTT writes and CPU reads from inside the kernel on recent hw,
 410          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 411          * system agents we cannot reproduce this behaviour, until Cannonlake
 412          * that was!).
 413          */
 414
 415         wmb();
 416
 417         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 418                 return;
 419
 420         intel_gt_chipset_flush(gt);
 421
 422         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 423                 unsigned long flags;
 424
 425                 spin_lock_irqsave(&uncore->lock, flags);
 426                 intel_uncore_posting_read_fw(uncore,
 427                                              RING_HEAD(RENDER_RING_BASE));
 428                 spin_unlock_irqrestore(&uncore->lock, flags);
 429         }
 430 }
 431
 432 void intel_gt_chipset_flush(struct intel_gt *gt)
 433 {
 434         wmb();
 435         if (GRAPHICS_VER(gt->i915) < 6)
 436                 intel_gtt_chipset_flush();
 437 }
 438
 439 void intel_gt_driver_register(struct intel_gt *gt)
 440 {
 441         intel_rps_driver_register(&gt->rps);
 442
 443         intel_gt_debugfs_register(gt);
 444 }
 445
 446 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 447 {
 448         struct drm_i915_private *i915 = gt->i915;
 449         struct drm_i915_gem_object *obj;
 450         struct i915_vma *vma;
 451         int ret;
 452
 453         obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
 454         if (IS_ERR(obj))
 455                 obj = i915_gem_object_create_stolen(i915, size);
 456         if (IS_ERR(obj))
 457                 obj = i915_gem_object_create_internal(i915, size);
 458         if (IS_ERR(obj)) {
 459                 drm_err(&i915->drm, "Failed to allocate scratch page\n");
 460                 return PTR_ERR(obj);
 461         }
 462
 463         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 464         if (IS_ERR(vma)) {
 465                 ret = PTR_ERR(vma);
 466                 goto err_unref;
 467         }
 468
 469         ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
 470         if (ret)
 471                 goto err_unref;
 472
 473         gt->scratch = i915_vma_make_unshrinkable(vma);
 474
 475         return 0;
 476
 477 err_unref:
 478         i915_gem_object_put(obj);
 479         return ret;
 480 }
 481
 482 static void intel_gt_fini_scratch(struct intel_gt *gt)
 483 {
 484         i915_vma_unpin_and_release(&gt->scratch, 0);
 485 }
 486
 487 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 488 {
 489         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 490                 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
 491         else
 492                 return i915_vm_get(&gt->ggtt->vm);
 493 }
 494
 495 static int __engines_record_defaults(struct intel_gt *gt)
 496 {
 497         struct i915_request *requests[I915_NUM_ENGINES] = {};
 498         struct intel_engine_cs *engine;
 499         enum intel_engine_id id;
 500         int err = 0;
 501
 502         /*
 503          * As we reset the gpu during very early sanitisation, the current
 504          * register state on the GPU should reflect its defaults values.
 505          * We load a context onto the hw (with restore-inhibit), then switch
 506          * over to a second context to save that default register state. We
 507          * can then prime every new context with that state so they all start
 508          * from the same default HW values.
 509          */
 510
 511         for_each_engine(engine, gt, id) {
 512                 struct intel_renderstate so;
 513                 struct intel_context *ce;
 514                 struct i915_request *rq;
 515
 516                 /* We must be able to switch to something! */
 517                 GEM_BUG_ON(!engine->kernel_context);
 518
 519                 ce = intel_context_create(engine);
 520                 if (IS_ERR(ce)) {
 521                         err = PTR_ERR(ce);
 522                         goto out;
 523                 }
 524
 525                 err = intel_renderstate_init(&so, ce);
 526                 if (err)
 527                         goto err;
 528
 529                 rq = i915_request_create(ce);
 530                 if (IS_ERR(rq)) {
 531                         err = PTR_ERR(rq);
 532                         goto err_fini;
 533                 }
 534
 535                 err = intel_engine_emit_ctx_wa(rq);
 536                 if (err)
 537                         goto err_rq;
 538
 539                 err = intel_renderstate_emit(&so, rq);
 540                 if (err)
 541                         goto err_rq;
 542
 543 err_rq:
 544                 requests[id] = i915_request_get(rq);
 545                 i915_request_add(rq);
 546 err_fini:
 547                 intel_renderstate_fini(&so, ce);
 548 err:
 549                 if (err) {
 550                         intel_context_put(ce);
 551                         goto out;
 552                 }
 553         }
 554
 555         /* Flush the default context image to memory, and enable powersaving. */
 556         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 557                 err = -EIO;
 558                 goto out;
 559         }
 560
 561         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 562                 struct i915_request *rq;
 563                 struct file *state;
 564
 565                 rq = requests[id];
 566                 if (!rq)
 567                         continue;
 568
 569                 if (rq->fence.error) {
 570                         err = -EIO;
 571                         goto out;
 572                 }
 573
 574                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 575                 if (!rq->context->state)
 576                         continue;
 577
 578                 /* Keep a copy of the state's backing pages; free the obj */
 579                 state = shmem_create_from_object(rq->context->state->obj);
 580                 if (IS_ERR(state)) {
 581                         err = PTR_ERR(state);
 582                         goto out;
 583                 }
 584                 rq->engine->default_state = state;
 585         }
 586
 587 out:
 588         /*
 589          * If we have to abandon now, we expect the engines to be idle
 590          * and ready to be torn-down. The quickest way we can accomplish
 591          * this is by declaring ourselves wedged.
 592          */
 593         if (err)
 594                 intel_gt_set_wedged(gt);
 595
 596         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 597                 struct intel_context *ce;
 598                 struct i915_request *rq;
 599
 600                 rq = requests[id];
 601                 if (!rq)
 602                         continue;
 603
 604                 ce = rq->context;
 605                 i915_request_put(rq);
 606                 intel_context_put(ce);
 607         }
 608         return err;
 609 }
 610
 611 static int __engines_verify_workarounds(struct intel_gt *gt)
 612 {
 613         struct intel_engine_cs *engine;
 614         enum intel_engine_id id;
 615         int err = 0;
 616
 617         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 618                 return 0;
 619
 620         for_each_engine(engine, gt, id) {
 621                 if (intel_engine_verify_workarounds(engine, "load"))
 622                         err = -EIO;
 623         }
 624
 625         /* Flush and restore the kernel context for safety */
 626         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
 627                 err = -EIO;
 628
 629         return err;
 630 }
 631
 632 static void __intel_gt_disable(struct intel_gt *gt)
 633 {
 634         intel_gt_set_wedged_on_fini(gt);
 635
 636         intel_gt_suspend_prepare(gt);
 637         intel_gt_suspend_late(gt);
 638
 639         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 640 }
 641
 642 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
 643 {
 644         long remaining_timeout;
 645
 646         /* If the device is asleep, we have no requests outstanding */
 647         if (!intel_gt_pm_is_awake(gt))
 648                 return 0;
 649
 650         while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
 651                                                            &remaining_timeout)) > 0) {
 652                 cond_resched();
 653                 if (signal_pending(current))
 654                         return -EINTR;
 655         }
 656
 657         return timeout ? timeout : intel_uc_wait_for_idle(&gt->uc,
 658                                                           remaining_timeout);
 659 }
 660
 661 int intel_gt_init(struct intel_gt *gt)
 662 {
 663         int err;
 664
 665         err = i915_inject_probe_error(gt->i915, -ENODEV);
 666         if (err)
 667                 return err;
 668
 669         intel_gt_init_workarounds(gt);
 670
 671         /*
 672          * This is just a security blanket to placate dragons.
 673          * On some systems, we very sporadically observe that the first TLBs
 674          * used by the CS may be stale, despite us poking the TLB reset. If
 675          * we hold the forcewake during initialisation these problems
 676          * just magically go away.
 677          */
 678         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 679
 680         err = intel_gt_init_scratch(gt,
 681                                     GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
 682         if (err)
 683                 goto out_fw;
 684
 685         intel_gt_pm_init(gt);
 686
 687         gt->vm = kernel_vm(gt);
 688         if (!gt->vm) {
 689                 err = -ENOMEM;
 690                 goto err_pm;
 691         }
 692
 693         intel_set_mocs_index(gt);
 694
 695         err = intel_engines_init(gt);
 696         if (err)
 697                 goto err_engines;
 698
 699         err = intel_uc_init(&gt->uc);
 700         if (err)
 701                 goto err_engines;
 702
 703         err = intel_gt_resume(gt);
 704         if (err)
 705                 goto err_uc_init;
 706
 707         err = __engines_record_defaults(gt);
 708         if (err)
 709                 goto err_gt;
 710
 711         err = __engines_verify_workarounds(gt);
 712         if (err)
 713                 goto err_gt;
 714
 715         intel_uc_init_late(&gt->uc);
 716
 717         err = i915_inject_probe_error(gt->i915, -EIO);
 718         if (err)
 719                 goto err_gt;
 720
 721         intel_migrate_init(&gt->migrate, gt);
 722
 723         intel_pxp_init(&gt->pxp);
 724
 725         goto out_fw;
 726 err_gt:
 727         __intel_gt_disable(gt);
 728         intel_uc_fini_hw(&gt->uc);
 729 err_uc_init:
 730         intel_uc_fini(&gt->uc);
 731 err_engines:
 732         intel_engines_release(gt);
 733         i915_vm_put(fetch_and_zero(&gt->vm));
 734 err_pm:
 735         intel_gt_pm_fini(gt);
 736         intel_gt_fini_scratch(gt);
 737 out_fw:
 738         if (err)
 739                 intel_gt_set_wedged_on_init(gt);
 740         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 741         return err;
 742 }
 743
 744 void intel_gt_driver_remove(struct intel_gt *gt)
 745 {
 746         __intel_gt_disable(gt);
 747
 748         intel_migrate_fini(&gt->migrate);
 749         intel_uc_driver_remove(&gt->uc);
 750
 751         intel_engines_release(gt);
 752
 753         intel_gt_flush_buffer_pool(gt);
 754 }
 755
 756 void intel_gt_driver_unregister(struct intel_gt *gt)
 757 {
 758         intel_wakeref_t wakeref;
 759
 760         intel_rps_driver_unregister(&gt->rps);
 761
 762         intel_pxp_fini(&gt->pxp);
 763
 764         /*
 765          * Upon unregistering the device to prevent any new users, cancel
 766          * all in-flight requests so that we can quickly unbind the active
 767          * resources.
 768          */
 769         intel_gt_set_wedged_on_fini(gt);
 770
 771         /* Scrub all HW state upon release */
 772         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 773                 __intel_gt_reset(gt, ALL_ENGINES);
 774 }
 775
 776 void intel_gt_driver_release(struct intel_gt *gt)
 777 {
 778         struct i915_address_space *vm;
 779
 780         vm = fetch_and_zero(&gt->vm);
 781         if (vm) /* FIXME being called twice on error paths :( */
 782                 i915_vm_put(vm);
 783
 784         intel_wa_list_free(&gt->wa_list);
 785         intel_gt_pm_fini(gt);
 786         intel_gt_fini_scratch(gt);
 787         intel_gt_fini_buffer_pool(gt);
 788 }
 789
 790 void intel_gt_driver_late_release(struct intel_gt *gt)
 791 {
 792         /* We need to wait for inflight RCU frees to release their grip */
 793         rcu_barrier();
 794
 795         intel_uc_driver_late_release(&gt->uc);
 796         intel_gt_fini_requests(gt);
 797         intel_gt_fini_reset(gt);
 798         intel_gt_fini_timelines(gt);
 799         intel_engines_free(gt);
 800 }
 801
 802 /**
 803  * intel_gt_reg_needs_read_steering - determine whether a register read
 804  *     requires explicit steering
 805  * @gt: GT structure
 806  * @reg: the register to check steering requirements for
 807  * @type: type of multicast steering to check
 808  *
 809  * Determines whether @reg needs explicit steering of a specific type for
 810  * reads.
 811  *
 812  * Returns false if @reg does not belong to a register range of the given
 813  * steering type, or if the default (subslice-based) steering IDs are suitable
 814  * for @type steering too.
 815  */
 816 static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
 817                                              i915_reg_t reg,
 818                                              enum intel_steering_type type)
 819 {
 820         const u32 offset = i915_mmio_reg_offset(reg);
 821         const struct intel_mmio_range *entry;
 822
 823         if (likely(!intel_gt_needs_read_steering(gt, type)))
 824                 return false;
 825
 826         for (entry = gt->steering_table[type]; entry->end; entry++) {
 827                 if (offset >= entry->start && offset <= entry->end)
 828                         return true;
 829         }
 830
 831         return false;
 832 }
 833
 834 /**
 835  * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering
 836  * @gt: GT structure
 837  * @type: multicast register type
 838  * @sliceid: Slice ID returned
 839  * @subsliceid: Subslice ID returned
 840  *
 841  * Determines sliceid and subsliceid values that will steer reads
 842  * of a specific multicast register class to a valid value.
 843  */
 844 static void intel_gt_get_valid_steering(struct intel_gt *gt,
 845                                         enum intel_steering_type type,
 846                                         u8 *sliceid, u8 *subsliceid)
 847 {
 848         switch (type) {
 849         case L3BANK:
 850                 GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
 851
 852                 *sliceid = 0;           /* unused */
 853                 *subsliceid = __ffs(gt->info.l3bank_mask);
 854                 break;
 855         case MSLICE:
 856                 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
 857
 858                 *sliceid = __ffs(gt->info.mslice_mask);
 859                 *subsliceid = 0;        /* unused */
 860                 break;
 861         case LNCF:
 862                 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
 863
 864                 /*
 865                  * An LNCF is always present if its mslice is present, so we
 866                  * can safely just steer to LNCF 0 in all cases.
 867                  */
 868                 *sliceid = __ffs(gt->info.mslice_mask) << 1;
 869                 *subsliceid = 0;        /* unused */
 870                 break;
 871         default:
 872                 MISSING_CASE(type);
 873                 *sliceid = 0;
 874                 *subsliceid = 0;
 875         }
 876 }
 877
 878 /**
 879  * intel_gt_read_register_fw - reads a GT register with support for multicast
 880  * @gt: GT structure
 881  * @reg: register to read
 882  *
 883  * This function will read a GT register.  If the register is a multicast
 884  * register, the read will be steered to a valid instance (i.e., one that
 885  * isn't fused off or powered down by power gating).
 886  *
 887  * Returns the value from a valid instance of @reg.
 888  */
 889 u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
 890 {
 891         int type;
 892         u8 sliceid, subsliceid;
 893
 894         for (type = 0; type < NUM_STEERING_TYPES; type++) {
 895                 if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
 896                         intel_gt_get_valid_steering(gt, type, &sliceid,
 897                                                     &subsliceid);
 898                         return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
 899                                                                       reg,
 900                                                                       sliceid,
 901                                                                       subsliceid);
 902                 }
 903         }
 904
 905         return intel_uncore_read_fw(gt->uncore, reg);
 906 }
 907
 908 void intel_gt_info_print(const struct intel_gt_info *info,
 909                          struct drm_printer *p)
 910 {
 911         drm_printf(p, "available engines: %x\n", info->engine_mask);
 912
 913         intel_sseu_dump(&info->sseu, p);
 914 }