drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include "debugfs_gt.h"
   7
   8 #include "gem/i915_gem_lmem.h"
   9 #include "i915_drv.h"
  10 #include "intel_context.h"
  11 #include "intel_gt.h"
  12 #include "intel_gt_buffer_pool.h"
  13 #include "intel_gt_clock_utils.h"
  14 #include "intel_gt_pm.h"
  15 #include "intel_gt_requests.h"
  16 #include "intel_mocs.h"
  17 #include "intel_rc6.h"
  18 #include "intel_renderstate.h"
  19 #include "intel_rps.h"
  20 #include "intel_uncore.h"
  21 #include "intel_pm.h"
  22 #include "shmem_utils.h"
  23
  24 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  25 {
  26         gt->i915 = i915;
  27         gt->uncore = &i915->uncore;
  28
  29         spin_lock_init(&gt->irq_lock);
  30
  31         INIT_LIST_HEAD(&gt->closed_vma);
  32         spin_lock_init(&gt->closed_lock);
  33
  34         intel_gt_init_buffer_pool(gt);
  35         intel_gt_init_reset(gt);
  36         intel_gt_init_requests(gt);
  37         intel_gt_init_timelines(gt);
  38         intel_gt_pm_init_early(gt);
  39
  40         intel_rps_init_early(&gt->rps);
  41         intel_uc_init_early(&gt->uc);
  42 }
  43
  44 int intel_gt_probe_lmem(struct intel_gt *gt)
  45 {
  46         struct drm_i915_private *i915 = gt->i915;
  47         struct intel_memory_region *mem;
  48         int id;
  49         int err;
  50
  51         mem = intel_gt_setup_lmem(gt);
  52         if (mem == ERR_PTR(-ENODEV))
  53                 mem = intel_gt_setup_fake_lmem(gt);
  54         if (IS_ERR(mem)) {
  55                 err = PTR_ERR(mem);
  56                 if (err == -ENODEV)
  57                         return 0;
  58
  59                 drm_err(&i915->drm,
  60                         "Failed to setup region(%d) type=%d\n",
  61                         err, INTEL_MEMORY_LOCAL);
  62                 return err;
  63         }
  64
  65         id = INTEL_REGION_LMEM;
  66
  67         mem->id = id;
  68         mem->type = INTEL_MEMORY_LOCAL;
  69         mem->instance = 0;
  70
  71         GEM_BUG_ON(!HAS_REGION(i915, id));
  72         GEM_BUG_ON(i915->mm.regions[id]);
  73         i915->mm.regions[id] = mem;
  74
  75         return 0;
  76 }
  77
  78 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
  79 {
  80         gt->ggtt = ggtt;
  81 }
  82
  83 int intel_gt_init_mmio(struct intel_gt *gt)
  84 {
  85         intel_gt_init_clock_frequency(gt);
  86
  87         intel_uc_init_mmio(&gt->uc);
  88         intel_sseu_info_init(gt);
  89
  90         return intel_engines_init_mmio(gt);
  91 }
  92
  93 static void init_unused_ring(struct intel_gt *gt, u32 base)
  94 {
  95         struct intel_uncore *uncore = gt->uncore;
  96
  97         intel_uncore_write(uncore, RING_CTL(base), 0);
  98         intel_uncore_write(uncore, RING_HEAD(base), 0);
  99         intel_uncore_write(uncore, RING_TAIL(base), 0);
 100         intel_uncore_write(uncore, RING_START(base), 0);
 101 }
 102
 103 static void init_unused_rings(struct intel_gt *gt)
 104 {
 105         struct drm_i915_private *i915 = gt->i915;
 106
 107         if (IS_I830(i915)) {
 108                 init_unused_ring(gt, PRB1_BASE);
 109                 init_unused_ring(gt, SRB0_BASE);
 110                 init_unused_ring(gt, SRB1_BASE);
 111                 init_unused_ring(gt, SRB2_BASE);
 112                 init_unused_ring(gt, SRB3_BASE);
 113         } else if (IS_GEN(i915, 2)) {
 114                 init_unused_ring(gt, SRB0_BASE);
 115                 init_unused_ring(gt, SRB1_BASE);
 116         } else if (IS_GEN(i915, 3)) {
 117                 init_unused_ring(gt, PRB1_BASE);
 118                 init_unused_ring(gt, PRB2_BASE);
 119         }
 120 }
 121
 122 int intel_gt_init_hw(struct intel_gt *gt)
 123 {
 124         struct drm_i915_private *i915 = gt->i915;
 125         struct intel_uncore *uncore = gt->uncore;
 126         int ret;
 127
 128         gt->last_init_time = ktime_get();
 129
 130         /* Double layer security blanket, see i915_gem_init() */
 131         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 132
 133         if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
 134                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 135
 136         if (IS_HASWELL(i915))
 137                 intel_uncore_write(uncore,
 138                                    MI_PREDICATE_RESULT_2,
 139                                    IS_HSW_GT3(i915) ?
 140                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 141
 142         /* Apply the GT workarounds... */
 143         intel_gt_apply_workarounds(gt);
 144         /* ...and determine whether they are sticking. */
 145         intel_gt_verify_workarounds(gt, "init");
 146
 147         intel_gt_init_swizzling(gt);
 148
 149         /*
 150          * At least 830 can leave some of the unused rings
 151          * "active" (ie. head != tail) after resume which
 152          * will prevent c3 entry. Makes sure all unused rings
 153          * are totally idle.
 154          */
 155         init_unused_rings(gt);
 156
 157         ret = i915_ppgtt_init_hw(gt);
 158         if (ret) {
 159                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 160                 goto out;
 161         }
 162
 163         /* We can't enable contexts until all firmware is loaded */
 164         ret = intel_uc_init_hw(&gt->uc);
 165         if (ret) {
 166                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 167                 goto out;
 168         }
 169
 170         intel_mocs_init(gt);
 171
 172 out:
 173         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 174         return ret;
 175 }
 176
 177 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 178 {
 179         intel_uncore_rmw(uncore, reg, 0, set);
 180 }
 181
 182 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
 183 {
 184         intel_uncore_rmw(uncore, reg, clr, 0);
 185 }
 186
 187 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 188 {
 189         intel_uncore_rmw(uncore, reg, 0, 0);
 190 }
 191
 192 static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
 193 {
 194         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 195         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 196 }
 197
 198 void
 199 intel_gt_clear_error_registers(struct intel_gt *gt,
 200                                intel_engine_mask_t engine_mask)
 201 {
 202         struct drm_i915_private *i915 = gt->i915;
 203         struct intel_uncore *uncore = gt->uncore;
 204         u32 eir;
 205
 206         if (!IS_GEN(i915, 2))
 207                 clear_register(uncore, PGTBL_ER);
 208
 209         if (INTEL_GEN(i915) < 4)
 210                 clear_register(uncore, IPEIR(RENDER_RING_BASE));
 211         else
 212                 clear_register(uncore, IPEIR_I965);
 213
 214         clear_register(uncore, EIR);
 215         eir = intel_uncore_read(uncore, EIR);
 216         if (eir) {
 217                 /*
 218                  * some errors might have become stuck,
 219                  * mask them.
 220                  */
 221                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
 222                 rmw_set(uncore, EMR, eir);
 223                 intel_uncore_write(uncore, GEN2_IIR,
 224                                    I915_MASTER_ERROR_INTERRUPT);
 225         }
 226
 227         if (INTEL_GEN(i915) >= 12) {
 228                 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
 229                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 230         } else if (INTEL_GEN(i915) >= 8) {
 231                 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
 232                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 233         } else if (INTEL_GEN(i915) >= 6) {
 234                 struct intel_engine_cs *engine;
 235                 enum intel_engine_id id;
 236
 237                 for_each_engine_masked(engine, gt, engine_mask, id)
 238                         gen8_clear_engine_error_register(engine);
 239         }
 240 }
 241
 242 static void gen6_check_faults(struct intel_gt *gt)
 243 {
 244         struct intel_engine_cs *engine;
 245         enum intel_engine_id id;
 246         u32 fault;
 247
 248         for_each_engine(engine, gt, id) {
 249                 fault = GEN6_RING_FAULT_REG_READ(engine);
 250                 if (fault & RING_FAULT_VALID) {
 251                         drm_dbg(&engine->i915->drm, "Unexpected fault\n"
 252                                 "\tAddr: 0x%08lx\n"
 253                                 "\tAddress space: %s\n"
 254                                 "\tSource ID: %d\n"
 255                                 "\tType: %d\n",
 256                                 fault & PAGE_MASK,
 257                                 fault & RING_FAULT_GTTSEL_MASK ?
 258                                 "GGTT" : "PPGTT",
 259                                 RING_FAULT_SRCID(fault),
 260                                 RING_FAULT_FAULT_TYPE(fault));
 261                 }
 262         }
 263 }
 264
 265 static void gen8_check_faults(struct intel_gt *gt)
 266 {
 267         struct intel_uncore *uncore = gt->uncore;
 268         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 269         u32 fault;
 270
 271         if (INTEL_GEN(gt->i915) >= 12) {
 272                 fault_reg = GEN12_RING_FAULT_REG;
 273                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 274                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 275         } else {
 276                 fault_reg = GEN8_RING_FAULT_REG;
 277                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 278                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 279         }
 280
 281         fault = intel_uncore_read(uncore, fault_reg);
 282         if (fault & RING_FAULT_VALID) {
 283                 u32 fault_data0, fault_data1;
 284                 u64 fault_addr;
 285
 286                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 287                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 288
 289                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 290                              ((u64)fault_data0 << 12);
 291
 292                 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
 293                         "\tAddr: 0x%08x_%08x\n"
 294                         "\tAddress space: %s\n"
 295                         "\tEngine ID: %d\n"
 296                         "\tSource ID: %d\n"
 297                         "\tType: %d\n",
 298                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 299                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 300                         GEN8_RING_FAULT_ENGINE_ID(fault),
 301                         RING_FAULT_SRCID(fault),
 302                         RING_FAULT_FAULT_TYPE(fault));
 303         }
 304 }
 305
 306 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 307 {
 308         struct drm_i915_private *i915 = gt->i915;
 309
 310         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 311         if (INTEL_GEN(i915) >= 8)
 312                 gen8_check_faults(gt);
 313         else if (INTEL_GEN(i915) >= 6)
 314                 gen6_check_faults(gt);
 315         else
 316                 return;
 317
 318         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 319 }
 320
 321 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 322 {
 323         struct intel_uncore *uncore = gt->uncore;
 324         intel_wakeref_t wakeref;
 325
 326         /*
 327          * No actual flushing is required for the GTT write domain for reads
 328          * from the GTT domain. Writes to it "immediately" go to main memory
 329          * as far as we know, so there's no chipset flush. It also doesn't
 330          * land in the GPU render cache.
 331          *
 332          * However, we do have to enforce the order so that all writes through
 333          * the GTT land before any writes to the device, such as updates to
 334          * the GATT itself.
 335          *
 336          * We also have to wait a bit for the writes to land from the GTT.
 337          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 338          * timing. This issue has only been observed when switching quickly
 339          * between GTT writes and CPU reads from inside the kernel on recent hw,
 340          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 341          * system agents we cannot reproduce this behaviour, until Cannonlake
 342          * that was!).
 343          */
 344
 345         wmb();
 346
 347         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 348                 return;
 349
 350         intel_gt_chipset_flush(gt);
 351
 352         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 353                 unsigned long flags;
 354
 355                 spin_lock_irqsave(&uncore->lock, flags);
 356                 intel_uncore_posting_read_fw(uncore,
 357                                              RING_HEAD(RENDER_RING_BASE));
 358                 spin_unlock_irqrestore(&uncore->lock, flags);
 359         }
 360 }
 361
 362 void intel_gt_chipset_flush(struct intel_gt *gt)
 363 {
 364         wmb();
 365         if (INTEL_GEN(gt->i915) < 6)
 366                 intel_gtt_chipset_flush();
 367 }
 368
 369 void intel_gt_driver_register(struct intel_gt *gt)
 370 {
 371         intel_rps_driver_register(&gt->rps);
 372
 373         debugfs_gt_register(gt);
 374 }
 375
 376 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 377 {
 378         struct drm_i915_private *i915 = gt->i915;
 379         struct drm_i915_gem_object *obj;
 380         struct i915_vma *vma;
 381         int ret;
 382
 383         obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
 384         if (IS_ERR(obj))
 385                 obj = i915_gem_object_create_stolen(i915, size);
 386         if (IS_ERR(obj))
 387                 obj = i915_gem_object_create_internal(i915, size);
 388         if (IS_ERR(obj)) {
 389                 drm_err(&i915->drm, "Failed to allocate scratch page\n");
 390                 return PTR_ERR(obj);
 391         }
 392
 393         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 394         if (IS_ERR(vma)) {
 395                 ret = PTR_ERR(vma);
 396                 goto err_unref;
 397         }
 398
 399         ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
 400         if (ret)
 401                 goto err_unref;
 402
 403         gt->scratch = i915_vma_make_unshrinkable(vma);
 404
 405         return 0;
 406
 407 err_unref:
 408         i915_gem_object_put(obj);
 409         return ret;
 410 }
 411
 412 static void intel_gt_fini_scratch(struct intel_gt *gt)
 413 {
 414         i915_vma_unpin_and_release(&gt->scratch, 0);
 415 }
 416
 417 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 418 {
 419         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 420                 return &i915_ppgtt_create(gt)->vm;
 421         else
 422                 return i915_vm_get(&gt->ggtt->vm);
 423 }
 424
 425 static int __engines_record_defaults(struct intel_gt *gt)
 426 {
 427         struct i915_request *requests[I915_NUM_ENGINES] = {};
 428         struct intel_engine_cs *engine;
 429         enum intel_engine_id id;
 430         int err = 0;
 431
 432         /*
 433          * As we reset the gpu during very early sanitisation, the current
 434          * register state on the GPU should reflect its defaults values.
 435          * We load a context onto the hw (with restore-inhibit), then switch
 436          * over to a second context to save that default register state. We
 437          * can then prime every new context with that state so they all start
 438          * from the same default HW values.
 439          */
 440
 441         for_each_engine(engine, gt, id) {
 442                 struct intel_renderstate so;
 443                 struct intel_context *ce;
 444                 struct i915_request *rq;
 445
 446                 /* We must be able to switch to something! */
 447                 GEM_BUG_ON(!engine->kernel_context);
 448
 449                 ce = intel_context_create(engine);
 450                 if (IS_ERR(ce)) {
 451                         err = PTR_ERR(ce);
 452                         goto out;
 453                 }
 454
 455                 err = intel_renderstate_init(&so, ce);
 456                 if (err)
 457                         goto err;
 458
 459                 rq = i915_request_create(ce);
 460                 if (IS_ERR(rq)) {
 461                         err = PTR_ERR(rq);
 462                         goto err_fini;
 463                 }
 464
 465                 err = intel_engine_emit_ctx_wa(rq);
 466                 if (err)
 467                         goto err_rq;
 468
 469                 err = intel_renderstate_emit(&so, rq);
 470                 if (err)
 471                         goto err_rq;
 472
 473 err_rq:
 474                 requests[id] = i915_request_get(rq);
 475                 i915_request_add(rq);
 476 err_fini:
 477                 intel_renderstate_fini(&so, ce);
 478 err:
 479                 if (err) {
 480                         intel_context_put(ce);
 481                         goto out;
 482                 }
 483         }
 484
 485         /* Flush the default context image to memory, and enable powersaving. */
 486         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 487                 err = -EIO;
 488                 goto out;
 489         }
 490
 491         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 492                 struct i915_request *rq;
 493                 struct file *state;
 494
 495                 rq = requests[id];
 496                 if (!rq)
 497                         continue;
 498
 499                 if (rq->fence.error) {
 500                         err = -EIO;
 501                         goto out;
 502                 }
 503
 504                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 505                 if (!rq->context->state)
 506                         continue;
 507
 508                 /* Keep a copy of the state's backing pages; free the obj */
 509                 state = shmem_create_from_object(rq->context->state->obj);
 510                 if (IS_ERR(state)) {
 511                         err = PTR_ERR(state);
 512                         goto out;
 513                 }
 514                 rq->engine->default_state = state;
 515         }
 516
 517 out:
 518         /*
 519          * If we have to abandon now, we expect the engines to be idle
 520          * and ready to be torn-down. The quickest way we can accomplish
 521          * this is by declaring ourselves wedged.
 522          */
 523         if (err)
 524                 intel_gt_set_wedged(gt);
 525
 526         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 527                 struct intel_context *ce;
 528                 struct i915_request *rq;
 529
 530                 rq = requests[id];
 531                 if (!rq)
 532                         continue;
 533
 534                 ce = rq->context;
 535                 i915_request_put(rq);
 536                 intel_context_put(ce);
 537         }
 538         return err;
 539 }
 540
 541 static int __engines_verify_workarounds(struct intel_gt *gt)
 542 {
 543         struct intel_engine_cs *engine;
 544         enum intel_engine_id id;
 545         int err = 0;
 546
 547         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 548                 return 0;
 549
 550         for_each_engine(engine, gt, id) {
 551                 if (intel_engine_verify_workarounds(engine, "load"))
 552                         err = -EIO;
 553         }
 554
 555         /* Flush and restore the kernel context for safety */
 556         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
 557                 err = -EIO;
 558
 559         return err;
 560 }
 561
 562 static void __intel_gt_disable(struct intel_gt *gt)
 563 {
 564         intel_gt_set_wedged_on_fini(gt);
 565
 566         intel_gt_suspend_prepare(gt);
 567         intel_gt_suspend_late(gt);
 568
 569         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 570 }
 571
 572 int intel_gt_init(struct intel_gt *gt)
 573 {
 574         int err;
 575
 576         err = i915_inject_probe_error(gt->i915, -ENODEV);
 577         if (err)
 578                 return err;
 579
 580         /*
 581          * This is just a security blanket to placate dragons.
 582          * On some systems, we very sporadically observe that the first TLBs
 583          * used by the CS may be stale, despite us poking the TLB reset. If
 584          * we hold the forcewake during initialisation these problems
 585          * just magically go away.
 586          */
 587         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 588
 589         err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
 590         if (err)
 591                 goto out_fw;
 592
 593         intel_gt_pm_init(gt);
 594
 595         gt->vm = kernel_vm(gt);
 596         if (!gt->vm) {
 597                 err = -ENOMEM;
 598                 goto err_pm;
 599         }
 600
 601         err = intel_engines_init(gt);
 602         if (err)
 603                 goto err_engines;
 604
 605         err = intel_uc_init(&gt->uc);
 606         if (err)
 607                 goto err_engines;
 608
 609         err = intel_gt_resume(gt);
 610         if (err)
 611                 goto err_uc_init;
 612
 613         err = __engines_record_defaults(gt);
 614         if (err)
 615                 goto err_gt;
 616
 617         err = __engines_verify_workarounds(gt);
 618         if (err)
 619                 goto err_gt;
 620
 621         err = i915_inject_probe_error(gt->i915, -EIO);
 622         if (err)
 623                 goto err_gt;
 624
 625         goto out_fw;
 626 err_gt:
 627         __intel_gt_disable(gt);
 628         intel_uc_fini_hw(&gt->uc);
 629 err_uc_init:
 630         intel_uc_fini(&gt->uc);
 631 err_engines:
 632         intel_engines_release(gt);
 633         i915_vm_put(fetch_and_zero(&gt->vm));
 634 err_pm:
 635         intel_gt_pm_fini(gt);
 636         intel_gt_fini_scratch(gt);
 637 out_fw:
 638         if (err)
 639                 intel_gt_set_wedged_on_init(gt);
 640         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 641         return err;
 642 }
 643
 644 void intel_gt_driver_remove(struct intel_gt *gt)
 645 {
 646         __intel_gt_disable(gt);
 647
 648         intel_uc_driver_remove(&gt->uc);
 649
 650         intel_engines_release(gt);
 651 }
 652
 653 void intel_gt_driver_unregister(struct intel_gt *gt)
 654 {
 655         intel_wakeref_t wakeref;
 656
 657         intel_rps_driver_unregister(&gt->rps);
 658
 659         /*
 660          * Upon unregistering the device to prevent any new users, cancel
 661          * all in-flight requests so that we can quickly unbind the active
 662          * resources.
 663          */
 664         intel_gt_set_wedged(gt);
 665
 666         /* Scrub all HW state upon release */
 667         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 668                 __intel_gt_reset(gt, ALL_ENGINES);
 669 }
 670
 671 void intel_gt_driver_release(struct intel_gt *gt)
 672 {
 673         struct i915_address_space *vm;
 674
 675         vm = fetch_and_zero(&gt->vm);
 676         if (vm) /* FIXME being called twice on error paths :( */
 677                 i915_vm_put(vm);
 678
 679         intel_gt_pm_fini(gt);
 680         intel_gt_fini_scratch(gt);
 681         intel_gt_fini_buffer_pool(gt);
 682 }
 683
 684 void intel_gt_driver_late_release(struct intel_gt *gt)
 685 {
 686         /* We need to wait for inflight RCU frees to release their grip */
 687         rcu_barrier();
 688
 689         intel_uc_driver_late_release(&gt->uc);
 690         intel_gt_fini_requests(gt);
 691         intel_gt_fini_reset(gt);
 692         intel_gt_fini_timelines(gt);
 693         intel_engines_free(gt);
 694 }
 695
 696 void intel_gt_info_print(const struct intel_gt_info *info,
 697                          struct drm_printer *p)
 698 {
 699         drm_printf(p, "available engines: %x\n", info->engine_mask);
 700
 701         intel_sseu_dump(&info->sseu, p);
 702 }