drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include "intel_gt_debugfs.h"
   7
   8 #include "gem/i915_gem_lmem.h"
   9 #include "i915_drv.h"
  10 #include "intel_context.h"
  11 #include "intel_gt.h"
  12 #include "intel_gt_buffer_pool.h"
  13 #include "intel_gt_clock_utils.h"
  14 #include "intel_gt_pm.h"
  15 #include "intel_gt_requests.h"
  16 #include "intel_migrate.h"
  17 #include "intel_mocs.h"
  18 #include "intel_pm.h"
  19 #include "intel_rc6.h"
  20 #include "intel_renderstate.h"
  21 #include "intel_rps.h"
  22 #include "intel_uncore.h"
  23 #include "shmem_utils.h"
  24 #include "pxp/intel_pxp.h"
  25
  26 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
  27 {
  28         gt->i915 = i915;
  29         gt->uncore = &i915->uncore;
  30
  31         spin_lock_init(&gt->irq_lock);
  32
  33         INIT_LIST_HEAD(&gt->closed_vma);
  34         spin_lock_init(&gt->closed_lock);
  35
  36         init_llist_head(&gt->watchdog.list);
  37         INIT_WORK(&gt->watchdog.work, intel_gt_watchdog_work);
  38
  39         intel_gt_init_buffer_pool(gt);
  40         intel_gt_init_reset(gt);
  41         intel_gt_init_requests(gt);
  42         intel_gt_init_timelines(gt);
  43         intel_gt_pm_init_early(gt);
  44
  45         intel_uc_init_early(&gt->uc);
  46         intel_rps_init_early(&gt->rps);
  47 }
  48
  49 int intel_gt_probe_lmem(struct intel_gt *gt)
  50 {
  51         struct drm_i915_private *i915 = gt->i915;
  52         struct intel_memory_region *mem;
  53         int id;
  54         int err;
  55
  56         mem = intel_gt_setup_lmem(gt);
  57         if (mem == ERR_PTR(-ENODEV))
  58                 mem = intel_gt_setup_fake_lmem(gt);
  59         if (IS_ERR(mem)) {
  60                 err = PTR_ERR(mem);
  61                 if (err == -ENODEV)
  62                         return 0;
  63
  64                 drm_err(&i915->drm,
  65                         "Failed to setup region(%d) type=%d\n",
  66                         err, INTEL_MEMORY_LOCAL);
  67                 return err;
  68         }
  69
  70         id = INTEL_REGION_LMEM;
  71
  72         mem->id = id;
  73
  74         intel_memory_region_set_name(mem, "local%u", mem->instance);
  75
  76         GEM_BUG_ON(!HAS_REGION(i915, id));
  77         GEM_BUG_ON(i915->mm.regions[id]);
  78         i915->mm.regions[id] = mem;
  79
  80         return 0;
  81 }
  82
  83 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt)
  84 {
  85         gt->ggtt = ggtt;
  86 }
  87
  88 static const struct intel_mmio_range icl_l3bank_steering_table[] = {
  89         { 0x00B100, 0x00B3FF },
  90         {},
  91 };
  92
  93 static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
  94         { 0x004000, 0x004AFF },
  95         { 0x00C800, 0x00CFFF },
  96         { 0x00DD00, 0x00DDFF },
  97         { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
  98         {},
  99 };
 100
 101 static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
 102         { 0x00B000, 0x00B0FF },
 103         { 0x00D800, 0x00D8FF },
 104         {},
 105 };
 106
 107 static const struct intel_mmio_range dg2_lncf_steering_table[] = {
 108         { 0x00B000, 0x00B0FF },
 109         { 0x00D880, 0x00D8FF },
 110         {},
 111 };
 112
 113 static u16 slicemask(struct intel_gt *gt, int count)
 114 {
 115         u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
 116
 117         return intel_slicemask_from_dssmask(dss_mask, count);
 118 }
 119
 120 int intel_gt_init_mmio(struct intel_gt *gt)
 121 {
 122         struct drm_i915_private *i915 = gt->i915;
 123
 124         intel_gt_init_clock_frequency(gt);
 125
 126         intel_uc_init_mmio(&gt->uc);
 127         intel_sseu_info_init(gt);
 128
 129         /*
 130          * An mslice is unavailable only if both the meml3 for the slice is
 131          * disabled *and* all of the DSS in the slice (quadrant) are disabled.
 132          */
 133         if (HAS_MSLICES(i915))
 134                 gt->info.mslice_mask =
 135                         slicemask(gt, GEN_DSS_PER_MSLICE) |
 136                         (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 137                          GEN12_MEML3_EN_MASK);
 138
 139         if (IS_DG2(i915)) {
 140                 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 141                 gt->steering_table[LNCF] = dg2_lncf_steering_table;
 142         } else if (IS_XEHPSDV(i915)) {
 143                 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
 144                 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
 145         } else if (GRAPHICS_VER(i915) >= 11 &&
 146                    GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) {
 147                 gt->steering_table[L3BANK] = icl_l3bank_steering_table;
 148                 gt->info.l3bank_mask =
 149                         ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 150                         GEN10_L3BANK_MASK;
 151         } else if (HAS_MSLICES(i915)) {
 152                 MISSING_CASE(INTEL_INFO(i915)->platform);
 153         }
 154
 155         return intel_engines_init_mmio(gt);
 156 }
 157
 158 static void init_unused_ring(struct intel_gt *gt, u32 base)
 159 {
 160         struct intel_uncore *uncore = gt->uncore;
 161
 162         intel_uncore_write(uncore, RING_CTL(base), 0);
 163         intel_uncore_write(uncore, RING_HEAD(base), 0);
 164         intel_uncore_write(uncore, RING_TAIL(base), 0);
 165         intel_uncore_write(uncore, RING_START(base), 0);
 166 }
 167
 168 static void init_unused_rings(struct intel_gt *gt)
 169 {
 170         struct drm_i915_private *i915 = gt->i915;
 171
 172         if (IS_I830(i915)) {
 173                 init_unused_ring(gt, PRB1_BASE);
 174                 init_unused_ring(gt, SRB0_BASE);
 175                 init_unused_ring(gt, SRB1_BASE);
 176                 init_unused_ring(gt, SRB2_BASE);
 177                 init_unused_ring(gt, SRB3_BASE);
 178         } else if (GRAPHICS_VER(i915) == 2) {
 179                 init_unused_ring(gt, SRB0_BASE);
 180                 init_unused_ring(gt, SRB1_BASE);
 181         } else if (GRAPHICS_VER(i915) == 3) {
 182                 init_unused_ring(gt, PRB1_BASE);
 183                 init_unused_ring(gt, PRB2_BASE);
 184         }
 185 }
 186
 187 int intel_gt_init_hw(struct intel_gt *gt)
 188 {
 189         struct drm_i915_private *i915 = gt->i915;
 190         struct intel_uncore *uncore = gt->uncore;
 191         int ret;
 192
 193         gt->last_init_time = ktime_get();
 194
 195         /* Double layer security blanket, see i915_gem_init() */
 196         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 197
 198         if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
 199                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 200
 201         if (IS_HASWELL(i915))
 202                 intel_uncore_write(uncore,
 203                                    MI_PREDICATE_RESULT_2,
 204                                    IS_HSW_GT3(i915) ?
 205                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 206
 207         /* Apply the GT workarounds... */
 208         intel_gt_apply_workarounds(gt);
 209         /* ...and determine whether they are sticking. */
 210         intel_gt_verify_workarounds(gt, "init");
 211
 212         intel_gt_init_swizzling(gt);
 213
 214         /*
 215          * At least 830 can leave some of the unused rings
 216          * "active" (ie. head != tail) after resume which
 217          * will prevent c3 entry. Makes sure all unused rings
 218          * are totally idle.
 219          */
 220         init_unused_rings(gt);
 221
 222         ret = i915_ppgtt_init_hw(gt);
 223         if (ret) {
 224                 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
 225                 goto out;
 226         }
 227
 228         /* We can't enable contexts until all firmware is loaded */
 229         ret = intel_uc_init_hw(&gt->uc);
 230         if (ret) {
 231                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 232                 goto out;
 233         }
 234
 235         intel_mocs_init(gt);
 236
 237 out:
 238         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 239         return ret;
 240 }
 241
 242 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
 243 {
 244         intel_uncore_rmw(uncore, reg, 0, set);
 245 }
 246
 247 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
 248 {
 249         intel_uncore_rmw(uncore, reg, clr, 0);
 250 }
 251
 252 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 253 {
 254         intel_uncore_rmw(uncore, reg, 0, 0);
 255 }
 256
 257 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
 258 {
 259         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 260         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 261 }
 262
 263 void
 264 intel_gt_clear_error_registers(struct intel_gt *gt,
 265                                intel_engine_mask_t engine_mask)
 266 {
 267         struct drm_i915_private *i915 = gt->i915;
 268         struct intel_uncore *uncore = gt->uncore;
 269         u32 eir;
 270
 271         if (GRAPHICS_VER(i915) != 2)
 272                 clear_register(uncore, PGTBL_ER);
 273
 274         if (GRAPHICS_VER(i915) < 4)
 275                 clear_register(uncore, IPEIR(RENDER_RING_BASE));
 276         else
 277                 clear_register(uncore, IPEIR_I965);
 278
 279         clear_register(uncore, EIR);
 280         eir = intel_uncore_read(uncore, EIR);
 281         if (eir) {
 282                 /*
 283                  * some errors might have become stuck,
 284                  * mask them.
 285                  */
 286                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
 287                 rmw_set(uncore, EMR, eir);
 288                 intel_uncore_write(uncore, GEN2_IIR,
 289                                    I915_MASTER_ERROR_INTERRUPT);
 290         }
 291
 292         if (GRAPHICS_VER(i915) >= 12) {
 293                 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
 294                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 295         } else if (GRAPHICS_VER(i915) >= 8) {
 296                 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
 297                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 298         } else if (GRAPHICS_VER(i915) >= 6) {
 299                 struct intel_engine_cs *engine;
 300                 enum intel_engine_id id;
 301
 302                 for_each_engine_masked(engine, gt, engine_mask, id)
 303                         gen6_clear_engine_error_register(engine);
 304         }
 305 }
 306
 307 static void gen6_check_faults(struct intel_gt *gt)
 308 {
 309         struct intel_engine_cs *engine;
 310         enum intel_engine_id id;
 311         u32 fault;
 312
 313         for_each_engine(engine, gt, id) {
 314                 fault = GEN6_RING_FAULT_REG_READ(engine);
 315                 if (fault & RING_FAULT_VALID) {
 316                         drm_dbg(&engine->i915->drm, "Unexpected fault\n"
 317                                 "\tAddr: 0x%08lx\n"
 318                                 "\tAddress space: %s\n"
 319                                 "\tSource ID: %d\n"
 320                                 "\tType: %d\n",
 321                                 fault & PAGE_MASK,
 322                                 fault & RING_FAULT_GTTSEL_MASK ?
 323                                 "GGTT" : "PPGTT",
 324                                 RING_FAULT_SRCID(fault),
 325                                 RING_FAULT_FAULT_TYPE(fault));
 326                 }
 327         }
 328 }
 329
 330 static void gen8_check_faults(struct intel_gt *gt)
 331 {
 332         struct intel_uncore *uncore = gt->uncore;
 333         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 334         u32 fault;
 335
 336         if (GRAPHICS_VER(gt->i915) >= 12) {
 337                 fault_reg = GEN12_RING_FAULT_REG;
 338                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 339                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 340         } else {
 341                 fault_reg = GEN8_RING_FAULT_REG;
 342                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 343                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 344         }
 345
 346         fault = intel_uncore_read(uncore, fault_reg);
 347         if (fault & RING_FAULT_VALID) {
 348                 u32 fault_data0, fault_data1;
 349                 u64 fault_addr;
 350
 351                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 352                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 353
 354                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 355                              ((u64)fault_data0 << 12);
 356
 357                 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
 358                         "\tAddr: 0x%08x_%08x\n"
 359                         "\tAddress space: %s\n"
 360                         "\tEngine ID: %d\n"
 361                         "\tSource ID: %d\n"
 362                         "\tType: %d\n",
 363                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 364                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 365                         GEN8_RING_FAULT_ENGINE_ID(fault),
 366                         RING_FAULT_SRCID(fault),
 367                         RING_FAULT_FAULT_TYPE(fault));
 368         }
 369 }
 370
 371 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 372 {
 373         struct drm_i915_private *i915 = gt->i915;
 374
 375         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 376         if (GRAPHICS_VER(i915) >= 8)
 377                 gen8_check_faults(gt);
 378         else if (GRAPHICS_VER(i915) >= 6)
 379                 gen6_check_faults(gt);
 380         else
 381                 return;
 382
 383         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 384 }
 385
 386 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 387 {
 388         struct intel_uncore *uncore = gt->uncore;
 389         intel_wakeref_t wakeref;
 390
 391         /*
 392          * No actual flushing is required for the GTT write domain for reads
 393          * from the GTT domain. Writes to it "immediately" go to main memory
 394          * as far as we know, so there's no chipset flush. It also doesn't
 395          * land in the GPU render cache.
 396          *
 397          * However, we do have to enforce the order so that all writes through
 398          * the GTT land before any writes to the device, such as updates to
 399          * the GATT itself.
 400          *
 401          * We also have to wait a bit for the writes to land from the GTT.
 402          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 403          * timing. This issue has only been observed when switching quickly
 404          * between GTT writes and CPU reads from inside the kernel on recent hw,
 405          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 406          * system agents we cannot reproduce this behaviour, until Cannonlake
 407          * that was!).
 408          */
 409
 410         wmb();
 411
 412         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 413                 return;
 414
 415         intel_gt_chipset_flush(gt);
 416
 417         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 418                 unsigned long flags;
 419
 420                 spin_lock_irqsave(&uncore->lock, flags);
 421                 intel_uncore_posting_read_fw(uncore,
 422                                              RING_HEAD(RENDER_RING_BASE));
 423                 spin_unlock_irqrestore(&uncore->lock, flags);
 424         }
 425 }
 426
 427 void intel_gt_chipset_flush(struct intel_gt *gt)
 428 {
 429         wmb();
 430         if (GRAPHICS_VER(gt->i915) < 6)
 431                 intel_gtt_chipset_flush();
 432 }
 433
 434 void intel_gt_driver_register(struct intel_gt *gt)
 435 {
 436         intel_rps_driver_register(&gt->rps);
 437
 438         intel_gt_debugfs_register(gt);
 439 }
 440
 441 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 442 {
 443         struct drm_i915_private *i915 = gt->i915;
 444         struct drm_i915_gem_object *obj;
 445         struct i915_vma *vma;
 446         int ret;
 447
 448         obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
 449         if (IS_ERR(obj))
 450                 obj = i915_gem_object_create_stolen(i915, size);
 451         if (IS_ERR(obj))
 452                 obj = i915_gem_object_create_internal(i915, size);
 453         if (IS_ERR(obj)) {
 454                 drm_err(&i915->drm, "Failed to allocate scratch page\n");
 455                 return PTR_ERR(obj);
 456         }
 457
 458         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 459         if (IS_ERR(vma)) {
 460                 ret = PTR_ERR(vma);
 461                 goto err_unref;
 462         }
 463
 464         ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
 465         if (ret)
 466                 goto err_unref;
 467
 468         gt->scratch = i915_vma_make_unshrinkable(vma);
 469
 470         return 0;
 471
 472 err_unref:
 473         i915_gem_object_put(obj);
 474         return ret;
 475 }
 476
 477 static void intel_gt_fini_scratch(struct intel_gt *gt)
 478 {
 479         i915_vma_unpin_and_release(&gt->scratch, 0);
 480 }
 481
 482 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 483 {
 484         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 485                 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
 486         else
 487                 return i915_vm_get(&gt->ggtt->vm);
 488 }
 489
 490 static int __engines_record_defaults(struct intel_gt *gt)
 491 {
 492         struct i915_request *requests[I915_NUM_ENGINES] = {};
 493         struct intel_engine_cs *engine;
 494         enum intel_engine_id id;
 495         int err = 0;
 496
 497         /*
 498          * As we reset the gpu during very early sanitisation, the current
 499          * register state on the GPU should reflect its defaults values.
 500          * We load a context onto the hw (with restore-inhibit), then switch
 501          * over to a second context to save that default register state. We
 502          * can then prime every new context with that state so they all start
 503          * from the same default HW values.
 504          */
 505
 506         for_each_engine(engine, gt, id) {
 507                 struct intel_renderstate so;
 508                 struct intel_context *ce;
 509                 struct i915_request *rq;
 510
 511                 /* We must be able to switch to something! */
 512                 GEM_BUG_ON(!engine->kernel_context);
 513
 514                 ce = intel_context_create(engine);
 515                 if (IS_ERR(ce)) {
 516                         err = PTR_ERR(ce);
 517                         goto out;
 518                 }
 519
 520                 err = intel_renderstate_init(&so, ce);
 521                 if (err)
 522                         goto err;
 523
 524                 rq = i915_request_create(ce);
 525                 if (IS_ERR(rq)) {
 526                         err = PTR_ERR(rq);
 527                         goto err_fini;
 528                 }
 529
 530                 err = intel_engine_emit_ctx_wa(rq);
 531                 if (err)
 532                         goto err_rq;
 533
 534                 err = intel_renderstate_emit(&so, rq);
 535                 if (err)
 536                         goto err_rq;
 537
 538 err_rq:
 539                 requests[id] = i915_request_get(rq);
 540                 i915_request_add(rq);
 541 err_fini:
 542                 intel_renderstate_fini(&so, ce);
 543 err:
 544                 if (err) {
 545                         intel_context_put(ce);
 546                         goto out;
 547                 }
 548         }
 549
 550         /* Flush the default context image to memory, and enable powersaving. */
 551         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 552                 err = -EIO;
 553                 goto out;
 554         }
 555
 556         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 557                 struct i915_request *rq;
 558                 struct file *state;
 559
 560                 rq = requests[id];
 561                 if (!rq)
 562                         continue;
 563
 564                 if (rq->fence.error) {
 565                         err = -EIO;
 566                         goto out;
 567                 }
 568
 569                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 570                 if (!rq->context->state)
 571                         continue;
 572
 573                 /* Keep a copy of the state's backing pages; free the obj */
 574                 state = shmem_create_from_object(rq->context->state->obj);
 575                 if (IS_ERR(state)) {
 576                         err = PTR_ERR(state);
 577                         goto out;
 578                 }
 579                 rq->engine->default_state = state;
 580         }
 581
 582 out:
 583         /*
 584          * If we have to abandon now, we expect the engines to be idle
 585          * and ready to be torn-down. The quickest way we can accomplish
 586          * this is by declaring ourselves wedged.
 587          */
 588         if (err)
 589                 intel_gt_set_wedged(gt);
 590
 591         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 592                 struct intel_context *ce;
 593                 struct i915_request *rq;
 594
 595                 rq = requests[id];
 596                 if (!rq)
 597                         continue;
 598
 599                 ce = rq->context;
 600                 i915_request_put(rq);
 601                 intel_context_put(ce);
 602         }
 603         return err;
 604 }
 605
 606 static int __engines_verify_workarounds(struct intel_gt *gt)
 607 {
 608         struct intel_engine_cs *engine;
 609         enum intel_engine_id id;
 610         int err = 0;
 611
 612         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 613                 return 0;
 614
 615         for_each_engine(engine, gt, id) {
 616                 if (intel_engine_verify_workarounds(engine, "load"))
 617                         err = -EIO;
 618         }
 619
 620         /* Flush and restore the kernel context for safety */
 621         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
 622                 err = -EIO;
 623
 624         return err;
 625 }
 626
 627 static void __intel_gt_disable(struct intel_gt *gt)
 628 {
 629         intel_gt_set_wedged_on_fini(gt);
 630
 631         intel_gt_suspend_prepare(gt);
 632         intel_gt_suspend_late(gt);
 633
 634         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 635 }
 636
 637 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
 638 {
 639         long remaining_timeout;
 640
 641         /* If the device is asleep, we have no requests outstanding */
 642         if (!intel_gt_pm_is_awake(gt))
 643                 return 0;
 644
 645         while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
 646                                                            &remaining_timeout)) > 0) {
 647                 cond_resched();
 648                 if (signal_pending(current))
 649                         return -EINTR;
 650         }
 651
 652         return timeout ? timeout : intel_uc_wait_for_idle(&gt->uc,
 653                                                           remaining_timeout);
 654 }
 655
 656 int intel_gt_init(struct intel_gt *gt)
 657 {
 658         int err;
 659
 660         err = i915_inject_probe_error(gt->i915, -ENODEV);
 661         if (err)
 662                 return err;
 663
 664         intel_gt_init_workarounds(gt);
 665
 666         /*
 667          * This is just a security blanket to placate dragons.
 668          * On some systems, we very sporadically observe that the first TLBs
 669          * used by the CS may be stale, despite us poking the TLB reset. If
 670          * we hold the forcewake during initialisation these problems
 671          * just magically go away.
 672          */
 673         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 674
 675         err = intel_gt_init_scratch(gt,
 676                                     GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
 677         if (err)
 678                 goto out_fw;
 679
 680         intel_gt_pm_init(gt);
 681
 682         gt->vm = kernel_vm(gt);
 683         if (!gt->vm) {
 684                 err = -ENOMEM;
 685                 goto err_pm;
 686         }
 687
 688         intel_set_mocs_index(gt);
 689
 690         err = intel_engines_init(gt);
 691         if (err)
 692                 goto err_engines;
 693
 694         err = intel_uc_init(&gt->uc);
 695         if (err)
 696                 goto err_engines;
 697
 698         err = intel_gt_resume(gt);
 699         if (err)
 700                 goto err_uc_init;
 701
 702         err = __engines_record_defaults(gt);
 703         if (err)
 704                 goto err_gt;
 705
 706         err = __engines_verify_workarounds(gt);
 707         if (err)
 708                 goto err_gt;
 709
 710         intel_uc_init_late(&gt->uc);
 711
 712         err = i915_inject_probe_error(gt->i915, -EIO);
 713         if (err)
 714                 goto err_gt;
 715
 716         intel_migrate_init(&gt->migrate, gt);
 717
 718         intel_pxp_init(&gt->pxp);
 719
 720         goto out_fw;
 721 err_gt:
 722         __intel_gt_disable(gt);
 723         intel_uc_fini_hw(&gt->uc);
 724 err_uc_init:
 725         intel_uc_fini(&gt->uc);
 726 err_engines:
 727         intel_engines_release(gt);
 728         i915_vm_put(fetch_and_zero(&gt->vm));
 729 err_pm:
 730         intel_gt_pm_fini(gt);
 731         intel_gt_fini_scratch(gt);
 732 out_fw:
 733         if (err)
 734                 intel_gt_set_wedged_on_init(gt);
 735         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 736         return err;
 737 }
 738
 739 void intel_gt_driver_remove(struct intel_gt *gt)
 740 {
 741         __intel_gt_disable(gt);
 742
 743         intel_migrate_fini(&gt->migrate);
 744         intel_uc_driver_remove(&gt->uc);
 745
 746         intel_engines_release(gt);
 747
 748         intel_gt_flush_buffer_pool(gt);
 749 }
 750
 751 void intel_gt_driver_unregister(struct intel_gt *gt)
 752 {
 753         intel_wakeref_t wakeref;
 754
 755         intel_rps_driver_unregister(&gt->rps);
 756
 757         intel_pxp_fini(&gt->pxp);
 758
 759         /*
 760          * Upon unregistering the device to prevent any new users, cancel
 761          * all in-flight requests so that we can quickly unbind the active
 762          * resources.
 763          */
 764         intel_gt_set_wedged_on_fini(gt);
 765
 766         /* Scrub all HW state upon release */
 767         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 768                 __intel_gt_reset(gt, ALL_ENGINES);
 769 }
 770
 771 void intel_gt_driver_release(struct intel_gt *gt)
 772 {
 773         struct i915_address_space *vm;
 774
 775         vm = fetch_and_zero(&gt->vm);
 776         if (vm) /* FIXME being called twice on error paths :( */
 777                 i915_vm_put(vm);
 778
 779         intel_wa_list_free(&gt->wa_list);
 780         intel_gt_pm_fini(gt);
 781         intel_gt_fini_scratch(gt);
 782         intel_gt_fini_buffer_pool(gt);
 783 }
 784
 785 void intel_gt_driver_late_release(struct intel_gt *gt)
 786 {
 787         /* We need to wait for inflight RCU frees to release their grip */
 788         rcu_barrier();
 789
 790         intel_uc_driver_late_release(&gt->uc);
 791         intel_gt_fini_requests(gt);
 792         intel_gt_fini_reset(gt);
 793         intel_gt_fini_timelines(gt);
 794         intel_engines_free(gt);
 795 }
 796
 797 /**
 798  * intel_gt_reg_needs_read_steering - determine whether a register read
 799  *     requires explicit steering
 800  * @gt: GT structure
 801  * @reg: the register to check steering requirements for
 802  * @type: type of multicast steering to check
 803  *
 804  * Determines whether @reg needs explicit steering of a specific type for
 805  * reads.
 806  *
 807  * Returns false if @reg does not belong to a register range of the given
 808  * steering type, or if the default (subslice-based) steering IDs are suitable
 809  * for @type steering too.
 810  */
 811 static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
 812                                              i915_reg_t reg,
 813                                              enum intel_steering_type type)
 814 {
 815         const u32 offset = i915_mmio_reg_offset(reg);
 816         const struct intel_mmio_range *entry;
 817
 818         if (likely(!intel_gt_needs_read_steering(gt, type)))
 819                 return false;
 820
 821         for (entry = gt->steering_table[type]; entry->end; entry++) {
 822                 if (offset >= entry->start && offset <= entry->end)
 823                         return true;
 824         }
 825
 826         return false;
 827 }
 828
 829 /**
 830  * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering
 831  * @gt: GT structure
 832  * @type: multicast register type
 833  * @sliceid: Slice ID returned
 834  * @subsliceid: Subslice ID returned
 835  *
 836  * Determines sliceid and subsliceid values that will steer reads
 837  * of a specific multicast register class to a valid value.
 838  */
 839 static void intel_gt_get_valid_steering(struct intel_gt *gt,
 840                                         enum intel_steering_type type,
 841                                         u8 *sliceid, u8 *subsliceid)
 842 {
 843         switch (type) {
 844         case L3BANK:
 845                 GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
 846
 847                 *sliceid = 0;           /* unused */
 848                 *subsliceid = __ffs(gt->info.l3bank_mask);
 849                 break;
 850         case MSLICE:
 851                 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
 852
 853                 *sliceid = __ffs(gt->info.mslice_mask);
 854                 *subsliceid = 0;        /* unused */
 855                 break;
 856         case LNCF:
 857                 GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
 858
 859                 /*
 860                  * An LNCF is always present if its mslice is present, so we
 861                  * can safely just steer to LNCF 0 in all cases.
 862                  */
 863                 *sliceid = __ffs(gt->info.mslice_mask) << 1;
 864                 *subsliceid = 0;        /* unused */
 865                 break;
 866         default:
 867                 MISSING_CASE(type);
 868                 *sliceid = 0;
 869                 *subsliceid = 0;
 870         }
 871 }
 872
 873 /**
 874  * intel_gt_read_register_fw - reads a GT register with support for multicast
 875  * @gt: GT structure
 876  * @reg: register to read
 877  *
 878  * This function will read a GT register.  If the register is a multicast
 879  * register, the read will be steered to a valid instance (i.e., one that
 880  * isn't fused off or powered down by power gating).
 881  *
 882  * Returns the value from a valid instance of @reg.
 883  */
 884 u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg)
 885 {
 886         int type;
 887         u8 sliceid, subsliceid;
 888
 889         for (type = 0; type < NUM_STEERING_TYPES; type++) {
 890                 if (intel_gt_reg_needs_read_steering(gt, reg, type)) {
 891                         intel_gt_get_valid_steering(gt, type, &sliceid,
 892                                                     &subsliceid);
 893                         return intel_uncore_read_with_mcr_steering_fw(gt->uncore,
 894                                                                       reg,
 895                                                                       sliceid,
 896                                                                       subsliceid);
 897                 }
 898         }
 899
 900         return intel_uncore_read_fw(gt->uncore, reg);
 901 }
 902
 903 void intel_gt_info_print(const struct intel_gt_info *info,
 904                          struct drm_printer *p)
 905 {
 906         drm_printf(p, "available engines: %x\n", info->engine_mask);
 907
 908         intel_sseu_dump(&info->sseu, p);
 909 }