drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "i915_scatterlist.h"
  26 #include "i915_pvinfo.h"
  27 #include "i915_vgpu.h"
  28
  29 /**
  30  * DOC: fence register handling
  31  *
  32  * Important to avoid confusions: "fences" in the i915 driver are not execution
  33  * fences used to track command completion but hardware detiler objects which
  34  * wrap a given range of the global GTT. Each platform has only a fairly limited
  35  * set of these objects.
  36  *
  37  * Fences are used to detile GTT memory mappings. They're also connected to the
  38  * hardware frontbuffer render tracking and hence interact with frontbuffer
  39  * compression. Furthermore on older platforms fences are required for tiled
  40  * objects used by the display engine. They can also be used by the render
  41  * engine - they're required for blitter commands and are optional for render
  42  * commands. But on gen4+ both display (with the exception of fbc) and rendering
  43  * have their own tiling state bits and don't need fences.
  44  *
  45  * Also note that fences only support X and Y tiling and hence can't be used for
  46  * the fancier new tiling formats like W, Ys and Yf.
  47  *
  48  * Finally note that because fences are such a restricted resource they're
  49  * dynamically associated with objects. Furthermore fence state is committed to
  50  * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
  51  * explicitly call i915_gem_object_get_fence() to synchronize fencing status
  52  * for cpu access. Also note that some code wants an unfenced view, for those
  53  * cases the fence can be removed forcefully with i915_gem_object_put_fence().
  54  *
  55  * Internally these functions will synchronize with userspace access by removing
  56  * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
  57  */
  58
  59 #define pipelined 0
  60
  61 static struct drm_i915_private *fence_to_i915(struct i915_fence_reg *fence)
  62 {
  63         return fence->ggtt->vm.i915;
  64 }
  65
  66 static struct intel_uncore *fence_to_uncore(struct i915_fence_reg *fence)
  67 {
  68         return fence->ggtt->vm.gt->uncore;
  69 }
  70
  71 static void i965_write_fence_reg(struct i915_fence_reg *fence)
  72 {
  73         i915_reg_t fence_reg_lo, fence_reg_hi;
  74         int fence_pitch_shift;
  75         u64 val;
  76
  77         if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
  78                 fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
  79                 fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
  80                 fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
  81
  82         } else {
  83                 fence_reg_lo = FENCE_REG_965_LO(fence->id);
  84                 fence_reg_hi = FENCE_REG_965_HI(fence->id);
  85                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
  86         }
  87
  88         val = 0;
  89         if (fence->tiling) {
  90                 unsigned int stride = fence->stride;
  91
  92                 GEM_BUG_ON(!IS_ALIGNED(stride, 128));
  93
  94                 val = fence->start + fence->size - I965_FENCE_PAGE;
  95                 val <<= 32;
  96                 val |= fence->start;
  97                 val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
  98                 if (fence->tiling == I915_TILING_Y)
  99                         val |= BIT(I965_FENCE_TILING_Y_SHIFT);
 100                 val |= I965_FENCE_REG_VALID;
 101         }
 102
 103         if (!pipelined) {
 104                 struct intel_uncore *uncore = fence_to_uncore(fence);
 105
 106                 /*
 107                  * To w/a incoherency with non-atomic 64-bit register updates,
 108                  * we split the 64-bit update into two 32-bit writes. In order
 109                  * for a partial fence not to be evaluated between writes, we
 110                  * precede the update with write to turn off the fence register,
 111                  * and only enable the fence as the last step.
 112                  *
 113                  * For extra levels of paranoia, we make sure each step lands
 114                  * before applying the next step.
 115                  */
 116                 intel_uncore_write_fw(uncore, fence_reg_lo, 0);
 117                 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
 118
 119                 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val));
 120                 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val));
 121                 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
 122         }
 123 }
 124
 125 static void i915_write_fence_reg(struct i915_fence_reg *fence)
 126 {
 127         u32 val;
 128
 129         val = 0;
 130         if (fence->tiling) {
 131                 unsigned int stride = fence->stride;
 132                 unsigned int tiling = fence->tiling;
 133                 bool is_y_tiled = tiling == I915_TILING_Y;
 134
 135                 if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence_to_i915(fence)))
 136                         stride /= 128;
 137                 else
 138                         stride /= 512;
 139                 GEM_BUG_ON(!is_power_of_2(stride));
 140
 141                 val = fence->start;
 142                 if (is_y_tiled)
 143                         val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 144                 val |= I915_FENCE_SIZE_BITS(fence->size);
 145                 val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
 146
 147                 val |= I830_FENCE_REG_VALID;
 148         }
 149
 150         if (!pipelined) {
 151                 struct intel_uncore *uncore = fence_to_uncore(fence);
 152                 i915_reg_t reg = FENCE_REG(fence->id);
 153
 154                 intel_uncore_write_fw(uncore, reg, val);
 155                 intel_uncore_posting_read_fw(uncore, reg);
 156         }
 157 }
 158
 159 static void i830_write_fence_reg(struct i915_fence_reg *fence)
 160 {
 161         u32 val;
 162
 163         val = 0;
 164         if (fence->tiling) {
 165                 unsigned int stride = fence->stride;
 166
 167                 val = fence->start;
 168                 if (fence->tiling == I915_TILING_Y)
 169                         val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 170                 val |= I830_FENCE_SIZE_BITS(fence->size);
 171                 val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
 172                 val |= I830_FENCE_REG_VALID;
 173         }
 174
 175         if (!pipelined) {
 176                 struct intel_uncore *uncore = fence_to_uncore(fence);
 177                 i915_reg_t reg = FENCE_REG(fence->id);
 178
 179                 intel_uncore_write_fw(uncore, reg, val);
 180                 intel_uncore_posting_read_fw(uncore, reg);
 181         }
 182 }
 183
 184 static void fence_write(struct i915_fence_reg *fence)
 185 {
 186         struct drm_i915_private *i915 = fence_to_i915(fence);
 187
 188         /*
 189          * Previous access through the fence register is marshalled by
 190          * the mb() inside the fault handlers (i915_gem_release_mmaps)
 191          * and explicitly managed for internal users.
 192          */
 193
 194         if (IS_GEN(i915, 2))
 195                 i830_write_fence_reg(fence);
 196         else if (IS_GEN(i915, 3))
 197                 i915_write_fence_reg(fence);
 198         else
 199                 i965_write_fence_reg(fence);
 200
 201         /*
 202          * Access through the fenced region afterwards is
 203          * ordered by the posting reads whilst writing the registers.
 204          */
 205 }
 206
 207 static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
 208 {
 209         return INTEL_GEN(fence_to_i915(fence)) < 4;
 210 }
 211
 212 static int fence_update(struct i915_fence_reg *fence,
 213                         struct i915_vma *vma)
 214 {
 215         struct i915_ggtt *ggtt = fence->ggtt;
 216         struct intel_uncore *uncore = fence_to_uncore(fence);
 217         intel_wakeref_t wakeref;
 218         struct i915_vma *old;
 219         int ret;
 220
 221         fence->tiling = 0;
 222         if (vma) {
 223                 GEM_BUG_ON(!i915_gem_object_get_stride(vma->obj) ||
 224                            !i915_gem_object_get_tiling(vma->obj));
 225
 226                 if (!i915_vma_is_map_and_fenceable(vma))
 227                         return -EINVAL;
 228
 229                 if (gpu_uses_fence_registers(fence)) {
 230                         /* implicit 'unfenced' GPU blits */
 231                         ret = i915_vma_sync(vma);
 232                         if (ret)
 233                                 return ret;
 234                 }
 235
 236                 fence->start = vma->node.start;
 237                 fence->size = vma->fence_size;
 238                 fence->stride = i915_gem_object_get_stride(vma->obj);
 239                 fence->tiling = i915_gem_object_get_tiling(vma->obj);
 240         }
 241         WRITE_ONCE(fence->dirty, false);
 242
 243         old = xchg(&fence->vma, NULL);
 244         if (old) {
 245                 /* XXX Ideally we would move the waiting to outside the mutex */
 246                 ret = i915_active_wait(&fence->active);
 247                 if (ret) {
 248                         fence->vma = old;
 249                         return ret;
 250                 }
 251
 252                 i915_vma_flush_writes(old);
 253
 254                 /*
 255                  * Ensure that all userspace CPU access is completed before
 256                  * stealing the fence.
 257                  */
 258                 if (old != vma) {
 259                         GEM_BUG_ON(old->fence != fence);
 260                         i915_vma_revoke_mmap(old);
 261                         old->fence = NULL;
 262                 }
 263
 264                 list_move(&fence->link, &ggtt->fence_list);
 265         }
 266
 267         /*
 268          * We only need to update the register itself if the device is awake.
 269          * If the device is currently powered down, we will defer the write
 270          * to the runtime resume, see intel_ggtt_restore_fences().
 271          *
 272          * This only works for removing the fence register, on acquisition
 273          * the caller must hold the rpm wakeref. The fence register must
 274          * be cleared before we can use any other fences to ensure that
 275          * the new fences do not overlap the elided clears, confusing HW.
 276          */
 277         wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm);
 278         if (!wakeref) {
 279                 GEM_BUG_ON(vma);
 280                 return 0;
 281         }
 282
 283         WRITE_ONCE(fence->vma, vma);
 284         fence_write(fence);
 285
 286         if (vma) {
 287                 vma->fence = fence;
 288                 list_move_tail(&fence->link, &ggtt->fence_list);
 289         }
 290
 291         intel_runtime_pm_put(uncore->rpm, wakeref);
 292         return 0;
 293 }
 294
 295 /**
 296  * i915_vma_revoke_fence - force-remove fence for a VMA
 297  * @vma: vma to map linearly (not through a fence reg)
 298  *
 299  * This function force-removes any fence from the given object, which is useful
 300  * if the kernel wants to do untiled GTT access.
 301  */
 302 void i915_vma_revoke_fence(struct i915_vma *vma)
 303 {
 304         struct i915_fence_reg *fence = vma->fence;
 305         intel_wakeref_t wakeref;
 306
 307         lockdep_assert_held(&vma->vm->mutex);
 308         if (!fence)
 309                 return;
 310
 311         GEM_BUG_ON(fence->vma != vma);
 312         GEM_BUG_ON(!i915_active_is_idle(&fence->active));
 313         GEM_BUG_ON(atomic_read(&fence->pin_count));
 314
 315         fence->tiling = 0;
 316         WRITE_ONCE(fence->vma, NULL);
 317         vma->fence = NULL;
 318
 319         /*
 320          * Skip the write to HW if and only if the device is currently
 321          * suspended.
 322          *
 323          * If the driver does not currently hold a wakeref (if_in_use == 0),
 324          * the device may currently be runtime suspended, or it may be woken
 325          * up before the suspend takes place. If the device is not suspended
 326          * (powered down) and we skip clearing the fence register, the HW is
 327          * left in an undefined state where we may end up with multiple
 328          * registers overlapping.
 329          */
 330         with_intel_runtime_pm_if_active(fence_to_uncore(fence)->rpm, wakeref)
 331                 fence_write(fence);
 332 }
 333
 334 static bool fence_is_active(const struct i915_fence_reg *fence)
 335 {
 336         return fence->vma && i915_vma_is_active(fence->vma);
 337 }
 338
 339 static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt)
 340 {
 341         struct i915_fence_reg *active = NULL;
 342         struct i915_fence_reg *fence, *fn;
 343
 344         list_for_each_entry_safe(fence, fn, &ggtt->fence_list, link) {
 345                 GEM_BUG_ON(fence->vma && fence->vma->fence != fence);
 346
 347                 if (fence == active) /* now seen this fence twice */
 348                         active = ERR_PTR(-EAGAIN);
 349
 350                 /* Prefer idle fences so we do not have to wait on the GPU */
 351                 if (active != ERR_PTR(-EAGAIN) && fence_is_active(fence)) {
 352                         if (!active)
 353                                 active = fence;
 354
 355                         list_move_tail(&fence->link, &ggtt->fence_list);
 356                         continue;
 357                 }
 358
 359                 if (atomic_read(&fence->pin_count))
 360                         continue;
 361
 362                 return fence;
 363         }
 364
 365         /* Wait for completion of pending flips which consume fences */
 366         if (intel_has_pending_fb_unpin(ggtt->vm.i915))
 367                 return ERR_PTR(-EAGAIN);
 368
 369         return ERR_PTR(-EDEADLK);
 370 }
 371
 372 int __i915_vma_pin_fence(struct i915_vma *vma)
 373 {
 374         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm);
 375         struct i915_fence_reg *fence;
 376         struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
 377         int err;
 378
 379         lockdep_assert_held(&vma->vm->mutex);
 380
 381         /* Just update our place in the LRU if our fence is getting reused. */
 382         if (vma->fence) {
 383                 fence = vma->fence;
 384                 GEM_BUG_ON(fence->vma != vma);
 385                 atomic_inc(&fence->pin_count);
 386                 if (!fence->dirty) {
 387                         list_move_tail(&fence->link, &ggtt->fence_list);
 388                         return 0;
 389                 }
 390         } else if (set) {
 391                 fence = fence_find(ggtt);
 392                 if (IS_ERR(fence))
 393                         return PTR_ERR(fence);
 394
 395                 GEM_BUG_ON(atomic_read(&fence->pin_count));
 396                 atomic_inc(&fence->pin_count);
 397         } else {
 398                 return 0;
 399         }
 400
 401         err = fence_update(fence, set);
 402         if (err)
 403                 goto out_unpin;
 404
 405         GEM_BUG_ON(fence->vma != set);
 406         GEM_BUG_ON(vma->fence != (set ? fence : NULL));
 407
 408         if (set)
 409                 return 0;
 410
 411 out_unpin:
 412         atomic_dec(&fence->pin_count);
 413         return err;
 414 }
 415
 416 /**
 417  * i915_vma_pin_fence - set up fencing for a vma
 418  * @vma: vma to map through a fence reg
 419  *
 420  * When mapping objects through the GTT, userspace wants to be able to write
 421  * to them without having to worry about swizzling if the object is tiled.
 422  * This function walks the fence regs looking for a free one for @obj,
 423  * stealing one if it can't find any.
 424  *
 425  * It then sets up the reg based on the object's properties: address, pitch
 426  * and tiling format.
 427  *
 428  * For an untiled surface, this removes any existing fence.
 429  *
 430  * Returns:
 431  *
 432  * 0 on success, negative error code on failure.
 433  */
 434 int i915_vma_pin_fence(struct i915_vma *vma)
 435 {
 436         int err;
 437
 438         if (!vma->fence && !i915_gem_object_is_tiled(vma->obj))
 439                 return 0;
 440
 441         /*
 442          * Note that we revoke fences on runtime suspend. Therefore the user
 443          * must keep the device awake whilst using the fence.
 444          */
 445         assert_rpm_wakelock_held(vma->vm->gt->uncore->rpm);
 446         GEM_BUG_ON(!i915_vma_is_pinned(vma));
 447         GEM_BUG_ON(!i915_vma_is_ggtt(vma));
 448
 449         err = mutex_lock_interruptible(&vma->vm->mutex);
 450         if (err)
 451                 return err;
 452
 453         err = __i915_vma_pin_fence(vma);
 454         mutex_unlock(&vma->vm->mutex);
 455
 456         return err;
 457 }
 458
 459 /**
 460  * i915_reserve_fence - Reserve a fence for vGPU
 461  * @ggtt: Global GTT
 462  *
 463  * This function walks the fence regs looking for a free one and remove
 464  * it from the fence_list. It is used to reserve fence for vGPU to use.
 465  */
 466 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt)
 467 {
 468         struct i915_fence_reg *fence;
 469         int count;
 470         int ret;
 471
 472         lockdep_assert_held(&ggtt->vm.mutex);
 473
 474         /* Keep at least one fence available for the display engine. */
 475         count = 0;
 476         list_for_each_entry(fence, &ggtt->fence_list, link)
 477                 count += !atomic_read(&fence->pin_count);
 478         if (count <= 1)
 479                 return ERR_PTR(-ENOSPC);
 480
 481         fence = fence_find(ggtt);
 482         if (IS_ERR(fence))
 483                 return fence;
 484
 485         if (fence->vma) {
 486                 /* Force-remove fence from VMA */
 487                 ret = fence_update(fence, NULL);
 488                 if (ret)
 489                         return ERR_PTR(ret);
 490         }
 491
 492         list_del(&fence->link);
 493
 494         return fence;
 495 }
 496
 497 /**
 498  * i915_unreserve_fence - Reclaim a reserved fence
 499  * @fence: the fence reg
 500  *
 501  * This function add a reserved fence register from vGPU to the fence_list.
 502  */
 503 void i915_unreserve_fence(struct i915_fence_reg *fence)
 504 {
 505         struct i915_ggtt *ggtt = fence->ggtt;
 506
 507         lockdep_assert_held(&ggtt->vm.mutex);
 508
 509         list_add(&fence->link, &ggtt->fence_list);
 510 }
 511
 512 /**
 513  * intel_ggtt_restore_fences - restore fence state
 514  * @ggtt: Global GTT
 515  *
 516  * Restore the hw fence state to match the software tracking again, to be called
 517  * after a gpu reset and on resume. Note that on runtime suspend we only cancel
 518  * the fences, to be reacquired by the user later.
 519  */
 520 void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)
 521 {
 522         int i;
 523
 524         for (i = 0; i < ggtt->num_fences; i++)
 525                 fence_write(&ggtt->fence_regs[i]);
 526 }
 527
 528 /**
 529  * DOC: tiling swizzling details
 530  *
 531  * The idea behind tiling is to increase cache hit rates by rearranging
 532  * pixel data so that a group of pixel accesses are in the same cacheline.
 533  * Performance improvement from doing this on the back/depth buffer are on
 534  * the order of 30%.
 535  *
 536  * Intel architectures make this somewhat more complicated, though, by
 537  * adjustments made to addressing of data when the memory is in interleaved
 538  * mode (matched pairs of DIMMS) to improve memory bandwidth.
 539  * For interleaved memory, the CPU sends every sequential 64 bytes
 540  * to an alternate memory channel so it can get the bandwidth from both.
 541  *
 542  * The GPU also rearranges its accesses for increased bandwidth to interleaved
 543  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 544  * it does it a little differently, since one walks addresses not just in the
 545  * X direction but also Y.  So, along with alternating channels when bit
 546  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 547  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 548  * are common to both the 915 and 965-class hardware.
 549  *
 550  * The CPU also sometimes XORs in higher bits as well, to improve
 551  * bandwidth doing strided access like we do so frequently in graphics.  This
 552  * is called "Channel XOR Randomization" in the MCH documentation.  The result
 553  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 554  * decode.
 555  *
 556  * All of this bit 6 XORing has an effect on our memory management,
 557  * as we need to make sure that the 3d driver can correctly address object
 558  * contents.
 559  *
 560  * If we don't have interleaved memory, all tiling is safe and no swizzling is
 561  * required.
 562  *
 563  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 564  * 17 is not just a page offset, so as we page an object out and back in,
 565  * individual pages in it will have different bit 17 addresses, resulting in
 566  * each 64 bytes being swapped with its neighbor!
 567  *
 568  * Otherwise, if interleaved, we have to tell the 3d driver what the address
 569  * swizzling it needs to do is, since it's writing with the CPU to the pages
 570  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 571  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 572  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 573  * to match what the GPU expects.
 574  */
 575
 576 /**
 577  * detect_bit_6_swizzle - detect bit 6 swizzling pattern
 578  * @ggtt: Global GGTT
 579  *
 580  * Detects bit 6 swizzling of address lookup between IGD access and CPU
 581  * access through main memory.
 582  */
 583 static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 584 {
 585         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 586         struct drm_i915_private *i915 = ggtt->vm.i915;
 587         u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 588         u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 589
 590         if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
 591                 /*
 592                  * On BDW+, swizzling is not used. We leave the CPU memory
 593                  * controller in charge of optimizing memory accesses without
 594                  * the extra address manipulation GPU side.
 595                  *
 596                  * VLV and CHV don't have GPU swizzling.
 597                  */
 598                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 599                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 600         } else if (INTEL_GEN(i915) >= 6) {
 601                 if (i915->preserve_bios_swizzle) {
 602                         if (intel_uncore_read(uncore, DISP_ARB_CTL) &
 603                             DISP_TILE_SURFACE_SWIZZLING) {
 604                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 605                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 606                         } else {
 607                                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 608                                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 609                         }
 610                 } else {
 611                         u32 dimm_c0, dimm_c1;
 612                         dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0);
 613                         dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1);
 614                         dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 615                         dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 616                         /*
 617                          * Enable swizzling when the channels are populated
 618                          * with identically sized dimms. We don't need to check
 619                          * the 3rd channel because no cpu with gpu attached
 620                          * ships in that configuration. Also, swizzling only
 621                          * makes sense for 2 channels anyway.
 622                          */
 623                         if (dimm_c0 == dimm_c1) {
 624                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 625                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 626                         } else {
 627                                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 628                                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 629                         }
 630                 }
 631         } else if (IS_GEN(i915, 5)) {
 632                 /*
 633                  * On Ironlake whatever DRAM config, GPU always do
 634                  * same swizzling setup.
 635                  */
 636                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 637                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 638         } else if (IS_GEN(i915, 2)) {
 639                 /*
 640                  * As far as we know, the 865 doesn't have these bit 6
 641                  * swizzling issues.
 642                  */
 643                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 644                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 645         } else if (IS_G45(i915) || IS_I965G(i915) || IS_G33(i915)) {
 646                 /*
 647                  * The 965, G33, and newer, have a very flexible memory
 648                  * configuration.  It will enable dual-channel mode
 649                  * (interleaving) on as much memory as it can, and the GPU
 650                  * will additionally sometimes enable different bit 6
 651                  * swizzling for tiled objects from the CPU.
 652                  *
 653                  * Here's what I found on the G965:
 654                  *    slot fill         memory size  swizzling
 655                  * 0A   0B   1A   1B    1-ch   2-ch
 656                  * 512  0    0    0     512    0     O
 657                  * 512  0    512  0     16     1008  X
 658                  * 512  0    0    512   16     1008  X
 659                  * 0    512  0    512   16     1008  X
 660                  * 1024 1024 1024 0     2048   1024  O
 661                  *
 662                  * We could probably detect this based on either the DRB
 663                  * matching, which was the case for the swizzling required in
 664                  * the table above, or from the 1-ch value being less than
 665                  * the minimum size of a rank.
 666                  *
 667                  * Reports indicate that the swizzling actually
 668                  * varies depending upon page placement inside the
 669                  * channels, i.e. we see swizzled pages where the
 670                  * banks of memory are paired and unswizzled on the
 671                  * uneven portion, so leave that as unknown.
 672                  */
 673                 if (intel_uncore_read(uncore, C0DRB3) ==
 674                     intel_uncore_read(uncore, C1DRB3)) {
 675                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 676                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 677                 }
 678         } else {
 679                 u32 dcc = intel_uncore_read(uncore, DCC);
 680
 681                 /*
 682                  * On 9xx chipsets, channel interleave by the CPU is
 683                  * determined by DCC.  For single-channel, neither the CPU
 684                  * nor the GPU do swizzling.  For dual channel interleaved,
 685                  * the GPU's interleave is bit 9 and 10 for X tiled, and bit
 686                  * 9 for Y tiled.  The CPU's interleave is independent, and
 687                  * can be based on either bit 11 (haven't seen this yet) or
 688                  * bit 17 (common).
 689                  */
 690                 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
 691                 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
 692                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
 693                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 694                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 695                         break;
 696                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
 697                         if (dcc & DCC_CHANNEL_XOR_DISABLE) {
 698                                 /*
 699                                  * This is the base swizzling by the GPU for
 700                                  * tiled buffers.
 701                                  */
 702                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 703                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 704                         } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
 705                                 /* Bit 11 swizzling by the CPU in addition. */
 706                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
 707                                 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
 708                         } else {
 709                                 /* Bit 17 swizzling by the CPU in addition. */
 710                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 711                                 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 712                         }
 713                         break;
 714                 }
 715
 716                 /* check for L-shaped memory aka modified enhanced addressing */
 717                 if (IS_GEN(i915, 4) &&
 718                     !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
 719                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 720                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 721                 }
 722
 723                 if (dcc == 0xffffffff) {
 724                         drm_err(&i915->drm, "Couldn't read from MCHBAR.  "
 725                                   "Disabling tiling.\n");
 726                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 727                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 728                 }
 729         }
 730
 731         if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
 732             swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
 733                 /*
 734                  * Userspace likes to explode if it sees unknown swizzling,
 735                  * so lie. We will finish the lie when reporting through
 736                  * the get-tiling-ioctl by reporting the physical swizzle
 737                  * mode as unknown instead.
 738                  *
 739                  * As we don't strictly know what the swizzling is, it may be
 740                  * bit17 dependent, and so we need to also prevent the pages
 741                  * from being moved.
 742                  */
 743                 i915->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
 744                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 745                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 746         }
 747
 748         i915->ggtt.bit_6_swizzle_x = swizzle_x;
 749         i915->ggtt.bit_6_swizzle_y = swizzle_y;
 750 }
 751
 752 /*
 753  * Swap every 64 bytes of this page around, to account for it having a new
 754  * bit 17 of its physical address and therefore being interpreted differently
 755  * by the GPU.
 756  */
 757 static void swizzle_page(struct page *page)
 758 {
 759         char temp[64];
 760         char *vaddr;
 761         int i;
 762
 763         vaddr = kmap(page);
 764
 765         for (i = 0; i < PAGE_SIZE; i += 128) {
 766                 memcpy(temp, &vaddr[i], 64);
 767                 memcpy(&vaddr[i], &vaddr[i + 64], 64);
 768                 memcpy(&vaddr[i + 64], temp, 64);
 769         }
 770
 771         kunmap(page);
 772 }
 773
 774 /**
 775  * i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling
 776  * @obj: i915 GEM buffer object
 777  * @pages: the scattergather list of physical pages
 778  *
 779  * This function fixes up the swizzling in case any page frame number for this
 780  * object has changed in bit 17 since that state has been saved with
 781  * i915_gem_object_save_bit_17_swizzle().
 782  *
 783  * This is called when pinning backing storage again, since the kernel is free
 784  * to move unpinned backing storage around (either by directly moving pages or
 785  * by swapping them out and back in again).
 786  */
 787 void
 788 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
 789                                   struct sg_table *pages)
 790 {
 791         struct sgt_iter sgt_iter;
 792         struct page *page;
 793         int i;
 794
 795         if (obj->bit_17 == NULL)
 796                 return;
 797
 798         i = 0;
 799         for_each_sgt_page(page, sgt_iter, pages) {
 800                 char new_bit_17 = page_to_phys(page) >> 17;
 801                 if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {
 802                         swizzle_page(page);
 803                         set_page_dirty(page);
 804                 }
 805                 i++;
 806         }
 807 }
 808
 809 /**
 810  * i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling
 811  * @obj: i915 GEM buffer object
 812  * @pages: the scattergather list of physical pages
 813  *
 814  * This function saves the bit 17 of each page frame number so that swizzling
 815  * can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must
 816  * be called before the backing storage can be unpinned.
 817  */
 818 void
 819 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 820                                     struct sg_table *pages)
 821 {
 822         const unsigned int page_count = obj->base.size >> PAGE_SHIFT;
 823         struct sgt_iter sgt_iter;
 824         struct page *page;
 825         int i;
 826
 827         if (obj->bit_17 == NULL) {
 828                 obj->bit_17 = bitmap_zalloc(page_count, GFP_KERNEL);
 829                 if (obj->bit_17 == NULL) {
 830                         DRM_ERROR("Failed to allocate memory for bit 17 "
 831                                   "record\n");
 832                         return;
 833                 }
 834         }
 835
 836         i = 0;
 837
 838         for_each_sgt_page(page, sgt_iter, pages) {
 839                 if (page_to_phys(page) & (1 << 17))
 840                         __set_bit(i, obj->bit_17);
 841                 else
 842                         __clear_bit(i, obj->bit_17);
 843                 i++;
 844         }
 845 }
 846
 847 void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
 848 {
 849         struct drm_i915_private *i915 = ggtt->vm.i915;
 850         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 851         int num_fences;
 852         int i;
 853
 854         INIT_LIST_HEAD(&ggtt->fence_list);
 855         INIT_LIST_HEAD(&ggtt->userfault_list);
 856         intel_wakeref_auto_init(&ggtt->userfault_wakeref, uncore->rpm);
 857
 858         detect_bit_6_swizzle(ggtt);
 859
 860         if (!i915_ggtt_has_aperture(ggtt))
 861                 num_fences = 0;
 862         else if (INTEL_GEN(i915) >= 7 &&
 863                  !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
 864                 num_fences = 32;
 865         else if (INTEL_GEN(i915) >= 4 ||
 866                  IS_I945G(i915) || IS_I945GM(i915) ||
 867                  IS_G33(i915) || IS_PINEVIEW(i915))
 868                 num_fences = 16;
 869         else
 870                 num_fences = 8;
 871
 872         if (intel_vgpu_active(i915))
 873                 num_fences = intel_uncore_read(uncore,
 874                                                vgtif_reg(avail_rs.fence_num));
 875         ggtt->fence_regs = kcalloc(num_fences,
 876                                    sizeof(*ggtt->fence_regs),
 877                                    GFP_KERNEL);
 878         if (!ggtt->fence_regs)
 879                 num_fences = 0;
 880
 881         /* Initialize fence registers to zero */
 882         for (i = 0; i < num_fences; i++) {
 883                 struct i915_fence_reg *fence = &ggtt->fence_regs[i];
 884
 885                 i915_active_init(&fence->active, NULL, NULL);
 886                 fence->ggtt = ggtt;
 887                 fence->id = i;
 888                 list_add_tail(&fence->link, &ggtt->fence_list);
 889         }
 890         ggtt->num_fences = num_fences;
 891
 892         intel_ggtt_restore_fences(ggtt);
 893 }
 894
 895 void intel_ggtt_fini_fences(struct i915_ggtt *ggtt)
 896 {
 897         int i;
 898
 899         for (i = 0; i < ggtt->num_fences; i++) {
 900                 struct i915_fence_reg *fence = &ggtt->fence_regs[i];
 901
 902                 i915_active_fini(&fence->active);
 903         }
 904
 905         kfree(ggtt->fence_regs);
 906 }
 907
 908 void intel_gt_init_swizzling(struct intel_gt *gt)
 909 {
 910         struct drm_i915_private *i915 = gt->i915;
 911         struct intel_uncore *uncore = gt->uncore;
 912
 913         if (INTEL_GEN(i915) < 5 ||
 914             i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 915                 return;
 916
 917         intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
 918
 919         if (IS_GEN(i915, 5))
 920                 return;
 921
 922         intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
 923
 924         if (IS_GEN(i915, 6))
 925                 intel_uncore_write(uncore,
 926                                    ARB_MODE,
 927                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
 928         else if (IS_GEN(i915, 7))
 929                 intel_uncore_write(uncore,
 930                                    ARB_MODE,
 931                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
 932         else if (IS_GEN(i915, 8))
 933                 intel_uncore_write(uncore,
 934                                    GAMTARBMODE,
 935                                    _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
 936         else
 937                 MISSING_CASE(INTEL_GEN(i915));
 938 }