drivers/gpu/drm/i915/gt/intel_ggtt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <linux/agp_backend.h>
   7 #include <linux/stop_machine.h>
   8
   9 #include <asm/set_memory.h>
  10 #include <asm/smp.h>
  11
  12 #include <drm/i915_drm.h>
  13 #include <drm/intel-gtt.h>
  14
  15 #include "gem/i915_gem_lmem.h"
  16
  17 #include "intel_gt.h"
  18 #include "intel_gt_regs.h"
  19 #include "i915_drv.h"
  20 #include "i915_scatterlist.h"
  21 #include "i915_vgpu.h"
  22
  23 #include "intel_gtt.h"
  24 #include "gen8_ppgtt.h"
  25
  26 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
  27                                    unsigned long color,
  28                                    u64 *start,
  29                                    u64 *end)
  30 {
  31         if (i915_node_color_differs(node, color))
  32                 *start += I915_GTT_PAGE_SIZE;
  33
  34         /*
  35          * Also leave a space between the unallocated reserved node after the
  36          * GTT and any objects within the GTT, i.e. we use the color adjustment
  37          * to insert a guard page to prevent prefetches crossing over the
  38          * GTT boundary.
  39          */
  40         node = list_next_entry(node, node_list);
  41         if (node->color != color)
  42                 *end -= I915_GTT_PAGE_SIZE;
  43 }
  44
  45 static int ggtt_init_hw(struct i915_ggtt *ggtt)
  46 {
  47         struct drm_i915_private *i915 = ggtt->vm.i915;
  48
  49         i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
  50
  51         ggtt->vm.is_ggtt = true;
  52
  53         /* Only VLV supports read-only GGTT mappings */
  54         ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
  55
  56         if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
  57                 ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
  58
  59         if (ggtt->mappable_end) {
  60                 if (!io_mapping_init_wc(&ggtt->iomap,
  61                                         ggtt->gmadr.start,
  62                                         ggtt->mappable_end)) {
  63                         ggtt->vm.cleanup(&ggtt->vm);
  64                         return -EIO;
  65                 }
  66
  67                 ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
  68                                               ggtt->mappable_end);
  69         }
  70
  71         intel_ggtt_init_fences(ggtt);
  72
  73         return 0;
  74 }
  75
  76 /**
  77  * i915_ggtt_init_hw - Initialize GGTT hardware
  78  * @i915: i915 device
  79  */
  80 int i915_ggtt_init_hw(struct drm_i915_private *i915)
  81 {
  82         int ret;
  83
  84         /*
  85          * Note that we use page colouring to enforce a guard page at the
  86          * end of the address space. This is required as the CS may prefetch
  87          * beyond the end of the batch buffer, across the page boundary,
  88          * and beyond the end of the GTT if we do not provide a guard.
  89          */
  90         ret = ggtt_init_hw(to_gt(i915)->ggtt);
  91         if (ret)
  92                 return ret;
  93
  94         return 0;
  95 }
  96
  97 /*
  98  * Certain Gen5 chipsets require idling the GPU before
  99  * unmapping anything from the GTT when VT-d is enabled.
 100  */
 101 static bool needs_idle_maps(struct drm_i915_private *i915)
 102 {
 103         /*
 104          * Query intel_iommu to see if we need the workaround. Presumably that
 105          * was loaded first.
 106          */
 107         if (!intel_vtd_active(i915))
 108                 return false;
 109
 110         if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
 111                 return true;
 112
 113         if (GRAPHICS_VER(i915) == 12)
 114                 return true; /* XXX DMAR fault reason 7 */
 115
 116         return false;
 117 }
 118
 119 /**
 120  * i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM
 121  * @vm: The VM to suspend the mappings for
 122  *
 123  * Suspend the memory mappings for all objects mapped to HW via the GGTT or a
 124  * DPT page table.
 125  */
 126 void i915_ggtt_suspend_vm(struct i915_address_space *vm)
 127 {
 128         struct i915_vma *vma, *vn;
 129         int open;
 130
 131         drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
 132
 133 retry:
 134         i915_gem_drain_freed_objects(vm->i915);
 135
 136         mutex_lock(&vm->mutex);
 137
 138         /* Skip rewriting PTE on VMA unbind. */
 139         open = atomic_xchg(&vm->open, 0);
 140
 141         list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
 142                 struct drm_i915_gem_object *obj = vma->obj;
 143
 144                 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
 145
 146                 if (i915_vma_is_pinned(vma) || !i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
 147                         continue;
 148
 149                 /* unlikely to race when GPU is idle, so no worry about slowpath.. */
 150                 if (WARN_ON(!i915_gem_object_trylock(obj, NULL))) {
 151                         /*
 152                          * No dead objects should appear here, GPU should be
 153                          * completely idle, and userspace suspended
 154                          */
 155                         i915_gem_object_get(obj);
 156
 157                         atomic_set(&vm->open, open);
 158                         mutex_unlock(&vm->mutex);
 159
 160                         i915_gem_object_lock(obj, NULL);
 161                         open = i915_vma_unbind(vma);
 162                         i915_gem_object_unlock(obj);
 163
 164                         GEM_WARN_ON(open);
 165
 166                         i915_gem_object_put(obj);
 167                         goto retry;
 168                 }
 169
 170                 if (!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) {
 171                         i915_vma_wait_for_bind(vma);
 172
 173                         __i915_vma_evict(vma, false);
 174                         drm_mm_remove_node(&vma->node);
 175                 }
 176
 177                 i915_gem_object_unlock(obj);
 178         }
 179
 180         vm->clear_range(vm, 0, vm->total);
 181
 182         atomic_set(&vm->open, open);
 183
 184         mutex_unlock(&vm->mutex);
 185 }
 186
 187 void i915_ggtt_suspend(struct i915_ggtt *ggtt)
 188 {
 189         i915_ggtt_suspend_vm(&ggtt->vm);
 190         ggtt->invalidate(ggtt);
 191
 192         intel_gt_check_and_clear_faults(ggtt->vm.gt);
 193 }
 194
 195 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 196 {
 197         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 198
 199         spin_lock_irq(&uncore->lock);
 200         intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 201         intel_uncore_read_fw(uncore, GFX_FLSH_CNTL_GEN6);
 202         spin_unlock_irq(&uncore->lock);
 203 }
 204
 205 static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 206 {
 207         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 208
 209         /*
 210          * Note that as an uncached mmio write, this will flush the
 211          * WCB of the writes into the GGTT before it triggers the invalidate.
 212          */
 213         intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 214 }
 215
 216 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 217 {
 218         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 219         struct drm_i915_private *i915 = ggtt->vm.i915;
 220
 221         gen8_ggtt_invalidate(ggtt);
 222
 223         if (GRAPHICS_VER(i915) >= 12)
 224                 intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
 225                                       GEN12_GUC_TLB_INV_CR_INVALIDATE);
 226         else
 227                 intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 228 }
 229
 230 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
 231 {
 232         intel_gtt_chipset_flush();
 233 }
 234
 235 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
 236                          enum i915_cache_level level,
 237                          u32 flags)
 238 {
 239         gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
 240
 241         if (flags & PTE_LM)
 242                 pte |= GEN12_GGTT_PTE_LM;
 243
 244         return pte;
 245 }
 246
 247 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
 248 {
 249         writeq(pte, addr);
 250 }
 251
 252 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
 253                                   dma_addr_t addr,
 254                                   u64 offset,
 255                                   enum i915_cache_level level,
 256                                   u32 flags)
 257 {
 258         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 259         gen8_pte_t __iomem *pte =
 260                 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
 261
 262         gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
 263
 264         ggtt->invalidate(ggtt);
 265 }
 266
 267 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 268                                      struct i915_vma_resource *vma_res,
 269                                      enum i915_cache_level level,
 270                                      u32 flags)
 271 {
 272         const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
 273         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 274         gen8_pte_t __iomem *gte;
 275         gen8_pte_t __iomem *end;
 276         struct sgt_iter iter;
 277         dma_addr_t addr;
 278
 279         /*
 280          * Note that we ignore PTE_READ_ONLY here. The caller must be careful
 281          * not to allow the user to override access to a read only page.
 282          */
 283
 284         gte = (gen8_pte_t __iomem *)ggtt->gsm;
 285         gte += vma_res->start / I915_GTT_PAGE_SIZE;
 286         end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
 287
 288         for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
 289                 gen8_set_pte(gte++, pte_encode | addr);
 290         GEM_BUG_ON(gte > end);
 291
 292         /* Fill the allocated but "unused" space beyond the end of the buffer */
 293         while (gte < end)
 294                 gen8_set_pte(gte++, vm->scratch[0]->encode);
 295
 296         /*
 297          * We want to flush the TLBs only after we're certain all the PTE
 298          * updates have finished.
 299          */
 300         ggtt->invalidate(ggtt);
 301 }
 302
 303 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
 304                                   dma_addr_t addr,
 305                                   u64 offset,
 306                                   enum i915_cache_level level,
 307                                   u32 flags)
 308 {
 309         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 310         gen6_pte_t __iomem *pte =
 311                 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
 312
 313         iowrite32(vm->pte_encode(addr, level, flags), pte);
 314
 315         ggtt->invalidate(ggtt);
 316 }
 317
 318 /*
 319  * Binds an object into the global gtt with the specified cache level.
 320  * The object will be accessible to the GPU via commands whose operands
 321  * reference offsets within the global GTT as well as accessible by the GPU
 322  * through the GMADR mapped BAR (i915->mm.gtt->gtt).
 323  */
 324 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 325                                      struct i915_vma_resource *vma_res,
 326                                      enum i915_cache_level level,
 327                                      u32 flags)
 328 {
 329         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 330         gen6_pte_t __iomem *gte;
 331         gen6_pte_t __iomem *end;
 332         struct sgt_iter iter;
 333         dma_addr_t addr;
 334
 335         gte = (gen6_pte_t __iomem *)ggtt->gsm;
 336         gte += vma_res->start / I915_GTT_PAGE_SIZE;
 337         end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
 338
 339         for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
 340                 iowrite32(vm->pte_encode(addr, level, flags), gte++);
 341         GEM_BUG_ON(gte > end);
 342
 343         /* Fill the allocated but "unused" space beyond the end of the buffer */
 344         while (gte < end)
 345                 iowrite32(vm->scratch[0]->encode, gte++);
 346
 347         /*
 348          * We want to flush the TLBs only after we're certain all the PTE
 349          * updates have finished.
 350          */
 351         ggtt->invalidate(ggtt);
 352 }
 353
 354 static void nop_clear_range(struct i915_address_space *vm,
 355                             u64 start, u64 length)
 356 {
 357 }
 358
 359 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
 360                                   u64 start, u64 length)
 361 {
 362         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 363         unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
 364         unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
 365         const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
 366         gen8_pte_t __iomem *gtt_base =
 367                 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
 368         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
 369         int i;
 370
 371         if (WARN(num_entries > max_entries,
 372                  "First entry = %d; Num entries = %d (max=%d)\n",
 373                  first_entry, num_entries, max_entries))
 374                 num_entries = max_entries;
 375
 376         for (i = 0; i < num_entries; i++)
 377                 gen8_set_pte(&gtt_base[i], scratch_pte);
 378 }
 379
 380 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
 381 {
 382         /*
 383          * Make sure the internal GAM fifo has been cleared of all GTT
 384          * writes before exiting stop_machine(). This guarantees that
 385          * any aperture accesses waiting to start in another process
 386          * cannot back up behind the GTT writes causing a hang.
 387          * The register can be any arbitrary GAM register.
 388          */
 389         intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
 390 }
 391
 392 struct insert_page {
 393         struct i915_address_space *vm;
 394         dma_addr_t addr;
 395         u64 offset;
 396         enum i915_cache_level level;
 397 };
 398
 399 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
 400 {
 401         struct insert_page *arg = _arg;
 402
 403         gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
 404         bxt_vtd_ggtt_wa(arg->vm);
 405
 406         return 0;
 407 }
 408
 409 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
 410                                           dma_addr_t addr,
 411                                           u64 offset,
 412                                           enum i915_cache_level level,
 413                                           u32 unused)
 414 {
 415         struct insert_page arg = { vm, addr, offset, level };
 416
 417         stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
 418 }
 419
 420 struct insert_entries {
 421         struct i915_address_space *vm;
 422         struct i915_vma_resource *vma_res;
 423         enum i915_cache_level level;
 424         u32 flags;
 425 };
 426
 427 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
 428 {
 429         struct insert_entries *arg = _arg;
 430
 431         gen8_ggtt_insert_entries(arg->vm, arg->vma_res, arg->level, arg->flags);
 432         bxt_vtd_ggtt_wa(arg->vm);
 433
 434         return 0;
 435 }
 436
 437 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
 438                                              struct i915_vma_resource *vma_res,
 439                                              enum i915_cache_level level,
 440                                              u32 flags)
 441 {
 442         struct insert_entries arg = { vm, vma_res, level, flags };
 443
 444         stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
 445 }
 446
 447 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 448                                   u64 start, u64 length)
 449 {
 450         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 451         unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
 452         unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
 453         gen6_pte_t scratch_pte, __iomem *gtt_base =
 454                 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
 455         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
 456         int i;
 457
 458         if (WARN(num_entries > max_entries,
 459                  "First entry = %d; Num entries = %d (max=%d)\n",
 460                  first_entry, num_entries, max_entries))
 461                 num_entries = max_entries;
 462
 463         scratch_pte = vm->scratch[0]->encode;
 464         for (i = 0; i < num_entries; i++)
 465                 iowrite32(scratch_pte, &gtt_base[i]);
 466 }
 467
 468 static void i915_ggtt_insert_page(struct i915_address_space *vm,
 469                                   dma_addr_t addr,
 470                                   u64 offset,
 471                                   enum i915_cache_level cache_level,
 472                                   u32 unused)
 473 {
 474         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 475                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 476
 477         intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
 478 }
 479
 480 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
 481                                      struct i915_vma_resource *vma_res,
 482                                      enum i915_cache_level cache_level,
 483                                      u32 unused)
 484 {
 485         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 486                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 487
 488         intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
 489                                     flags);
 490 }
 491
 492 static void i915_ggtt_clear_range(struct i915_address_space *vm,
 493                                   u64 start, u64 length)
 494 {
 495         intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
 496 }
 497
 498 static void ggtt_bind_vma(struct i915_address_space *vm,
 499                           struct i915_vm_pt_stash *stash,
 500                           struct i915_vma_resource *vma_res,
 501                           enum i915_cache_level cache_level,
 502                           u32 flags)
 503 {
 504         u32 pte_flags;
 505
 506         if (vma_res->bound_flags & (~flags & I915_VMA_BIND_MASK))
 507                 return;
 508
 509         vma_res->bound_flags |= flags;
 510
 511         /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
 512         pte_flags = 0;
 513         if (vma_res->bi.readonly)
 514                 pte_flags |= PTE_READ_ONLY;
 515         if (vma_res->bi.lmem)
 516                 pte_flags |= PTE_LM;
 517
 518         vm->insert_entries(vm, vma_res, cache_level, pte_flags);
 519         vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
 520 }
 521
 522 static void ggtt_unbind_vma(struct i915_address_space *vm,
 523                             struct i915_vma_resource *vma_res)
 524 {
 525         vm->clear_range(vm, vma_res->start, vma_res->vma_size);
 526 }
 527
 528 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
 529 {
 530         u64 size;
 531         int ret;
 532
 533         if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
 534                 return 0;
 535
 536         GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
 537         size = ggtt->vm.total - GUC_GGTT_TOP;
 538
 539         ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &ggtt->uc_fw, size,
 540                                    GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
 541                                    PIN_NOEVICT);
 542         if (ret)
 543                 drm_dbg(&ggtt->vm.i915->drm,
 544                         "Failed to reserve top of GGTT for GuC\n");
 545
 546         return ret;
 547 }
 548
 549 static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
 550 {
 551         if (drm_mm_node_allocated(&ggtt->uc_fw))
 552                 drm_mm_remove_node(&ggtt->uc_fw);
 553 }
 554
 555 static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
 556 {
 557         ggtt_release_guc_top(ggtt);
 558         if (drm_mm_node_allocated(&ggtt->error_capture))
 559                 drm_mm_remove_node(&ggtt->error_capture);
 560         mutex_destroy(&ggtt->error_mutex);
 561 }
 562
 563 static int init_ggtt(struct i915_ggtt *ggtt)
 564 {
 565         /*
 566          * Let GEM Manage all of the aperture.
 567          *
 568          * However, leave one page at the end still bound to the scratch page.
 569          * There are a number of places where the hardware apparently prefetches
 570          * past the end of the object, and we've seen multiple hangs with the
 571          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 572          * aperture.  One page should be enough to keep any prefetching inside
 573          * of the aperture.
 574          */
 575         unsigned long hole_start, hole_end;
 576         struct drm_mm_node *entry;
 577         int ret;
 578
 579         /*
 580          * GuC requires all resources that we're sharing with it to be placed in
 581          * non-WOPCM memory. If GuC is not present or not in use we still need a
 582          * small bias as ring wraparound at offset 0 sometimes hangs. No idea
 583          * why.
 584          */
 585         ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
 586                                intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
 587
 588         ret = intel_vgt_balloon(ggtt);
 589         if (ret)
 590                 return ret;
 591
 592         mutex_init(&ggtt->error_mutex);
 593         if (ggtt->mappable_end) {
 594                 /*
 595                  * Reserve a mappable slot for our lockless error capture.
 596                  *
 597                  * We strongly prefer taking address 0x0 in order to protect
 598                  * other critical buffers against accidental overwrites,
 599                  * as writing to address 0 is a very common mistake.
 600                  *
 601                  * Since 0 may already be in use by the system (e.g. the BIOS
 602                  * framebuffer), we let the reservation fail quietly and hope
 603                  * 0 remains reserved always.
 604                  *
 605                  * If we fail to reserve 0, and then fail to find any space
 606                  * for an error-capture, remain silent. We can afford not
 607                  * to reserve an error_capture node as we have fallback
 608                  * paths, and we trust that 0 will remain reserved. However,
 609                  * the only likely reason for failure to insert is a driver
 610                  * bug, which we expect to cause other failures...
 611                  */
 612                 ggtt->error_capture.size = I915_GTT_PAGE_SIZE;
 613                 ggtt->error_capture.color = I915_COLOR_UNEVICTABLE;
 614                 if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture))
 615                         drm_mm_insert_node_in_range(&ggtt->vm.mm,
 616                                                     &ggtt->error_capture,
 617                                                     ggtt->error_capture.size, 0,
 618                                                     ggtt->error_capture.color,
 619                                                     0, ggtt->mappable_end,
 620                                                     DRM_MM_INSERT_LOW);
 621         }
 622         if (drm_mm_node_allocated(&ggtt->error_capture))
 623                 drm_dbg(&ggtt->vm.i915->drm,
 624                         "Reserved GGTT:[%llx, %llx] for use by error capture\n",
 625                         ggtt->error_capture.start,
 626                         ggtt->error_capture.start + ggtt->error_capture.size);
 627
 628         /*
 629          * The upper portion of the GuC address space has a sizeable hole
 630          * (several MB) that is inaccessible by GuC. Reserve this range within
 631          * GGTT as it can comfortably hold GuC/HuC firmware images.
 632          */
 633         ret = ggtt_reserve_guc_top(ggtt);
 634         if (ret)
 635                 goto err;
 636
 637         /* Clear any non-preallocated blocks */
 638         drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
 639                 drm_dbg(&ggtt->vm.i915->drm,
 640                         "clearing unused GTT space: [%lx, %lx]\n",
 641                         hole_start, hole_end);
 642                 ggtt->vm.clear_range(&ggtt->vm, hole_start,
 643                                      hole_end - hole_start);
 644         }
 645
 646         /* And finally clear the reserved guard page */
 647         ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 648
 649         return 0;
 650
 651 err:
 652         cleanup_init_ggtt(ggtt);
 653         return ret;
 654 }
 655
 656 static void aliasing_gtt_bind_vma(struct i915_address_space *vm,
 657                                   struct i915_vm_pt_stash *stash,
 658                                   struct i915_vma_resource *vma_res,
 659                                   enum i915_cache_level cache_level,
 660                                   u32 flags)
 661 {
 662         u32 pte_flags;
 663
 664         /* Currently applicable only to VLV */
 665         pte_flags = 0;
 666         if (vma_res->bi.readonly)
 667                 pte_flags |= PTE_READ_ONLY;
 668
 669         if (flags & I915_VMA_LOCAL_BIND)
 670                 ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm,
 671                                stash, vma_res, cache_level, flags);
 672
 673         if (flags & I915_VMA_GLOBAL_BIND)
 674                 vm->insert_entries(vm, vma_res, cache_level, pte_flags);
 675
 676         vma_res->bound_flags |= flags;
 677 }
 678
 679 static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
 680                                     struct i915_vma_resource *vma_res)
 681 {
 682         if (vma_res->bound_flags & I915_VMA_GLOBAL_BIND)
 683                 vm->clear_range(vm, vma_res->start, vma_res->vma_size);
 684
 685         if (vma_res->bound_flags & I915_VMA_LOCAL_BIND)
 686                 ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma_res);
 687 }
 688
 689 static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
 690 {
 691         struct i915_vm_pt_stash stash = {};
 692         struct i915_ppgtt *ppgtt;
 693         int err;
 694
 695         ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
 696         if (IS_ERR(ppgtt))
 697                 return PTR_ERR(ppgtt);
 698
 699         if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
 700                 err = -ENODEV;
 701                 goto err_ppgtt;
 702         }
 703
 704         err = i915_vm_alloc_pt_stash(&ppgtt->vm, &stash, ggtt->vm.total);
 705         if (err)
 706                 goto err_ppgtt;
 707
 708         i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
 709         err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
 710         i915_gem_object_unlock(ppgtt->vm.scratch[0]);
 711         if (err)
 712                 goto err_stash;
 713
 714         /*
 715          * Note we only pre-allocate as far as the end of the global
 716          * GTT. On 48b / 4-level page-tables, the difference is very,
 717          * very significant! We have to preallocate as GVT/vgpu does
 718          * not like the page directory disappearing.
 719          */
 720         ppgtt->vm.allocate_va_range(&ppgtt->vm, &stash, 0, ggtt->vm.total);
 721
 722         ggtt->alias = ppgtt;
 723         ggtt->vm.bind_async_flags |= ppgtt->vm.bind_async_flags;
 724
 725         GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
 726         ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
 727
 728         GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
 729         ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
 730
 731         i915_vm_free_pt_stash(&ppgtt->vm, &stash);
 732         return 0;
 733
 734 err_stash:
 735         i915_vm_free_pt_stash(&ppgtt->vm, &stash);
 736 err_ppgtt:
 737         i915_vm_put(&ppgtt->vm);
 738         return err;
 739 }
 740
 741 static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)
 742 {
 743         struct i915_ppgtt *ppgtt;
 744
 745         ppgtt = fetch_and_zero(&ggtt->alias);
 746         if (!ppgtt)
 747                 return;
 748
 749         i915_vm_put(&ppgtt->vm);
 750
 751         ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
 752         ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
 753 }
 754
 755 int i915_init_ggtt(struct drm_i915_private *i915)
 756 {
 757         int ret;
 758
 759         ret = init_ggtt(to_gt(i915)->ggtt);
 760         if (ret)
 761                 return ret;
 762
 763         if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
 764                 ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
 765                 if (ret)
 766                         cleanup_init_ggtt(to_gt(i915)->ggtt);
 767         }
 768
 769         return 0;
 770 }
 771
 772 static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
 773 {
 774         struct i915_vma *vma, *vn;
 775
 776         atomic_set(&ggtt->vm.open, 0);
 777
 778         flush_workqueue(ggtt->vm.i915->wq);
 779         i915_gem_drain_freed_objects(ggtt->vm.i915);
 780
 781         mutex_lock(&ggtt->vm.mutex);
 782
 783         list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link) {
 784                 struct drm_i915_gem_object *obj = vma->obj;
 785                 bool trylock;
 786
 787                 trylock = i915_gem_object_trylock(obj, NULL);
 788                 WARN_ON(!trylock);
 789
 790                 WARN_ON(__i915_vma_unbind(vma));
 791                 if (trylock)
 792                         i915_gem_object_unlock(obj);
 793         }
 794
 795         if (drm_mm_node_allocated(&ggtt->error_capture))
 796                 drm_mm_remove_node(&ggtt->error_capture);
 797         mutex_destroy(&ggtt->error_mutex);
 798
 799         ggtt_release_guc_top(ggtt);
 800         intel_vgt_deballoon(ggtt);
 801
 802         ggtt->vm.cleanup(&ggtt->vm);
 803
 804         mutex_unlock(&ggtt->vm.mutex);
 805         i915_address_space_fini(&ggtt->vm);
 806
 807         arch_phys_wc_del(ggtt->mtrr);
 808
 809         if (ggtt->iomap.size)
 810                 io_mapping_fini(&ggtt->iomap);
 811 }
 812
 813 /**
 814  * i915_ggtt_driver_release - Clean up GGTT hardware initialization
 815  * @i915: i915 device
 816  */
 817 void i915_ggtt_driver_release(struct drm_i915_private *i915)
 818 {
 819         struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
 820
 821         fini_aliasing_ppgtt(ggtt);
 822
 823         intel_ggtt_fini_fences(ggtt);
 824         ggtt_cleanup_hw(ggtt);
 825 }
 826
 827 /**
 828  * i915_ggtt_driver_late_release - Cleanup of GGTT that needs to be done after
 829  * all free objects have been drained.
 830  * @i915: i915 device
 831  */
 832 void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
 833 {
 834         struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
 835
 836         GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
 837         dma_resv_fini(&ggtt->vm._resv);
 838 }
 839
 840 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 841 {
 842         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 843         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 844         return snb_gmch_ctl << 20;
 845 }
 846
 847 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
 848 {
 849         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
 850         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
 851         if (bdw_gmch_ctl)
 852                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
 853
 854 #ifdef CONFIG_X86_32
 855         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
 856         if (bdw_gmch_ctl > 4)
 857                 bdw_gmch_ctl = 4;
 858 #endif
 859
 860         return bdw_gmch_ctl << 20;
 861 }
 862
 863 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
 864 {
 865         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
 866         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
 867
 868         if (gmch_ctrl)
 869                 return 1 << (20 + gmch_ctrl);
 870
 871         return 0;
 872 }
 873
 874 static unsigned int gen6_gttmmadr_size(struct drm_i915_private *i915)
 875 {
 876         /*
 877          * GEN6: GTTMMADR size is 4MB and GTTADR starts at 2MB offset
 878          * GEN8: GTTMMADR size is 16MB and GTTADR starts at 8MB offset
 879          */
 880         GEM_BUG_ON(GRAPHICS_VER(i915) < 6);
 881         return (GRAPHICS_VER(i915) < 8) ? SZ_4M : SZ_16M;
 882 }
 883
 884 static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
 885 {
 886         return gen6_gttmmadr_size(i915) / 2;
 887 }
 888
 889 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 890 {
 891         struct drm_i915_private *i915 = ggtt->vm.i915;
 892         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 893         phys_addr_t phys_addr;
 894         u32 pte_flags;
 895         int ret;
 896
 897         GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915));
 898         phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915);
 899
 900         /*
 901          * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
 902          * will be dropped. For WC mappings in general we have 64 byte burst
 903          * writes when the WC buffer is flushed, so we can't use it, but have to
 904          * resort to an uncached mapping. The WC issue is easily caught by the
 905          * readback check when writing GTT PTE entries.
 906          */
 907         if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
 908                 ggtt->gsm = ioremap(phys_addr, size);
 909         else
 910                 ggtt->gsm = ioremap_wc(phys_addr, size);
 911         if (!ggtt->gsm) {
 912                 drm_err(&i915->drm, "Failed to map the ggtt page table\n");
 913                 return -ENOMEM;
 914         }
 915
 916         kref_init(&ggtt->vm.resv_ref);
 917         ret = setup_scratch_page(&ggtt->vm);
 918         if (ret) {
 919                 drm_err(&i915->drm, "Scratch setup failed\n");
 920                 /* iounmap will also get called at remove, but meh */
 921                 iounmap(ggtt->gsm);
 922                 return ret;
 923         }
 924
 925         pte_flags = 0;
 926         if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))
 927                 pte_flags |= PTE_LM;
 928
 929         ggtt->vm.scratch[0]->encode =
 930                 ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
 931                                     I915_CACHE_NONE, pte_flags);
 932
 933         return 0;
 934 }
 935
 936 static void gen6_gmch_remove(struct i915_address_space *vm)
 937 {
 938         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 939
 940         iounmap(ggtt->gsm);
 941         free_scratch(vm);
 942 }
 943
 944 static struct resource pci_resource(struct pci_dev *pdev, int bar)
 945 {
 946         return (struct resource)DEFINE_RES_MEM(pci_resource_start(pdev, bar),
 947                                                pci_resource_len(pdev, bar));
 948 }
 949
 950 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 951 {
 952         struct drm_i915_private *i915 = ggtt->vm.i915;
 953         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 954         unsigned int size;
 955         u16 snb_gmch_ctl;
 956
 957         /* TODO: We're not aware of mappable constraints on gen8 yet */
 958         if (!HAS_LMEM(i915)) {
 959                 ggtt->gmadr = pci_resource(pdev, 2);
 960                 ggtt->mappable_end = resource_size(&ggtt->gmadr);
 961         }
 962
 963         pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 964         if (IS_CHERRYVIEW(i915))
 965                 size = chv_get_total_gtt_size(snb_gmch_ctl);
 966         else
 967                 size = gen8_get_total_gtt_size(snb_gmch_ctl);
 968
 969         ggtt->vm.alloc_pt_dma = alloc_pt_dma;
 970         ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
 971         ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
 972
 973         ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
 974         ggtt->vm.cleanup = gen6_gmch_remove;
 975         ggtt->vm.insert_page = gen8_ggtt_insert_page;
 976         ggtt->vm.clear_range = nop_clear_range;
 977         if (intel_scanout_needs_vtd_wa(i915))
 978                 ggtt->vm.clear_range = gen8_ggtt_clear_range;
 979
 980         ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
 981
 982         /*
 983          * Serialize GTT updates with aperture access on BXT if VT-d is on,
 984          * and always on CHV.
 985          */
 986         if (intel_vm_no_concurrent_access_wa(i915)) {
 987                 ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
 988                 ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
 989                 ggtt->vm.bind_async_flags =
 990                         I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
 991         }
 992
 993         ggtt->invalidate = gen8_ggtt_invalidate;
 994
 995         ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
 996         ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
 997
 998         ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
 999
1000         setup_private_pat(ggtt->vm.gt->uncore);
1001
1002         return ggtt_probe_common(ggtt, size);
1003 }
1004
1005 static u64 snb_pte_encode(dma_addr_t addr,
1006                           enum i915_cache_level level,
1007                           u32 flags)
1008 {
1009         gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1010
1011         switch (level) {
1012         case I915_CACHE_L3_LLC:
1013         case I915_CACHE_LLC:
1014                 pte |= GEN6_PTE_CACHE_LLC;
1015                 break;
1016         case I915_CACHE_NONE:
1017                 pte |= GEN6_PTE_UNCACHED;
1018                 break;
1019         default:
1020                 MISSING_CASE(level);
1021         }
1022
1023         return pte;
1024 }
1025
1026 static u64 ivb_pte_encode(dma_addr_t addr,
1027                           enum i915_cache_level level,
1028                           u32 flags)
1029 {
1030         gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1031
1032         switch (level) {
1033         case I915_CACHE_L3_LLC:
1034                 pte |= GEN7_PTE_CACHE_L3_LLC;
1035                 break;
1036         case I915_CACHE_LLC:
1037                 pte |= GEN6_PTE_CACHE_LLC;
1038                 break;
1039         case I915_CACHE_NONE:
1040                 pte |= GEN6_PTE_UNCACHED;
1041                 break;
1042         default:
1043                 MISSING_CASE(level);
1044         }
1045
1046         return pte;
1047 }
1048
1049 static u64 byt_pte_encode(dma_addr_t addr,
1050                           enum i915_cache_level level,
1051                           u32 flags)
1052 {
1053         gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1054
1055         if (!(flags & PTE_READ_ONLY))
1056                 pte |= BYT_PTE_WRITEABLE;
1057
1058         if (level != I915_CACHE_NONE)
1059                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
1060
1061         return pte;
1062 }
1063
1064 static u64 hsw_pte_encode(dma_addr_t addr,
1065                           enum i915_cache_level level,
1066                           u32 flags)
1067 {
1068         gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1069
1070         if (level != I915_CACHE_NONE)
1071                 pte |= HSW_WB_LLC_AGE3;
1072
1073         return pte;
1074 }
1075
1076 static u64 iris_pte_encode(dma_addr_t addr,
1077                            enum i915_cache_level level,
1078                            u32 flags)
1079 {
1080         gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1081
1082         switch (level) {
1083         case I915_CACHE_NONE:
1084                 break;
1085         case I915_CACHE_WT:
1086                 pte |= HSW_WT_ELLC_LLC_AGE3;
1087                 break;
1088         default:
1089                 pte |= HSW_WB_ELLC_LLC_AGE3;
1090                 break;
1091         }
1092
1093         return pte;
1094 }
1095
1096 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
1097 {
1098         struct drm_i915_private *i915 = ggtt->vm.i915;
1099         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1100         unsigned int size;
1101         u16 snb_gmch_ctl;
1102
1103         ggtt->gmadr = pci_resource(pdev, 2);
1104         ggtt->mappable_end = resource_size(&ggtt->gmadr);
1105
1106         /*
1107          * 64/512MB is the current min/max we actually know of, but this is
1108          * just a coarse sanity check.
1109          */
1110         if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
1111                 drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
1112                         &ggtt->mappable_end);
1113                 return -ENXIO;
1114         }
1115
1116         pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1117
1118         size = gen6_get_total_gtt_size(snb_gmch_ctl);
1119         ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
1120
1121         ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1122         ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
1123
1124         ggtt->vm.clear_range = nop_clear_range;
1125         if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
1126                 ggtt->vm.clear_range = gen6_ggtt_clear_range;
1127         ggtt->vm.insert_page = gen6_ggtt_insert_page;
1128         ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
1129         ggtt->vm.cleanup = gen6_gmch_remove;
1130
1131         ggtt->invalidate = gen6_ggtt_invalidate;
1132
1133         if (HAS_EDRAM(i915))
1134                 ggtt->vm.pte_encode = iris_pte_encode;
1135         else if (IS_HASWELL(i915))
1136                 ggtt->vm.pte_encode = hsw_pte_encode;
1137         else if (IS_VALLEYVIEW(i915))
1138                 ggtt->vm.pte_encode = byt_pte_encode;
1139         else if (GRAPHICS_VER(i915) >= 7)
1140                 ggtt->vm.pte_encode = ivb_pte_encode;
1141         else
1142                 ggtt->vm.pte_encode = snb_pte_encode;
1143
1144         ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
1145         ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
1146
1147         return ggtt_probe_common(ggtt, size);
1148 }
1149
1150 static void i915_gmch_remove(struct i915_address_space *vm)
1151 {
1152         intel_gmch_remove();
1153 }
1154
1155 static int i915_gmch_probe(struct i915_ggtt *ggtt)
1156 {
1157         struct drm_i915_private *i915 = ggtt->vm.i915;
1158         phys_addr_t gmadr_base;
1159         int ret;
1160
1161         ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
1162         if (!ret) {
1163                 drm_err(&i915->drm, "failed to set up gmch\n");
1164                 return -EIO;
1165         }
1166
1167         intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
1168
1169         ggtt->gmadr =
1170                 (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
1171
1172         ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1173         ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
1174
1175         if (needs_idle_maps(i915)) {
1176                 drm_notice(&i915->drm,
1177                            "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
1178                 ggtt->do_idle_maps = true;
1179         }
1180
1181         ggtt->vm.insert_page = i915_ggtt_insert_page;
1182         ggtt->vm.insert_entries = i915_ggtt_insert_entries;
1183         ggtt->vm.clear_range = i915_ggtt_clear_range;
1184         ggtt->vm.cleanup = i915_gmch_remove;
1185
1186         ggtt->invalidate = gmch_ggtt_invalidate;
1187
1188         ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
1189         ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
1190
1191         if (unlikely(ggtt->do_idle_maps))
1192                 drm_notice(&i915->drm,
1193                            "Applying Ironlake quirks for intel_iommu\n");
1194
1195         return 0;
1196 }
1197
1198 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
1199 {
1200         struct drm_i915_private *i915 = gt->i915;
1201         int ret;
1202
1203         ggtt->vm.gt = gt;
1204         ggtt->vm.i915 = i915;
1205         ggtt->vm.dma = i915->drm.dev;
1206         dma_resv_init(&ggtt->vm._resv);
1207
1208         if (GRAPHICS_VER(i915) <= 5)
1209                 ret = i915_gmch_probe(ggtt);
1210         else if (GRAPHICS_VER(i915) < 8)
1211                 ret = gen6_gmch_probe(ggtt);
1212         else
1213                 ret = gen8_gmch_probe(ggtt);
1214         if (ret) {
1215                 dma_resv_fini(&ggtt->vm._resv);
1216                 return ret;
1217         }
1218
1219         if ((ggtt->vm.total - 1) >> 32) {
1220                 drm_err(&i915->drm,
1221                         "We never expected a Global GTT with more than 32bits"
1222                         " of address space! Found %lldM!\n",
1223                         ggtt->vm.total >> 20);
1224                 ggtt->vm.total = 1ULL << 32;
1225                 ggtt->mappable_end =
1226                         min_t(u64, ggtt->mappable_end, ggtt->vm.total);
1227         }
1228
1229         if (ggtt->mappable_end > ggtt->vm.total) {
1230                 drm_err(&i915->drm,
1231                         "mappable aperture extends past end of GGTT,"
1232                         " aperture=%pa, total=%llx\n",
1233                         &ggtt->mappable_end, ggtt->vm.total);
1234                 ggtt->mappable_end = ggtt->vm.total;
1235         }
1236
1237         /* GMADR is the PCI mmio aperture into the global GTT. */
1238         drm_dbg(&i915->drm, "GGTT size = %lluM\n", ggtt->vm.total >> 20);
1239         drm_dbg(&i915->drm, "GMADR size = %lluM\n",
1240                 (u64)ggtt->mappable_end >> 20);
1241         drm_dbg(&i915->drm, "DSM size = %lluM\n",
1242                 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
1243
1244         return 0;
1245 }
1246
1247 /**
1248  * i915_ggtt_probe_hw - Probe GGTT hardware location
1249  * @i915: i915 device
1250  */
1251 int i915_ggtt_probe_hw(struct drm_i915_private *i915)
1252 {
1253         int ret;
1254
1255         ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
1256         if (ret)
1257                 return ret;
1258
1259         if (intel_vtd_active(i915))
1260                 drm_info(&i915->drm, "VT-d active for gfx access\n");
1261
1262         return 0;
1263 }
1264
1265 int i915_ggtt_enable_hw(struct drm_i915_private *i915)
1266 {
1267         if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
1268                 return -EIO;
1269
1270         return 0;
1271 }
1272
1273 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
1274 {
1275         GEM_BUG_ON(ggtt->invalidate != gen8_ggtt_invalidate);
1276
1277         ggtt->invalidate = guc_ggtt_invalidate;
1278
1279         ggtt->invalidate(ggtt);
1280 }
1281
1282 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
1283 {
1284         /* XXX Temporary pardon for error unload */
1285         if (ggtt->invalidate == gen8_ggtt_invalidate)
1286                 return;
1287
1288         /* We should only be called after i915_ggtt_enable_guc() */
1289         GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
1290
1291         ggtt->invalidate = gen8_ggtt_invalidate;
1292
1293         ggtt->invalidate(ggtt);
1294 }
1295
1296 /**
1297  * i915_ggtt_resume_vm - Restore the memory mappings for a GGTT or DPT VM
1298  * @vm: The VM to restore the mappings for
1299  *
1300  * Restore the memory mappings for all objects mapped to HW via the GGTT or a
1301  * DPT page table.
1302  *
1303  * Returns %true if restoring the mapping for any object that was in a write
1304  * domain before suspend.
1305  */
1306 bool i915_ggtt_resume_vm(struct i915_address_space *vm)
1307 {
1308         struct i915_vma *vma;
1309         bool write_domain_objs = false;
1310         int open;
1311
1312         drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
1313
1314         /* First fill our portion of the GTT with scratch pages */
1315         vm->clear_range(vm, 0, vm->total);
1316
1317         /* Skip rewriting PTE on VMA unbind. */
1318         open = atomic_xchg(&vm->open, 0);
1319
1320         /* clflush objects bound into the GGTT and rebind them. */
1321         list_for_each_entry(vma, &vm->bound_list, vm_link) {
1322                 struct drm_i915_gem_object *obj = vma->obj;
1323                 unsigned int was_bound =
1324                         atomic_read(&vma->flags) & I915_VMA_BIND_MASK;
1325
1326                 GEM_BUG_ON(!was_bound);
1327                 vma->ops->bind_vma(vm, NULL, vma->resource,
1328                                    obj ? obj->cache_level : 0,
1329                                    was_bound);
1330                 if (obj) { /* only used during resume => exclusive access */
1331                         write_domain_objs |= fetch_and_zero(&obj->write_domain);
1332                         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1333                 }
1334         }
1335
1336         atomic_set(&vm->open, open);
1337
1338         return write_domain_objs;
1339 }
1340
1341 void i915_ggtt_resume(struct i915_ggtt *ggtt)
1342 {
1343         bool flush;
1344
1345         intel_gt_check_and_clear_faults(ggtt->vm.gt);
1346
1347         flush = i915_ggtt_resume_vm(&ggtt->vm);
1348
1349         ggtt->invalidate(ggtt);
1350
1351         if (flush)
1352                 wbinvd_on_all_cpus();
1353
1354         if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
1355                 setup_private_pat(ggtt->vm.gt->uncore);
1356
1357         intel_ggtt_restore_fences(ggtt);
1358 }