drivers/gpu/drm/i915/gt/intel_ggtt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <linux/agp_backend.h>
   7 #include <linux/stop_machine.h>
   8
   9 #include <asm/set_memory.h>
  10 #include <asm/smp.h>
  11
  12 #include <drm/i915_drm.h>
  13 #include <drm/intel-gtt.h>
  14
  15 #include "gem/i915_gem_lmem.h"
  16
  17 #include "intel_gt.h"
  18 #include "intel_gt_regs.h"
  19 #include "i915_drv.h"
  20 #include "i915_scatterlist.h"
  21 #include "i915_vgpu.h"
  22
  23 #include "intel_gtt.h"
  24 #include "gen8_ppgtt.h"
  25
  26 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
  27                                    unsigned long color,
  28                                    u64 *start,
  29                                    u64 *end)
  30 {
  31         if (i915_node_color_differs(node, color))
  32                 *start += I915_GTT_PAGE_SIZE;
  33
  34         /*
  35          * Also leave a space between the unallocated reserved node after the
  36          * GTT and any objects within the GTT, i.e. we use the color adjustment
  37          * to insert a guard page to prevent prefetches crossing over the
  38          * GTT boundary.
  39          */
  40         node = list_next_entry(node, node_list);
  41         if (node->color != color)
  42                 *end -= I915_GTT_PAGE_SIZE;
  43 }
  44
  45 static int ggtt_init_hw(struct i915_ggtt *ggtt)
  46 {
  47         struct drm_i915_private *i915 = ggtt->vm.i915;
  48
  49         i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
  50
  51         ggtt->vm.is_ggtt = true;
  52
  53         /* Only VLV supports read-only GGTT mappings */
  54         ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
  55
  56         if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
  57                 ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
  58
  59         if (ggtt->mappable_end) {
  60                 if (!io_mapping_init_wc(&ggtt->iomap,
  61                                         ggtt->gmadr.start,
  62                                         ggtt->mappable_end)) {
  63                         ggtt->vm.cleanup(&ggtt->vm);
  64                         return -EIO;
  65                 }
  66
  67                 ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
  68                                               ggtt->mappable_end);
  69         }
  70
  71         intel_ggtt_init_fences(ggtt);
  72
  73         return 0;
  74 }
  75
  76 /**
  77  * i915_ggtt_init_hw - Initialize GGTT hardware
  78  * @i915: i915 device
  79  */
  80 int i915_ggtt_init_hw(struct drm_i915_private *i915)
  81 {
  82         int ret;
  83
  84         /*
  85          * Note that we use page colouring to enforce a guard page at the
  86          * end of the address space. This is required as the CS may prefetch
  87          * beyond the end of the batch buffer, across the page boundary,
  88          * and beyond the end of the GTT if we do not provide a guard.
  89          */
  90         ret = ggtt_init_hw(to_gt(i915)->ggtt);
  91         if (ret)
  92                 return ret;
  93
  94         return 0;
  95 }
  96
  97 /*
  98  * Certain Gen5 chipsets require idling the GPU before
  99  * unmapping anything from the GTT when VT-d is enabled.
 100  */
 101 static bool needs_idle_maps(struct drm_i915_private *i915)
 102 {
 103         /*
 104          * Query intel_iommu to see if we need the workaround. Presumably that
 105          * was loaded first.
 106          */
 107         if (!intel_vtd_active(i915))
 108                 return false;
 109
 110         if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
 111                 return true;
 112
 113         if (GRAPHICS_VER(i915) == 12)
 114                 return true; /* XXX DMAR fault reason 7 */
 115
 116         return false;
 117 }
 118
 119 /**
 120  * i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM
 121  * @vm: The VM to suspend the mappings for
 122  *
 123  * Suspend the memory mappings for all objects mapped to HW via the GGTT or a
 124  * DPT page table.
 125  */
 126 void i915_ggtt_suspend_vm(struct i915_address_space *vm)
 127 {
 128         struct i915_vma *vma, *vn;
 129         int save_skip_rewrite;
 130
 131         drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
 132
 133 retry:
 134         i915_gem_drain_freed_objects(vm->i915);
 135
 136         mutex_lock(&vm->mutex);
 137
 138         /*
 139          * Skip rewriting PTE on VMA unbind.
 140          * FIXME: Use an argument to i915_vma_unbind() instead?
 141          */
 142         save_skip_rewrite = vm->skip_pte_rewrite;
 143         vm->skip_pte_rewrite = true;
 144
 145         list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
 146                 struct drm_i915_gem_object *obj = vma->obj;
 147
 148                 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
 149
 150                 if (i915_vma_is_pinned(vma) || !i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
 151                         continue;
 152
 153                 /* unlikely to race when GPU is idle, so no worry about slowpath.. */
 154                 if (WARN_ON(!i915_gem_object_trylock(obj, NULL))) {
 155                         /*
 156                          * No dead objects should appear here, GPU should be
 157                          * completely idle, and userspace suspended
 158                          */
 159                         i915_gem_object_get(obj);
 160
 161                         mutex_unlock(&vm->mutex);
 162
 163                         i915_gem_object_lock(obj, NULL);
 164                         GEM_WARN_ON(i915_vma_unbind(vma));
 165                         i915_gem_object_unlock(obj);
 166                         i915_gem_object_put(obj);
 167
 168                         vm->skip_pte_rewrite = save_skip_rewrite;
 169                         goto retry;
 170                 }
 171
 172                 if (!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) {
 173                         i915_vma_wait_for_bind(vma);
 174
 175                         __i915_vma_evict(vma, false);
 176                         drm_mm_remove_node(&vma->node);
 177                 }
 178
 179                 i915_gem_object_unlock(obj);
 180         }
 181
 182         vm->clear_range(vm, 0, vm->total);
 183
 184         vm->skip_pte_rewrite = save_skip_rewrite;
 185
 186         mutex_unlock(&vm->mutex);
 187 }
 188
 189 void i915_ggtt_suspend(struct i915_ggtt *ggtt)
 190 {
 191         i915_ggtt_suspend_vm(&ggtt->vm);
 192         ggtt->invalidate(ggtt);
 193
 194         intel_gt_check_and_clear_faults(ggtt->vm.gt);
 195 }
 196
 197 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
 198 {
 199         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 200
 201         spin_lock_irq(&uncore->lock);
 202         intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 203         intel_uncore_read_fw(uncore, GFX_FLSH_CNTL_GEN6);
 204         spin_unlock_irq(&uncore->lock);
 205 }
 206
 207 static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 208 {
 209         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 210
 211         /*
 212          * Note that as an uncached mmio write, this will flush the
 213          * WCB of the writes into the GGTT before it triggers the invalidate.
 214          */
 215         intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 216 }
 217
 218 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 219 {
 220         struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 221         struct drm_i915_private *i915 = ggtt->vm.i915;
 222
 223         gen8_ggtt_invalidate(ggtt);
 224
 225         if (GRAPHICS_VER(i915) >= 12)
 226                 intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
 227                                       GEN12_GUC_TLB_INV_CR_INVALIDATE);
 228         else
 229                 intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 230 }
 231
 232 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
 233 {
 234         intel_gtt_chipset_flush();
 235 }
 236
 237 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
 238                          enum i915_cache_level level,
 239                          u32 flags)
 240 {
 241         gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
 242
 243         if (flags & PTE_LM)
 244                 pte |= GEN12_GGTT_PTE_LM;
 245
 246         return pte;
 247 }
 248
 249 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
 250 {
 251         writeq(pte, addr);
 252 }
 253
 254 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
 255                                   dma_addr_t addr,
 256                                   u64 offset,
 257                                   enum i915_cache_level level,
 258                                   u32 flags)
 259 {
 260         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 261         gen8_pte_t __iomem *pte =
 262                 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
 263
 264         gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
 265
 266         ggtt->invalidate(ggtt);
 267 }
 268
 269 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 270                                      struct i915_vma_resource *vma_res,
 271                                      enum i915_cache_level level,
 272                                      u32 flags)
 273 {
 274         const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
 275         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 276         gen8_pte_t __iomem *gte;
 277         gen8_pte_t __iomem *end;
 278         struct sgt_iter iter;
 279         dma_addr_t addr;
 280
 281         /*
 282          * Note that we ignore PTE_READ_ONLY here. The caller must be careful
 283          * not to allow the user to override access to a read only page.
 284          */
 285
 286         gte = (gen8_pte_t __iomem *)ggtt->gsm;
 287         gte += vma_res->start / I915_GTT_PAGE_SIZE;
 288         end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
 289
 290         for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
 291                 gen8_set_pte(gte++, pte_encode | addr);
 292         GEM_BUG_ON(gte > end);
 293
 294         /* Fill the allocated but "unused" space beyond the end of the buffer */
 295         while (gte < end)
 296                 gen8_set_pte(gte++, vm->scratch[0]->encode);
 297
 298         /*
 299          * We want to flush the TLBs only after we're certain all the PTE
 300          * updates have finished.
 301          */
 302         ggtt->invalidate(ggtt);
 303 }
 304
 305 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
 306                                   dma_addr_t addr,
 307                                   u64 offset,
 308                                   enum i915_cache_level level,
 309                                   u32 flags)
 310 {
 311         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 312         gen6_pte_t __iomem *pte =
 313                 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
 314
 315         iowrite32(vm->pte_encode(addr, level, flags), pte);
 316
 317         ggtt->invalidate(ggtt);
 318 }
 319
 320 /*
 321  * Binds an object into the global gtt with the specified cache level.
 322  * The object will be accessible to the GPU via commands whose operands
 323  * reference offsets within the global GTT as well as accessible by the GPU
 324  * through the GMADR mapped BAR (i915->mm.gtt->gtt).
 325  */
 326 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 327                                      struct i915_vma_resource *vma_res,
 328                                      enum i915_cache_level level,
 329                                      u32 flags)
 330 {
 331         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 332         gen6_pte_t __iomem *gte;
 333         gen6_pte_t __iomem *end;
 334         struct sgt_iter iter;
 335         dma_addr_t addr;
 336
 337         gte = (gen6_pte_t __iomem *)ggtt->gsm;
 338         gte += vma_res->start / I915_GTT_PAGE_SIZE;
 339         end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
 340
 341         for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
 342                 iowrite32(vm->pte_encode(addr, level, flags), gte++);
 343         GEM_BUG_ON(gte > end);
 344
 345         /* Fill the allocated but "unused" space beyond the end of the buffer */
 346         while (gte < end)
 347                 iowrite32(vm->scratch[0]->encode, gte++);
 348
 349         /*
 350          * We want to flush the TLBs only after we're certain all the PTE
 351          * updates have finished.
 352          */
 353         ggtt->invalidate(ggtt);
 354 }
 355
 356 static void nop_clear_range(struct i915_address_space *vm,
 357                             u64 start, u64 length)
 358 {
 359 }
 360
 361 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
 362                                   u64 start, u64 length)
 363 {
 364         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 365         unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
 366         unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
 367         const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
 368         gen8_pte_t __iomem *gtt_base =
 369                 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
 370         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
 371         int i;
 372
 373         if (WARN(num_entries > max_entries,
 374                  "First entry = %d; Num entries = %d (max=%d)\n",
 375                  first_entry, num_entries, max_entries))
 376                 num_entries = max_entries;
 377
 378         for (i = 0; i < num_entries; i++)
 379                 gen8_set_pte(&gtt_base[i], scratch_pte);
 380 }
 381
 382 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
 383 {
 384         /*
 385          * Make sure the internal GAM fifo has been cleared of all GTT
 386          * writes before exiting stop_machine(). This guarantees that
 387          * any aperture accesses waiting to start in another process
 388          * cannot back up behind the GTT writes causing a hang.
 389          * The register can be any arbitrary GAM register.
 390          */
 391         intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
 392 }
 393
 394 struct insert_page {
 395         struct i915_address_space *vm;
 396         dma_addr_t addr;
 397         u64 offset;
 398         enum i915_cache_level level;
 399 };
 400
 401 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
 402 {
 403         struct insert_page *arg = _arg;
 404
 405         gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
 406         bxt_vtd_ggtt_wa(arg->vm);
 407
 408         return 0;
 409 }
 410
 411 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
 412                                           dma_addr_t addr,
 413                                           u64 offset,
 414                                           enum i915_cache_level level,
 415                                           u32 unused)
 416 {
 417         struct insert_page arg = { vm, addr, offset, level };
 418
 419         stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
 420 }
 421
 422 struct insert_entries {
 423         struct i915_address_space *vm;
 424         struct i915_vma_resource *vma_res;
 425         enum i915_cache_level level;
 426         u32 flags;
 427 };
 428
 429 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
 430 {
 431         struct insert_entries *arg = _arg;
 432
 433         gen8_ggtt_insert_entries(arg->vm, arg->vma_res, arg->level, arg->flags);
 434         bxt_vtd_ggtt_wa(arg->vm);
 435
 436         return 0;
 437 }
 438
 439 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
 440                                              struct i915_vma_resource *vma_res,
 441                                              enum i915_cache_level level,
 442                                              u32 flags)
 443 {
 444         struct insert_entries arg = { vm, vma_res, level, flags };
 445
 446         stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
 447 }
 448
 449 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 450                                   u64 start, u64 length)
 451 {
 452         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 453         unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
 454         unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
 455         gen6_pte_t scratch_pte, __iomem *gtt_base =
 456                 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
 457         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
 458         int i;
 459
 460         if (WARN(num_entries > max_entries,
 461                  "First entry = %d; Num entries = %d (max=%d)\n",
 462                  first_entry, num_entries, max_entries))
 463                 num_entries = max_entries;
 464
 465         scratch_pte = vm->scratch[0]->encode;
 466         for (i = 0; i < num_entries; i++)
 467                 iowrite32(scratch_pte, &gtt_base[i]);
 468 }
 469
 470 static void i915_ggtt_insert_page(struct i915_address_space *vm,
 471                                   dma_addr_t addr,
 472                                   u64 offset,
 473                                   enum i915_cache_level cache_level,
 474                                   u32 unused)
 475 {
 476         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 477                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 478
 479         intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
 480 }
 481
 482 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
 483                                      struct i915_vma_resource *vma_res,
 484                                      enum i915_cache_level cache_level,
 485                                      u32 unused)
 486 {
 487         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 488                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 489
 490         intel_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT,
 491                                     flags);
 492 }
 493
 494 static void i915_ggtt_clear_range(struct i915_address_space *vm,
 495                                   u64 start, u64 length)
 496 {
 497         intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
 498 }
 499
 500 static void ggtt_bind_vma(struct i915_address_space *vm,
 501                           struct i915_vm_pt_stash *stash,
 502                           struct i915_vma_resource *vma_res,
 503                           enum i915_cache_level cache_level,
 504                           u32 flags)
 505 {
 506         u32 pte_flags;
 507
 508         if (vma_res->bound_flags & (~flags & I915_VMA_BIND_MASK))
 509                 return;
 510
 511         vma_res->bound_flags |= flags;
 512
 513         /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
 514         pte_flags = 0;
 515         if (vma_res->bi.readonly)
 516                 pte_flags |= PTE_READ_ONLY;
 517         if (vma_res->bi.lmem)
 518                 pte_flags |= PTE_LM;
 519
 520         vm->insert_entries(vm, vma_res, cache_level, pte_flags);
 521         vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
 522 }
 523
 524 static void ggtt_unbind_vma(struct i915_address_space *vm,
 525                             struct i915_vma_resource *vma_res)
 526 {
 527         vm->clear_range(vm, vma_res->start, vma_res->vma_size);
 528 }
 529
 530 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
 531 {
 532         u64 size;
 533         int ret;
 534
 535         if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
 536                 return 0;
 537
 538         GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
 539         size = ggtt->vm.total - GUC_GGTT_TOP;
 540
 541         ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &ggtt->uc_fw, size,
 542                                    GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
 543                                    PIN_NOEVICT);
 544         if (ret)
 545                 drm_dbg(&ggtt->vm.i915->drm,
 546                         "Failed to reserve top of GGTT for GuC\n");
 547
 548         return ret;
 549 }
 550
 551 static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
 552 {
 553         if (drm_mm_node_allocated(&ggtt->uc_fw))
 554                 drm_mm_remove_node(&ggtt->uc_fw);
 555 }
 556
 557 static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
 558 {
 559         ggtt_release_guc_top(ggtt);
 560         if (drm_mm_node_allocated(&ggtt->error_capture))
 561                 drm_mm_remove_node(&ggtt->error_capture);
 562         mutex_destroy(&ggtt->error_mutex);
 563 }
 564
 565 static int init_ggtt(struct i915_ggtt *ggtt)
 566 {
 567         /*
 568          * Let GEM Manage all of the aperture.
 569          *
 570          * However, leave one page at the end still bound to the scratch page.
 571          * There are a number of places where the hardware apparently prefetches
 572          * past the end of the object, and we've seen multiple hangs with the
 573          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 574          * aperture.  One page should be enough to keep any prefetching inside
 575          * of the aperture.
 576          */
 577         unsigned long hole_start, hole_end;
 578         struct drm_mm_node *entry;
 579         int ret;
 580
 581         /*
 582          * GuC requires all resources that we're sharing with it to be placed in
 583          * non-WOPCM memory. If GuC is not present or not in use we still need a
 584          * small bias as ring wraparound at offset 0 sometimes hangs. No idea
 585          * why.
 586          */
 587         ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
 588                                intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
 589
 590         ret = intel_vgt_balloon(ggtt);
 591         if (ret)
 592                 return ret;
 593
 594         mutex_init(&ggtt->error_mutex);
 595         if (ggtt->mappable_end) {
 596                 /*
 597                  * Reserve a mappable slot for our lockless error capture.
 598                  *
 599                  * We strongly prefer taking address 0x0 in order to protect
 600                  * other critical buffers against accidental overwrites,
 601                  * as writing to address 0 is a very common mistake.
 602                  *
 603                  * Since 0 may already be in use by the system (e.g. the BIOS
 604                  * framebuffer), we let the reservation fail quietly and hope
 605                  * 0 remains reserved always.
 606                  *
 607                  * If we fail to reserve 0, and then fail to find any space
 608                  * for an error-capture, remain silent. We can afford not
 609                  * to reserve an error_capture node as we have fallback
 610                  * paths, and we trust that 0 will remain reserved. However,
 611                  * the only likely reason for failure to insert is a driver
 612                  * bug, which we expect to cause other failures...
 613                  */
 614                 ggtt->error_capture.size = I915_GTT_PAGE_SIZE;
 615                 ggtt->error_capture.color = I915_COLOR_UNEVICTABLE;
 616                 if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture))
 617                         drm_mm_insert_node_in_range(&ggtt->vm.mm,
 618                                                     &ggtt->error_capture,
 619                                                     ggtt->error_capture.size, 0,
 620                                                     ggtt->error_capture.color,
 621                                                     0, ggtt->mappable_end,
 622                                                     DRM_MM_INSERT_LOW);
 623         }
 624         if (drm_mm_node_allocated(&ggtt->error_capture))
 625                 drm_dbg(&ggtt->vm.i915->drm,
 626                         "Reserved GGTT:[%llx, %llx] for use by error capture\n",
 627                         ggtt->error_capture.start,
 628                         ggtt->error_capture.start + ggtt->error_capture.size);
 629
 630         /*
 631          * The upper portion of the GuC address space has a sizeable hole
 632          * (several MB) that is inaccessible by GuC. Reserve this range within
 633          * GGTT as it can comfortably hold GuC/HuC firmware images.
 634          */
 635         ret = ggtt_reserve_guc_top(ggtt);
 636         if (ret)
 637                 goto err;
 638
 639         /* Clear any non-preallocated blocks */
 640         drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
 641                 drm_dbg(&ggtt->vm.i915->drm,
 642                         "clearing unused GTT space: [%lx, %lx]\n",
 643                         hole_start, hole_end);
 644                 ggtt->vm.clear_range(&ggtt->vm, hole_start,
 645                                      hole_end - hole_start);
 646         }
 647
 648         /* And finally clear the reserved guard page */
 649         ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 650
 651         return 0;
 652
 653 err:
 654         cleanup_init_ggtt(ggtt);
 655         return ret;
 656 }
 657
 658 static void aliasing_gtt_bind_vma(struct i915_address_space *vm,
 659                                   struct i915_vm_pt_stash *stash,
 660                                   struct i915_vma_resource *vma_res,
 661                                   enum i915_cache_level cache_level,
 662                                   u32 flags)
 663 {
 664         u32 pte_flags;
 665
 666         /* Currently applicable only to VLV */
 667         pte_flags = 0;
 668         if (vma_res->bi.readonly)
 669                 pte_flags |= PTE_READ_ONLY;
 670
 671         if (flags & I915_VMA_LOCAL_BIND)
 672                 ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm,
 673                                stash, vma_res, cache_level, flags);
 674
 675         if (flags & I915_VMA_GLOBAL_BIND)
 676                 vm->insert_entries(vm, vma_res, cache_level, pte_flags);
 677
 678         vma_res->bound_flags |= flags;
 679 }
 680
 681 static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
 682                                     struct i915_vma_resource *vma_res)
 683 {
 684         if (vma_res->bound_flags & I915_VMA_GLOBAL_BIND)
 685                 vm->clear_range(vm, vma_res->start, vma_res->vma_size);
 686
 687         if (vma_res->bound_flags & I915_VMA_LOCAL_BIND)
 688                 ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma_res);
 689 }
 690
 691 static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
 692 {
 693         struct i915_vm_pt_stash stash = {};
 694         struct i915_ppgtt *ppgtt;
 695         int err;
 696
 697         ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
 698         if (IS_ERR(ppgtt))
 699                 return PTR_ERR(ppgtt);
 700
 701         if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
 702                 err = -ENODEV;
 703                 goto err_ppgtt;
 704         }
 705
 706         err = i915_vm_alloc_pt_stash(&ppgtt->vm, &stash, ggtt->vm.total);
 707         if (err)
 708                 goto err_ppgtt;
 709
 710         i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
 711         err = i915_vm_map_pt_stash(&ppgtt->vm, &stash);
 712         i915_gem_object_unlock(ppgtt->vm.scratch[0]);
 713         if (err)
 714                 goto err_stash;
 715
 716         /*
 717          * Note we only pre-allocate as far as the end of the global
 718          * GTT. On 48b / 4-level page-tables, the difference is very,
 719          * very significant! We have to preallocate as GVT/vgpu does
 720          * not like the page directory disappearing.
 721          */
 722         ppgtt->vm.allocate_va_range(&ppgtt->vm, &stash, 0, ggtt->vm.total);
 723
 724         ggtt->alias = ppgtt;
 725         ggtt->vm.bind_async_flags |= ppgtt->vm.bind_async_flags;
 726
 727         GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
 728         ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
 729
 730         GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
 731         ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
 732
 733         i915_vm_free_pt_stash(&ppgtt->vm, &stash);
 734         return 0;
 735
 736 err_stash:
 737         i915_vm_free_pt_stash(&ppgtt->vm, &stash);
 738 err_ppgtt:
 739         i915_vm_put(&ppgtt->vm);
 740         return err;
 741 }
 742
 743 static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)
 744 {
 745         struct i915_ppgtt *ppgtt;
 746
 747         ppgtt = fetch_and_zero(&ggtt->alias);
 748         if (!ppgtt)
 749                 return;
 750
 751         i915_vm_put(&ppgtt->vm);
 752
 753         ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
 754         ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
 755 }
 756
 757 int i915_init_ggtt(struct drm_i915_private *i915)
 758 {
 759         int ret;
 760
 761         ret = init_ggtt(to_gt(i915)->ggtt);
 762         if (ret)
 763                 return ret;
 764
 765         if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
 766                 ret = init_aliasing_ppgtt(to_gt(i915)->ggtt);
 767                 if (ret)
 768                         cleanup_init_ggtt(to_gt(i915)->ggtt);
 769         }
 770
 771         return 0;
 772 }
 773
 774 static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
 775 {
 776         struct i915_vma *vma, *vn;
 777
 778         flush_workqueue(ggtt->vm.i915->wq);
 779         i915_gem_drain_freed_objects(ggtt->vm.i915);
 780
 781         mutex_lock(&ggtt->vm.mutex);
 782
 783         ggtt->vm.skip_pte_rewrite = true;
 784
 785         list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link) {
 786                 struct drm_i915_gem_object *obj = vma->obj;
 787                 bool trylock;
 788
 789                 trylock = i915_gem_object_trylock(obj, NULL);
 790                 WARN_ON(!trylock);
 791
 792                 WARN_ON(__i915_vma_unbind(vma));
 793                 if (trylock)
 794                         i915_gem_object_unlock(obj);
 795         }
 796
 797         if (drm_mm_node_allocated(&ggtt->error_capture))
 798                 drm_mm_remove_node(&ggtt->error_capture);
 799         mutex_destroy(&ggtt->error_mutex);
 800
 801         ggtt_release_guc_top(ggtt);
 802         intel_vgt_deballoon(ggtt);
 803
 804         ggtt->vm.cleanup(&ggtt->vm);
 805
 806         mutex_unlock(&ggtt->vm.mutex);
 807         i915_address_space_fini(&ggtt->vm);
 808
 809         arch_phys_wc_del(ggtt->mtrr);
 810
 811         if (ggtt->iomap.size)
 812                 io_mapping_fini(&ggtt->iomap);
 813 }
 814
 815 /**
 816  * i915_ggtt_driver_release - Clean up GGTT hardware initialization
 817  * @i915: i915 device
 818  */
 819 void i915_ggtt_driver_release(struct drm_i915_private *i915)
 820 {
 821         struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
 822
 823         fini_aliasing_ppgtt(ggtt);
 824
 825         intel_ggtt_fini_fences(ggtt);
 826         ggtt_cleanup_hw(ggtt);
 827 }
 828
 829 /**
 830  * i915_ggtt_driver_late_release - Cleanup of GGTT that needs to be done after
 831  * all free objects have been drained.
 832  * @i915: i915 device
 833  */
 834 void i915_ggtt_driver_late_release(struct drm_i915_private *i915)
 835 {
 836         struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
 837
 838         GEM_WARN_ON(kref_read(&ggtt->vm.resv_ref) != 1);
 839         dma_resv_fini(&ggtt->vm._resv);
 840 }
 841
 842 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 843 {
 844         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 845         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 846         return snb_gmch_ctl << 20;
 847 }
 848
 849 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
 850 {
 851         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
 852         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
 853         if (bdw_gmch_ctl)
 854                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
 855
 856 #ifdef CONFIG_X86_32
 857         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
 858         if (bdw_gmch_ctl > 4)
 859                 bdw_gmch_ctl = 4;
 860 #endif
 861
 862         return bdw_gmch_ctl << 20;
 863 }
 864
 865 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
 866 {
 867         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
 868         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
 869
 870         if (gmch_ctrl)
 871                 return 1 << (20 + gmch_ctrl);
 872
 873         return 0;
 874 }
 875
 876 static unsigned int gen6_gttmmadr_size(struct drm_i915_private *i915)
 877 {
 878         /*
 879          * GEN6: GTTMMADR size is 4MB and GTTADR starts at 2MB offset
 880          * GEN8: GTTMMADR size is 16MB and GTTADR starts at 8MB offset
 881          */
 882         GEM_BUG_ON(GRAPHICS_VER(i915) < 6);
 883         return (GRAPHICS_VER(i915) < 8) ? SZ_4M : SZ_16M;
 884 }
 885
 886 static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
 887 {
 888         return gen6_gttmmadr_size(i915) / 2;
 889 }
 890
 891 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 892 {
 893         struct drm_i915_private *i915 = ggtt->vm.i915;
 894         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 895         phys_addr_t phys_addr;
 896         u32 pte_flags;
 897         int ret;
 898
 899         GEM_WARN_ON(pci_resource_len(pdev, 0) != gen6_gttmmadr_size(i915));
 900         phys_addr = pci_resource_start(pdev, 0) + gen6_gttadr_offset(i915);
 901
 902         /*
 903          * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
 904          * will be dropped. For WC mappings in general we have 64 byte burst
 905          * writes when the WC buffer is flushed, so we can't use it, but have to
 906          * resort to an uncached mapping. The WC issue is easily caught by the
 907          * readback check when writing GTT PTE entries.
 908          */
 909         if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
 910                 ggtt->gsm = ioremap(phys_addr, size);
 911         else
 912                 ggtt->gsm = ioremap_wc(phys_addr, size);
 913         if (!ggtt->gsm) {
 914                 drm_err(&i915->drm, "Failed to map the ggtt page table\n");
 915                 return -ENOMEM;
 916         }
 917
 918         kref_init(&ggtt->vm.resv_ref);
 919         ret = setup_scratch_page(&ggtt->vm);
 920         if (ret) {
 921                 drm_err(&i915->drm, "Scratch setup failed\n");
 922                 /* iounmap will also get called at remove, but meh */
 923                 iounmap(ggtt->gsm);
 924                 return ret;
 925         }
 926
 927         pte_flags = 0;
 928         if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))
 929                 pte_flags |= PTE_LM;
 930
 931         ggtt->vm.scratch[0]->encode =
 932                 ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
 933                                     I915_CACHE_NONE, pte_flags);
 934
 935         return 0;
 936 }
 937
 938 static void gen6_gmch_remove(struct i915_address_space *vm)
 939 {
 940         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 941
 942         iounmap(ggtt->gsm);
 943         free_scratch(vm);
 944 }
 945
 946 static struct resource pci_resource(struct pci_dev *pdev, int bar)
 947 {
 948         return (struct resource)DEFINE_RES_MEM(pci_resource_start(pdev, bar),
 949                                                pci_resource_len(pdev, bar));
 950 }
 951
 952 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 953 {
 954         struct drm_i915_private *i915 = ggtt->vm.i915;
 955         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 956         unsigned int size;
 957         u16 snb_gmch_ctl;
 958
 959         /* TODO: We're not aware of mappable constraints on gen8 yet */
 960         if (!HAS_LMEM(i915)) {
 961                 ggtt->gmadr = pci_resource(pdev, 2);
 962                 ggtt->mappable_end = resource_size(&ggtt->gmadr);
 963         }
 964
 965         pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 966         if (IS_CHERRYVIEW(i915))
 967                 size = chv_get_total_gtt_size(snb_gmch_ctl);
 968         else
 969                 size = gen8_get_total_gtt_size(snb_gmch_ctl);
 970
 971         ggtt->vm.alloc_pt_dma = alloc_pt_dma;
 972         ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
 973         ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
 974
 975         ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
 976         ggtt->vm.cleanup = gen6_gmch_remove;
 977         ggtt->vm.insert_page = gen8_ggtt_insert_page;
 978         ggtt->vm.clear_range = nop_clear_range;
 979         if (intel_scanout_needs_vtd_wa(i915))
 980                 ggtt->vm.clear_range = gen8_ggtt_clear_range;
 981
 982         ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
 983
 984         /*
 985          * Serialize GTT updates with aperture access on BXT if VT-d is on,
 986          * and always on CHV.
 987          */
 988         if (intel_vm_no_concurrent_access_wa(i915)) {
 989                 ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
 990                 ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
 991                 ggtt->vm.bind_async_flags =
 992                         I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
 993         }
 994
 995         ggtt->invalidate = gen8_ggtt_invalidate;
 996
 997         ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
 998         ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
 999
1000         ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
1001
1002         setup_private_pat(ggtt->vm.gt->uncore);
1003
1004         return ggtt_probe_common(ggtt, size);
1005 }
1006
1007 static u64 snb_pte_encode(dma_addr_t addr,
1008                           enum i915_cache_level level,
1009                           u32 flags)
1010 {
1011         gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1012
1013         switch (level) {
1014         case I915_CACHE_L3_LLC:
1015         case I915_CACHE_LLC:
1016                 pte |= GEN6_PTE_CACHE_LLC;
1017                 break;
1018         case I915_CACHE_NONE:
1019                 pte |= GEN6_PTE_UNCACHED;
1020                 break;
1021         default:
1022                 MISSING_CASE(level);
1023         }
1024
1025         return pte;
1026 }
1027
1028 static u64 ivb_pte_encode(dma_addr_t addr,
1029                           enum i915_cache_level level,
1030                           u32 flags)
1031 {
1032         gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1033
1034         switch (level) {
1035         case I915_CACHE_L3_LLC:
1036                 pte |= GEN7_PTE_CACHE_L3_LLC;
1037                 break;
1038         case I915_CACHE_LLC:
1039                 pte |= GEN6_PTE_CACHE_LLC;
1040                 break;
1041         case I915_CACHE_NONE:
1042                 pte |= GEN6_PTE_UNCACHED;
1043                 break;
1044         default:
1045                 MISSING_CASE(level);
1046         }
1047
1048         return pte;
1049 }
1050
1051 static u64 byt_pte_encode(dma_addr_t addr,
1052                           enum i915_cache_level level,
1053                           u32 flags)
1054 {
1055         gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1056
1057         if (!(flags & PTE_READ_ONLY))
1058                 pte |= BYT_PTE_WRITEABLE;
1059
1060         if (level != I915_CACHE_NONE)
1061                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
1062
1063         return pte;
1064 }
1065
1066 static u64 hsw_pte_encode(dma_addr_t addr,
1067                           enum i915_cache_level level,
1068                           u32 flags)
1069 {
1070         gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1071
1072         if (level != I915_CACHE_NONE)
1073                 pte |= HSW_WB_LLC_AGE3;
1074
1075         return pte;
1076 }
1077
1078 static u64 iris_pte_encode(dma_addr_t addr,
1079                            enum i915_cache_level level,
1080                            u32 flags)
1081 {
1082         gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
1083
1084         switch (level) {
1085         case I915_CACHE_NONE:
1086                 break;
1087         case I915_CACHE_WT:
1088                 pte |= HSW_WT_ELLC_LLC_AGE3;
1089                 break;
1090         default:
1091                 pte |= HSW_WB_ELLC_LLC_AGE3;
1092                 break;
1093         }
1094
1095         return pte;
1096 }
1097
1098 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
1099 {
1100         struct drm_i915_private *i915 = ggtt->vm.i915;
1101         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1102         unsigned int size;
1103         u16 snb_gmch_ctl;
1104
1105         ggtt->gmadr = pci_resource(pdev, 2);
1106         ggtt->mappable_end = resource_size(&ggtt->gmadr);
1107
1108         /*
1109          * 64/512MB is the current min/max we actually know of, but this is
1110          * just a coarse sanity check.
1111          */
1112         if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
1113                 drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
1114                         &ggtt->mappable_end);
1115                 return -ENXIO;
1116         }
1117
1118         pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1119
1120         size = gen6_get_total_gtt_size(snb_gmch_ctl);
1121         ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
1122
1123         ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1124         ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
1125
1126         ggtt->vm.clear_range = nop_clear_range;
1127         if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
1128                 ggtt->vm.clear_range = gen6_ggtt_clear_range;
1129         ggtt->vm.insert_page = gen6_ggtt_insert_page;
1130         ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
1131         ggtt->vm.cleanup = gen6_gmch_remove;
1132
1133         ggtt->invalidate = gen6_ggtt_invalidate;
1134
1135         if (HAS_EDRAM(i915))
1136                 ggtt->vm.pte_encode = iris_pte_encode;
1137         else if (IS_HASWELL(i915))
1138                 ggtt->vm.pte_encode = hsw_pte_encode;
1139         else if (IS_VALLEYVIEW(i915))
1140                 ggtt->vm.pte_encode = byt_pte_encode;
1141         else if (GRAPHICS_VER(i915) >= 7)
1142                 ggtt->vm.pte_encode = ivb_pte_encode;
1143         else
1144                 ggtt->vm.pte_encode = snb_pte_encode;
1145
1146         ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
1147         ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
1148
1149         return ggtt_probe_common(ggtt, size);
1150 }
1151
1152 static void i915_gmch_remove(struct i915_address_space *vm)
1153 {
1154         intel_gmch_remove();
1155 }
1156
1157 static int i915_gmch_probe(struct i915_ggtt *ggtt)
1158 {
1159         struct drm_i915_private *i915 = ggtt->vm.i915;
1160         phys_addr_t gmadr_base;
1161         int ret;
1162
1163         ret = intel_gmch_probe(i915->bridge_dev, to_pci_dev(i915->drm.dev), NULL);
1164         if (!ret) {
1165                 drm_err(&i915->drm, "failed to set up gmch\n");
1166                 return -EIO;
1167         }
1168
1169         intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
1170
1171         ggtt->gmadr =
1172                 (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
1173
1174         ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1175         ggtt->vm.alloc_scratch_dma = alloc_pt_dma;
1176
1177         if (needs_idle_maps(i915)) {
1178                 drm_notice(&i915->drm,
1179                            "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n");
1180                 ggtt->do_idle_maps = true;
1181         }
1182
1183         ggtt->vm.insert_page = i915_ggtt_insert_page;
1184         ggtt->vm.insert_entries = i915_ggtt_insert_entries;
1185         ggtt->vm.clear_range = i915_ggtt_clear_range;
1186         ggtt->vm.cleanup = i915_gmch_remove;
1187
1188         ggtt->invalidate = gmch_ggtt_invalidate;
1189
1190         ggtt->vm.vma_ops.bind_vma    = ggtt_bind_vma;
1191         ggtt->vm.vma_ops.unbind_vma  = ggtt_unbind_vma;
1192
1193         if (unlikely(ggtt->do_idle_maps))
1194                 drm_notice(&i915->drm,
1195                            "Applying Ironlake quirks for intel_iommu\n");
1196
1197         return 0;
1198 }
1199
1200 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
1201 {
1202         struct drm_i915_private *i915 = gt->i915;
1203         int ret;
1204
1205         ggtt->vm.gt = gt;
1206         ggtt->vm.i915 = i915;
1207         ggtt->vm.dma = i915->drm.dev;
1208         dma_resv_init(&ggtt->vm._resv);
1209
1210         if (GRAPHICS_VER(i915) <= 5)
1211                 ret = i915_gmch_probe(ggtt);
1212         else if (GRAPHICS_VER(i915) < 8)
1213                 ret = gen6_gmch_probe(ggtt);
1214         else
1215                 ret = gen8_gmch_probe(ggtt);
1216         if (ret) {
1217                 dma_resv_fini(&ggtt->vm._resv);
1218                 return ret;
1219         }
1220
1221         if ((ggtt->vm.total - 1) >> 32) {
1222                 drm_err(&i915->drm,
1223                         "We never expected a Global GTT with more than 32bits"
1224                         " of address space! Found %lldM!\n",
1225                         ggtt->vm.total >> 20);
1226                 ggtt->vm.total = 1ULL << 32;
1227                 ggtt->mappable_end =
1228                         min_t(u64, ggtt->mappable_end, ggtt->vm.total);
1229         }
1230
1231         if (ggtt->mappable_end > ggtt->vm.total) {
1232                 drm_err(&i915->drm,
1233                         "mappable aperture extends past end of GGTT,"
1234                         " aperture=%pa, total=%llx\n",
1235                         &ggtt->mappable_end, ggtt->vm.total);
1236                 ggtt->mappable_end = ggtt->vm.total;
1237         }
1238
1239         /* GMADR is the PCI mmio aperture into the global GTT. */
1240         drm_dbg(&i915->drm, "GGTT size = %lluM\n", ggtt->vm.total >> 20);
1241         drm_dbg(&i915->drm, "GMADR size = %lluM\n",
1242                 (u64)ggtt->mappable_end >> 20);
1243         drm_dbg(&i915->drm, "DSM size = %lluM\n",
1244                 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
1245
1246         return 0;
1247 }
1248
1249 /**
1250  * i915_ggtt_probe_hw - Probe GGTT hardware location
1251  * @i915: i915 device
1252  */
1253 int i915_ggtt_probe_hw(struct drm_i915_private *i915)
1254 {
1255         int ret;
1256
1257         ret = ggtt_probe_hw(to_gt(i915)->ggtt, to_gt(i915));
1258         if (ret)
1259                 return ret;
1260
1261         if (intel_vtd_active(i915))
1262                 drm_info(&i915->drm, "VT-d active for gfx access\n");
1263
1264         return 0;
1265 }
1266
1267 int i915_ggtt_enable_hw(struct drm_i915_private *i915)
1268 {
1269         if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
1270                 return -EIO;
1271
1272         return 0;
1273 }
1274
1275 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
1276 {
1277         GEM_BUG_ON(ggtt->invalidate != gen8_ggtt_invalidate);
1278
1279         ggtt->invalidate = guc_ggtt_invalidate;
1280
1281         ggtt->invalidate(ggtt);
1282 }
1283
1284 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
1285 {
1286         /* XXX Temporary pardon for error unload */
1287         if (ggtt->invalidate == gen8_ggtt_invalidate)
1288                 return;
1289
1290         /* We should only be called after i915_ggtt_enable_guc() */
1291         GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
1292
1293         ggtt->invalidate = gen8_ggtt_invalidate;
1294
1295         ggtt->invalidate(ggtt);
1296 }
1297
1298 /**
1299  * i915_ggtt_resume_vm - Restore the memory mappings for a GGTT or DPT VM
1300  * @vm: The VM to restore the mappings for
1301  *
1302  * Restore the memory mappings for all objects mapped to HW via the GGTT or a
1303  * DPT page table.
1304  *
1305  * Returns %true if restoring the mapping for any object that was in a write
1306  * domain before suspend.
1307  */
1308 bool i915_ggtt_resume_vm(struct i915_address_space *vm)
1309 {
1310         struct i915_vma *vma;
1311         bool write_domain_objs = false;
1312
1313         drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
1314
1315         /* First fill our portion of the GTT with scratch pages */
1316         vm->clear_range(vm, 0, vm->total);
1317
1318         /* clflush objects bound into the GGTT and rebind them. */
1319         list_for_each_entry(vma, &vm->bound_list, vm_link) {
1320                 struct drm_i915_gem_object *obj = vma->obj;
1321                 unsigned int was_bound =
1322                         atomic_read(&vma->flags) & I915_VMA_BIND_MASK;
1323
1324                 GEM_BUG_ON(!was_bound);
1325                 vma->ops->bind_vma(vm, NULL, vma->resource,
1326                                    obj ? obj->cache_level : 0,
1327                                    was_bound);
1328                 if (obj) { /* only used during resume => exclusive access */
1329                         write_domain_objs |= fetch_and_zero(&obj->write_domain);
1330                         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1331                 }
1332         }
1333
1334         return write_domain_objs;
1335 }
1336
1337 void i915_ggtt_resume(struct i915_ggtt *ggtt)
1338 {
1339         bool flush;
1340
1341         intel_gt_check_and_clear_faults(ggtt->vm.gt);
1342
1343         flush = i915_ggtt_resume_vm(&ggtt->vm);
1344
1345         ggtt->invalidate(ggtt);
1346
1347         if (flush)
1348                 wbinvd_on_all_cpus();
1349
1350         if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
1351                 setup_private_pat(ggtt->vm.gt->uncore);
1352
1353         intel_ggtt_restore_fences(ggtt);
1354 }