2 * SPDX-License-Identifier: MIT
4 * Copyright © 2019 Intel Corporation
7 #ifndef __INTEL_ENGINE_TYPES__
8 #define __INTEL_ENGINE_TYPES__
10 #include <linux/average.h>
11 #include <linux/hashtable.h>
12 #include <linux/irq_work.h>
13 #include <linux/kref.h>
14 #include <linux/list.h>
15 #include <linux/llist.h>
16 #include <linux/rbtree.h>
17 #include <linux/timer.h>
18 #include <linux/types.h>
19 #include <linux/workqueue.h>
23 #include "i915_priolist_types.h"
24 #include "i915_selftest.h"
25 #include "intel_engine_pool_types.h"
26 #include "intel_sseu.h"
27 #include "intel_timeline_types.h"
28 #include "intel_wakeref.h"
29 #include "intel_workarounds_types.h"
31 /* Legacy HW Engine ID */
42 /* Gen11+ HW Engine class + instance */
43 #define RENDER_CLASS 0
44 #define VIDEO_DECODE_CLASS 1
45 #define VIDEO_ENHANCEMENT_CLASS 2
46 #define COPY_ENGINE_CLASS 3
48 #define MAX_ENGINE_CLASS 4
49 #define MAX_ENGINE_INSTANCE 3
51 #define I915_MAX_SLICES 3
52 #define I915_MAX_SUBSLICES 8
54 #define I915_CMD_HASH_ORDER 9
57 struct drm_i915_gem_object;
58 struct drm_i915_reg_table;
59 struct i915_gem_context;
61 struct i915_sched_attr;
66 typedef u8 intel_engine_mask_t;
67 #define ALL_ENGINES ((intel_engine_mask_t)~0ul)
69 struct intel_hw_status_page {
74 struct intel_instdone {
76 /* The following exist only in the RCS engine */
78 u32 slice_common_extra[2];
79 u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
80 u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
84 * we use a single page to load ctx workarounds so all of these
85 * values are referred in terms of dwords
87 * struct i915_wa_ctx_bb:
88 * offset: specifies batch starting position, also helpful in case
89 * if we want to have multiple batches at different offsets based on
90 * some criteria. It is not a requirement at the moment but provides
91 * an option for future use.
92 * size: size of the batch in DWORDS
94 struct i915_ctx_workarounds {
95 struct i915_wa_ctx_bb {
98 } indirect_ctx, per_ctx;
102 #define I915_MAX_VCS 4
103 #define I915_MAX_VECS 2
106 * Engine IDs definitions.
107 * Keep instances of the same type engine together.
109 enum intel_engine_id {
116 #define _VCS(n) (VCS0 + (n))
119 #define _VECS(n) (VECS0 + (n))
121 #define INVALID_ENGINE ((enum intel_engine_id)-1)
124 /* A simple estimator for the round-trip latency of an engine */
125 DECLARE_EWMA(_engine_latency, 6, 4)
127 struct st_preempt_hang {
128 struct completion completion;
133 * struct intel_engine_execlists - execlist submission queue and port state
135 * The struct intel_engine_execlists represents the combined logical state of
136 * driver and the hardware state for execlist mode of submission.
138 struct intel_engine_execlists {
140 * @tasklet: softirq tasklet for bottom handler
142 struct tasklet_struct tasklet;
145 * @timer: kick the current context if its timeslice expires
147 struct timer_list timer;
150 * @preempt: reset the current context if it fails to give way
152 struct timer_list preempt;
155 * @default_priolist: priority list for I915_PRIORITY_NORMAL
157 struct i915_priolist default_priolist;
160 * @ccid: identifier for contexts submitted to this engine
165 * @yield: CCID at the time of the last semaphore-wait interrupt.
167 * Instead of leaving a semaphore busy-spinning on an engine, we would
168 * like to switch to another ready context, i.e. yielding the semaphore
174 * @error_interrupt: CS Master EIR
176 * The CS generates an interrupt when it detects an error. We capture
177 * the first error interrupt, record the EIR and schedule the tasklet.
178 * In the tasklet, we process the pending CS events to ensure we have
179 * the guilty request, and then reset the engine.
184 * @no_priolist: priority lists disabled
189 * @submit_reg: gen-specific execlist submission register
190 * set to the ExecList Submission Port (elsp) register pre-Gen11 and to
191 * the ExecList Submission Queue Contents register array for Gen11+
193 u32 __iomem *submit_reg;
196 * @ctrl_reg: the enhanced execlists control register, used to load the
197 * submit queue on the HW and to request preemptions to idle
199 u32 __iomem *ctrl_reg;
201 #define EXECLIST_MAX_PORTS 2
203 * @active: the currently known context executing on HW
205 struct i915_request * const *active;
207 * @inflight: the set of contexts submitted and acknowleged by HW
209 * The set of inflight contexts is managed by reading CS events
210 * from the HW. On a context-switch event (not preemption), we
211 * know the HW has transitioned from port0 to port1, and we
212 * advance our inflight/active tracking accordingly.
214 struct i915_request *inflight[EXECLIST_MAX_PORTS + 1 /* sentinel */];
216 * @pending: the next set of contexts submitted to ELSP
218 * We store the array of contexts that we submit to HW (via ELSP) and
219 * promote them to the inflight array once HW has signaled the
220 * preemption or idle-to-active event.
222 struct i915_request *pending[EXECLIST_MAX_PORTS + 1];
225 * @port_mask: number of execlist ports - 1
227 unsigned int port_mask;
230 * @switch_priority_hint: Second context priority.
232 * We submit multiple contexts to the HW simultaneously and would
233 * like to occasionally switch between them to emulate timeslicing.
234 * To know when timeslicing is suitable, we track the priority of
235 * the context submitted second.
237 int switch_priority_hint;
240 * @queue_priority_hint: Highest pending priority.
242 * When we add requests into the queue, or adjust the priority of
243 * executing requests, we compute the maximum priority of those
244 * pending requests. We can then use this value to determine if
245 * we need to preempt the executing requests to service the queue.
246 * However, since the we may have recorded the priority of an inflight
247 * request we wanted to preempt but since completed, at the time of
248 * dequeuing the priority hint may no longer may match the highest
249 * available request priority.
251 int queue_priority_hint;
254 * @queue: queue of requests, in priority lists
256 struct rb_root_cached queue;
257 struct rb_root_cached virtual;
260 * @csb_write: control register for Context Switch buffer
262 * Note this register may be either mmio or HWSP shadow.
267 * @csb_status: status array for Context Switch buffer
269 * Note these register may be either mmio or HWSP shadow.
274 * @csb_size: context status buffer FIFO size
279 * @csb_head: context status buffer head
283 I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)
286 #define INTEL_ENGINE_CS_MAX_NAME 8
288 struct intel_engine_cs {
289 struct drm_i915_private *i915;
291 struct intel_uncore *uncore;
292 char name[INTEL_ENGINE_CS_MAX_NAME];
294 enum intel_engine_id id;
295 enum intel_engine_id legacy_idx;
300 intel_engine_mask_t mask;
308 u32 uabi_capabilities;
312 unsigned long context_tag;
314 struct rb_node uabi_node;
316 struct intel_sseu sseu;
320 struct list_head requests;
321 struct list_head hold; /* ready requests, but on hold */
324 /* keep a request in reserve for a [pm] barrier under oom */
325 struct i915_request *request_pool;
327 struct llist_head barrier_tasks;
329 struct intel_context *kernel_context; /* pinned */
331 intel_engine_mask_t saturated; /* submitting semaphores too late? */
334 struct delayed_work work;
335 struct i915_request *systole;
338 unsigned long serial;
340 unsigned long wakeref_serial;
341 struct intel_wakeref wakeref;
342 struct drm_i915_gem_object *default_state;
343 void *pinned_default_state;
346 struct intel_ring *ring;
347 struct intel_timeline *timeline;
351 * We track the average duration of the idle pulse on parking the
352 * engine to keep an estimate of the how the fast the engine is
353 * under ideal conditions.
355 struct ewma__engine_latency latency;
357 /* Rather than have every client wait upon all user interrupts,
358 * with the herd waking after every interrupt and each doing the
359 * heavyweight seqno dance, we delegate the task (of being the
360 * bottom-half of the user interrupt) to the first client. After
361 * every interrupt, we wake up one client, who does the heavyweight
362 * coherent seqno read and either goes back to sleep (if incomplete),
363 * or wakes up all the completed clients in parallel, before then
364 * transferring the bottom-half status to the next client in the queue.
366 * Compared to walking the entire list of waiters in a single dedicated
367 * bottom-half, we reduce the latency of the first waiter by avoiding
368 * a context switch, but incur additional coherent seqno reads when
369 * following the chain of request breadcrumbs. Since it is most likely
370 * that we have a single client waiting on each seqno, then reducing
371 * the overhead of waking that client is much preferred.
373 struct intel_breadcrumbs {
375 struct list_head signalers;
377 struct irq_work irq_work; /* for use from inside irq_lock */
379 unsigned int irq_enabled;
384 struct intel_engine_pmu {
386 * @enable: Bitmask of enable sample events on this engine.
388 * Bits correspond to sample event types, for instance
389 * I915_SAMPLE_QUEUED is bit 0 etc.
393 * @enable_count: Reference count for the enabled samplers.
395 * Index number corresponds to @enum drm_i915_pmu_engine_sample.
397 unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT];
399 * @sample: Counter values for sampling events.
401 * Our internal timer stores the current counters in this field.
403 * Index number corresponds to @enum drm_i915_pmu_engine_sample.
405 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_COUNT];
409 * A pool of objects to use as shadow copies of client batch buffers
410 * when the command parser is enabled. Prevents the client from
411 * modifying the batch contents after software parsing.
413 struct intel_engine_pool pool;
415 struct intel_hw_status_page status_page;
416 struct i915_ctx_workarounds wa_ctx;
417 struct i915_wa_list ctx_wa_list;
418 struct i915_wa_list wa_list;
419 struct i915_wa_list whitelist;
421 u32 irq_keep_mask; /* always keep these interrupts */
422 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
423 void (*irq_enable)(struct intel_engine_cs *engine);
424 void (*irq_disable)(struct intel_engine_cs *engine);
426 void (*sanitize)(struct intel_engine_cs *engine);
427 int (*resume)(struct intel_engine_cs *engine);
430 void (*prepare)(struct intel_engine_cs *engine);
432 void (*rewind)(struct intel_engine_cs *engine, bool stalled);
433 void (*cancel)(struct intel_engine_cs *engine);
435 void (*finish)(struct intel_engine_cs *engine);
438 void (*park)(struct intel_engine_cs *engine);
439 void (*unpark)(struct intel_engine_cs *engine);
441 void (*set_default_submission)(struct intel_engine_cs *engine);
443 const struct intel_context_ops *cops;
445 int (*request_alloc)(struct i915_request *rq);
447 int (*emit_flush)(struct i915_request *request, u32 mode);
448 #define EMIT_INVALIDATE BIT(0)
449 #define EMIT_FLUSH BIT(1)
450 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
451 int (*emit_bb_start)(struct i915_request *rq,
452 u64 offset, u32 length,
453 unsigned int dispatch_flags);
454 #define I915_DISPATCH_SECURE BIT(0)
455 #define I915_DISPATCH_PINNED BIT(1)
456 int (*emit_init_breadcrumb)(struct i915_request *rq);
457 u32 *(*emit_fini_breadcrumb)(struct i915_request *rq,
459 unsigned int emit_fini_breadcrumb_dw;
461 /* Pass the request to the hardware queue (e.g. directly into
462 * the legacy ringbuffer or to the end of an execlist).
464 * This is called from an atomic context with irqs disabled; must
467 void (*submit_request)(struct i915_request *rq);
470 * Called on signaling of a SUBMIT_FENCE, passing along the signaling
471 * request down to the bonded pairs.
473 void (*bond_execute)(struct i915_request *rq,
474 struct dma_fence *signal);
477 * Call when the priority on a request has changed and it and its
478 * dependencies may need rescheduling. Note the request itself may
479 * not be ready to run!
481 void (*schedule)(struct i915_request *request,
482 const struct i915_sched_attr *attr);
484 void (*release)(struct intel_engine_cs *engine);
486 struct intel_engine_execlists execlists;
489 * Keep track of completed timelines on this engine for early
490 * retirement with the goal of quickly enabling powersaving as
491 * soon as the engine is idle.
493 struct intel_timeline *retire;
494 struct work_struct retire_work;
496 /* status_notifier: list of callbacks for context-switch changes */
497 struct atomic_notifier_head context_status_notifier;
499 #define I915_ENGINE_USING_CMD_PARSER BIT(0)
500 #define I915_ENGINE_SUPPORTS_STATS BIT(1)
501 #define I915_ENGINE_HAS_PREEMPTION BIT(2)
502 #define I915_ENGINE_HAS_SEMAPHORES BIT(3)
503 #define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
504 #define I915_ENGINE_IS_VIRTUAL BIT(5)
505 #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
506 #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
510 * Table of commands the command parser needs to know about
513 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
516 * Table of registers allowed in commands that read/write registers.
518 const struct drm_i915_reg_table *reg_tables;
522 * Returns the bitmask for the length field of the specified command.
523 * Return 0 for an unrecognized/invalid command.
525 * If the command parser finds an entry for a command in the engine's
526 * cmd_tables, it gets the command's length based on the table entry.
527 * If not, it calls this function to determine the per-engine length
528 * field encoding for the command (i.e. different opcode ranges use
529 * certain bits to encode the command length in the header).
531 u32 (*get_cmd_length_mask)(u32 cmd_header);
535 * @lock: Lock protecting the below fields.
539 * @enabled: Reference count indicating number of listeners.
541 unsigned int enabled;
543 * @active: Number of contexts currently scheduled in.
547 * @enabled_at: Timestamp when busy stats were enabled.
551 * @start: Timestamp of the last idle to active transition.
553 * Idle is defined as active == 0, active is active > 0.
557 * @total: Total time this engine was busy.
559 * Accumulated time not counting the most recent block in cases
560 * where engine is currently busy (active > 0).
566 unsigned long heartbeat_interval_ms;
567 unsigned long max_busywait_duration_ns;
568 unsigned long preempt_timeout_ms;
569 unsigned long stop_timeout_ms;
570 unsigned long timeslice_duration_ms;
575 intel_engine_using_cmd_parser(const struct intel_engine_cs *engine)
577 return engine->flags & I915_ENGINE_USING_CMD_PARSER;
581 intel_engine_requires_cmd_parser(const struct intel_engine_cs *engine)
583 return engine->flags & I915_ENGINE_REQUIRES_CMD_PARSER;
587 intel_engine_supports_stats(const struct intel_engine_cs *engine)
589 return engine->flags & I915_ENGINE_SUPPORTS_STATS;
593 intel_engine_has_preemption(const struct intel_engine_cs *engine)
595 return engine->flags & I915_ENGINE_HAS_PREEMPTION;
599 intel_engine_has_semaphores(const struct intel_engine_cs *engine)
601 return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
605 intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
607 return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
611 intel_engine_is_virtual(const struct intel_engine_cs *engine)
613 return engine->flags & I915_ENGINE_IS_VIRTUAL;
617 intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
619 return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO;
622 #define instdone_has_slice(dev_priv___, sseu___, slice___) \
623 ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
625 #define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
626 (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
627 intel_sseu_has_subslice(sseu__, 0, subslice__))
629 #define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
630 for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
631 (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
632 (slice_) += ((subslice_) == 0)) \
633 for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
634 (instdone_has_subslice(dev_priv_, sseu_, slice_, \
636 #endif /* __INTEL_ENGINE_TYPES_H__ */