drivers/gpu/drm/i915/gt/intel_engine_cs.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_print.h>
  26
  27 #include "gem/i915_gem_context.h"
  28
  29 #include "i915_drv.h"
  30
  31 #include "intel_context.h"
  32 #include "intel_engine.h"
  33 #include "intel_engine_pm.h"
  34 #include "intel_engine_user.h"
  35 #include "intel_gt.h"
  36 #include "intel_gt_requests.h"
  37 #include "intel_gt_pm.h"
  38 #include "intel_lrc.h"
  39 #include "intel_reset.h"
  40 #include "intel_ring.h"
  41
  42 /* Haswell does have the CXT_SIZE register however it does not appear to be
  43  * valid. Now, docs explain in dwords what is in the context object. The full
  44  * size is 70720 bytes, however, the power context and execlist context will
  45  * never be saved (power context is stored elsewhere, and execlists don't work
  46  * on HSW) - so the final size, including the extra state required for the
  47  * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
  48  */
  49 #define HSW_CXT_TOTAL_SIZE              (17 * PAGE_SIZE)
  50
  51 #define DEFAULT_LR_CONTEXT_RENDER_SIZE  (22 * PAGE_SIZE)
  52 #define GEN8_LR_CONTEXT_RENDER_SIZE     (20 * PAGE_SIZE)
  53 #define GEN9_LR_CONTEXT_RENDER_SIZE     (22 * PAGE_SIZE)
  54 #define GEN10_LR_CONTEXT_RENDER_SIZE    (18 * PAGE_SIZE)
  55 #define GEN11_LR_CONTEXT_RENDER_SIZE    (14 * PAGE_SIZE)
  56
  57 #define GEN8_LR_CONTEXT_OTHER_SIZE      ( 2 * PAGE_SIZE)
  58
  59 #define MAX_MMIO_BASES 3
  60 struct engine_info {
  61         unsigned int hw_id;
  62         u8 class;
  63         u8 instance;
  64         /* mmio bases table *must* be sorted in reverse gen order */
  65         struct engine_mmio_base {
  66                 u32 gen : 8;
  67                 u32 base : 24;
  68         } mmio_bases[MAX_MMIO_BASES];
  69 };
  70
  71 static const struct engine_info intel_engines[] = {
  72         [RCS0] = {
  73                 .hw_id = RCS0_HW,
  74                 .class = RENDER_CLASS,
  75                 .instance = 0,
  76                 .mmio_bases = {
  77                         { .gen = 1, .base = RENDER_RING_BASE }
  78                 },
  79         },
  80         [BCS0] = {
  81                 .hw_id = BCS0_HW,
  82                 .class = COPY_ENGINE_CLASS,
  83                 .instance = 0,
  84                 .mmio_bases = {
  85                         { .gen = 6, .base = BLT_RING_BASE }
  86                 },
  87         },
  88         [VCS0] = {
  89                 .hw_id = VCS0_HW,
  90                 .class = VIDEO_DECODE_CLASS,
  91                 .instance = 0,
  92                 .mmio_bases = {
  93                         { .gen = 11, .base = GEN11_BSD_RING_BASE },
  94                         { .gen = 6, .base = GEN6_BSD_RING_BASE },
  95                         { .gen = 4, .base = BSD_RING_BASE }
  96                 },
  97         },
  98         [VCS1] = {
  99                 .hw_id = VCS1_HW,
 100                 .class = VIDEO_DECODE_CLASS,
 101                 .instance = 1,
 102                 .mmio_bases = {
 103                         { .gen = 11, .base = GEN11_BSD2_RING_BASE },
 104                         { .gen = 8, .base = GEN8_BSD2_RING_BASE }
 105                 },
 106         },
 107         [VCS2] = {
 108                 .hw_id = VCS2_HW,
 109                 .class = VIDEO_DECODE_CLASS,
 110                 .instance = 2,
 111                 .mmio_bases = {
 112                         { .gen = 11, .base = GEN11_BSD3_RING_BASE }
 113                 },
 114         },
 115         [VCS3] = {
 116                 .hw_id = VCS3_HW,
 117                 .class = VIDEO_DECODE_CLASS,
 118                 .instance = 3,
 119                 .mmio_bases = {
 120                         { .gen = 11, .base = GEN11_BSD4_RING_BASE }
 121                 },
 122         },
 123         [VECS0] = {
 124                 .hw_id = VECS0_HW,
 125                 .class = VIDEO_ENHANCEMENT_CLASS,
 126                 .instance = 0,
 127                 .mmio_bases = {
 128                         { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
 129                         { .gen = 7, .base = VEBOX_RING_BASE }
 130                 },
 131         },
 132         [VECS1] = {
 133                 .hw_id = VECS1_HW,
 134                 .class = VIDEO_ENHANCEMENT_CLASS,
 135                 .instance = 1,
 136                 .mmio_bases = {
 137                         { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
 138                 },
 139         },
 140 };
 141
 142 /**
 143  * intel_engine_context_size() - return the size of the context for an engine
 144  * @gt: the gt
 145  * @class: engine class
 146  *
 147  * Each engine class may require a different amount of space for a context
 148  * image.
 149  *
 150  * Return: size (in bytes) of an engine class specific context image
 151  *
 152  * Note: this size includes the HWSP, which is part of the context image
 153  * in LRC mode, but does not include the "shared data page" used with
 154  * GuC submission. The caller should account for this if using the GuC.
 155  */
 156 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
 157 {
 158         struct intel_uncore *uncore = gt->uncore;
 159         u32 cxt_size;
 160
 161         BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
 162
 163         switch (class) {
 164         case RENDER_CLASS:
 165                 switch (INTEL_GEN(gt->i915)) {
 166                 default:
 167                         MISSING_CASE(INTEL_GEN(gt->i915));
 168                         return DEFAULT_LR_CONTEXT_RENDER_SIZE;
 169                 case 12:
 170                 case 11:
 171                         return GEN11_LR_CONTEXT_RENDER_SIZE;
 172                 case 10:
 173                         return GEN10_LR_CONTEXT_RENDER_SIZE;
 174                 case 9:
 175                         return GEN9_LR_CONTEXT_RENDER_SIZE;
 176                 case 8:
 177                         return GEN8_LR_CONTEXT_RENDER_SIZE;
 178                 case 7:
 179                         if (IS_HASWELL(gt->i915))
 180                                 return HSW_CXT_TOTAL_SIZE;
 181
 182                         cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
 183                         return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
 184                                         PAGE_SIZE);
 185                 case 6:
 186                         cxt_size = intel_uncore_read(uncore, CXT_SIZE);
 187                         return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
 188                                         PAGE_SIZE);
 189                 case 5:
 190                 case 4:
 191                         /*
 192                          * There is a discrepancy here between the size reported
 193                          * by the register and the size of the context layout
 194                          * in the docs. Both are described as authorative!
 195                          *
 196                          * The discrepancy is on the order of a few cachelines,
 197                          * but the total is under one page (4k), which is our
 198                          * minimum allocation anyway so it should all come
 199                          * out in the wash.
 200                          */
 201                         cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
 202                         drm_dbg(&gt->i915->drm,
 203                                 "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
 204                                 INTEL_GEN(gt->i915), cxt_size * 64,
 205                                 cxt_size - 1);
 206                         return round_up(cxt_size * 64, PAGE_SIZE);
 207                 case 3:
 208                 case 2:
 209                 /* For the special day when i810 gets merged. */
 210                 case 1:
 211                         return 0;
 212                 }
 213                 break;
 214         default:
 215                 MISSING_CASE(class);
 216                 /* fall through */
 217         case VIDEO_DECODE_CLASS:
 218         case VIDEO_ENHANCEMENT_CLASS:
 219         case COPY_ENGINE_CLASS:
 220                 if (INTEL_GEN(gt->i915) < 8)
 221                         return 0;
 222                 return GEN8_LR_CONTEXT_OTHER_SIZE;
 223         }
 224 }
 225
 226 static u32 __engine_mmio_base(struct drm_i915_private *i915,
 227                               const struct engine_mmio_base *bases)
 228 {
 229         int i;
 230
 231         for (i = 0; i < MAX_MMIO_BASES; i++)
 232                 if (INTEL_GEN(i915) >= bases[i].gen)
 233                         break;
 234
 235         GEM_BUG_ON(i == MAX_MMIO_BASES);
 236         GEM_BUG_ON(!bases[i].base);
 237
 238         return bases[i].base;
 239 }
 240
 241 static void __sprint_engine_name(struct intel_engine_cs *engine)
 242 {
 243         /*
 244          * Before we know what the uABI name for this engine will be,
 245          * we still would like to keep track of this engine in the debug logs.
 246          * We throw in a ' here as a reminder that this isn't its final name.
 247          */
 248         GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
 249                              intel_engine_class_repr(engine->class),
 250                              engine->instance) >= sizeof(engine->name));
 251 }
 252
 253 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
 254 {
 255         /*
 256          * Though they added more rings on g4x/ilk, they did not add
 257          * per-engine HWSTAM until gen6.
 258          */
 259         if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
 260                 return;
 261
 262         if (INTEL_GEN(engine->i915) >= 3)
 263                 ENGINE_WRITE(engine, RING_HWSTAM, mask);
 264         else
 265                 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
 266 }
 267
 268 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
 269 {
 270         /* Mask off all writes into the unknown HWSP */
 271         intel_engine_set_hwsp_writemask(engine, ~0u);
 272 }
 273
 274 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
 275 {
 276         const struct engine_info *info = &intel_engines[id];
 277         struct drm_i915_private *i915 = gt->i915;
 278         struct intel_engine_cs *engine;
 279
 280         BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
 281         BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
 282
 283         if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
 284                 return -EINVAL;
 285
 286         if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
 287                 return -EINVAL;
 288
 289         if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
 290                 return -EINVAL;
 291
 292         if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
 293                 return -EINVAL;
 294
 295         engine = kzalloc(sizeof(*engine), GFP_KERNEL);
 296         if (!engine)
 297                 return -ENOMEM;
 298
 299         BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
 300
 301         engine->id = id;
 302         engine->legacy_idx = INVALID_ENGINE;
 303         engine->mask = BIT(id);
 304         engine->i915 = i915;
 305         engine->gt = gt;
 306         engine->uncore = gt->uncore;
 307         engine->hw_id = engine->guc_id = info->hw_id;
 308         engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
 309
 310         engine->class = info->class;
 311         engine->instance = info->instance;
 312         __sprint_engine_name(engine);
 313
 314         engine->props.heartbeat_interval_ms =
 315                 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
 316         engine->props.max_busywait_duration_ns =
 317                 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
 318         engine->props.preempt_timeout_ms =
 319                 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
 320         engine->props.stop_timeout_ms =
 321                 CONFIG_DRM_I915_STOP_TIMEOUT;
 322         engine->props.timeslice_duration_ms =
 323                 CONFIG_DRM_I915_TIMESLICE_DURATION;
 324
 325         /* Override to uninterruptible for OpenCL workloads. */
 326         if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
 327                 engine->props.preempt_timeout_ms = 0;
 328
 329         engine->defaults = engine->props; /* never to change again */
 330
 331         engine->context_size = intel_engine_context_size(gt, engine->class);
 332         if (WARN_ON(engine->context_size > BIT(20)))
 333                 engine->context_size = 0;
 334         if (engine->context_size)
 335                 DRIVER_CAPS(i915)->has_logical_contexts = true;
 336
 337         /* Nothing to do here, execute in order of dependencies */
 338         engine->schedule = NULL;
 339
 340         ewma__engine_latency_init(&engine->latency);
 341         seqlock_init(&engine->stats.lock);
 342
 343         ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
 344
 345         /* Scrub mmio state on takeover */
 346         intel_engine_sanitize_mmio(engine);
 347
 348         gt->engine_class[info->class][info->instance] = engine;
 349         gt->engine[id] = engine;
 350
 351         return 0;
 352 }
 353
 354 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
 355 {
 356         struct drm_i915_private *i915 = engine->i915;
 357
 358         if (engine->class == VIDEO_DECODE_CLASS) {
 359                 /*
 360                  * HEVC support is present on first engine instance
 361                  * before Gen11 and on all instances afterwards.
 362                  */
 363                 if (INTEL_GEN(i915) >= 11 ||
 364                     (INTEL_GEN(i915) >= 9 && engine->instance == 0))
 365                         engine->uabi_capabilities |=
 366                                 I915_VIDEO_CLASS_CAPABILITY_HEVC;
 367
 368                 /*
 369                  * SFC block is present only on even logical engine
 370                  * instances.
 371                  */
 372                 if ((INTEL_GEN(i915) >= 11 &&
 373                      engine->gt->info.vdbox_sfc_access & engine->mask) ||
 374                     (INTEL_GEN(i915) >= 9 && engine->instance == 0))
 375                         engine->uabi_capabilities |=
 376                                 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 377         } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
 378                 if (INTEL_GEN(i915) >= 9)
 379                         engine->uabi_capabilities |=
 380                                 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 381         }
 382 }
 383
 384 static void intel_setup_engine_capabilities(struct intel_gt *gt)
 385 {
 386         struct intel_engine_cs *engine;
 387         enum intel_engine_id id;
 388
 389         for_each_engine(engine, gt, id)
 390                 __setup_engine_capabilities(engine);
 391 }
 392
 393 /**
 394  * intel_engines_release() - free the resources allocated for Command Streamers
 395  * @gt: pointer to struct intel_gt
 396  */
 397 void intel_engines_release(struct intel_gt *gt)
 398 {
 399         struct intel_engine_cs *engine;
 400         enum intel_engine_id id;
 401
 402         /*
 403          * Before we release the resources held by engine, we must be certain
 404          * that the HW is no longer accessing them -- having the GPU scribble
 405          * to or read from a page being used for something else causes no end
 406          * of fun.
 407          *
 408          * The GPU should be reset by this point, but assume the worst just
 409          * in case we aborted before completely initialising the engines.
 410          */
 411         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 412         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 413                 __intel_gt_reset(gt, ALL_ENGINES);
 414
 415         /* Decouple the backend; but keep the layout for late GPU resets */
 416         for_each_engine(engine, gt, id) {
 417                 if (!engine->release)
 418                         continue;
 419
 420                 intel_wakeref_wait_for_idle(&engine->wakeref);
 421                 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
 422
 423                 engine->release(engine);
 424                 engine->release = NULL;
 425
 426                 memset(&engine->reset, 0, sizeof(engine->reset));
 427         }
 428 }
 429
 430 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
 431 {
 432         if (!engine->request_pool)
 433                 return;
 434
 435         kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
 436 }
 437
 438 void intel_engines_free(struct intel_gt *gt)
 439 {
 440         struct intel_engine_cs *engine;
 441         enum intel_engine_id id;
 442
 443         /* Free the requests! dma-resv keeps fences around for an eternity */
 444         rcu_barrier();
 445
 446         for_each_engine(engine, gt, id) {
 447                 intel_engine_free_request_pool(engine);
 448                 kfree(engine);
 449                 gt->engine[id] = NULL;
 450         }
 451 }
 452
 453 /*
 454  * Determine which engines are fused off in our particular hardware.
 455  * Note that we have a catch-22 situation where we need to be able to access
 456  * the blitter forcewake domain to read the engine fuses, but at the same time
 457  * we need to know which engines are available on the system to know which
 458  * forcewake domains are present. We solve this by intializing the forcewake
 459  * domains based on the full engine mask in the platform capabilities before
 460  * calling this function and pruning the domains for fused-off engines
 461  * afterwards.
 462  */
 463 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 464 {
 465         struct drm_i915_private *i915 = gt->i915;
 466         struct intel_gt_info *info = &gt->info;
 467         struct intel_uncore *uncore = gt->uncore;
 468         unsigned int logical_vdbox = 0;
 469         unsigned int i;
 470         u32 media_fuse;
 471         u16 vdbox_mask;
 472         u16 vebox_mask;
 473
 474         info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
 475
 476         if (INTEL_GEN(i915) < 11)
 477                 return info->engine_mask;
 478
 479         media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
 480
 481         vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
 482         vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
 483                       GEN11_GT_VEBOX_DISABLE_SHIFT;
 484
 485         for (i = 0; i < I915_MAX_VCS; i++) {
 486                 if (!HAS_ENGINE(gt, _VCS(i))) {
 487                         vdbox_mask &= ~BIT(i);
 488                         continue;
 489                 }
 490
 491                 if (!(BIT(i) & vdbox_mask)) {
 492                         info->engine_mask &= ~BIT(_VCS(i));
 493                         drm_dbg(&i915->drm, "vcs%u fused off\n", i);
 494                         continue;
 495                 }
 496
 497                 /*
 498                  * In Gen11, only even numbered logical VDBOXes are
 499                  * hooked up to an SFC (Scaler & Format Converter) unit.
 500                  * In TGL each VDBOX has access to an SFC.
 501                  */
 502                 if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
 503                         gt->info.vdbox_sfc_access |= BIT(i);
 504         }
 505         drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
 506                 vdbox_mask, VDBOX_MASK(gt));
 507         GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
 508
 509         for (i = 0; i < I915_MAX_VECS; i++) {
 510                 if (!HAS_ENGINE(gt, _VECS(i))) {
 511                         vebox_mask &= ~BIT(i);
 512                         continue;
 513                 }
 514
 515                 if (!(BIT(i) & vebox_mask)) {
 516                         info->engine_mask &= ~BIT(_VECS(i));
 517                         drm_dbg(&i915->drm, "vecs%u fused off\n", i);
 518                 }
 519         }
 520         drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
 521                 vebox_mask, VEBOX_MASK(gt));
 522         GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
 523
 524         return info->engine_mask;
 525 }
 526
 527 /**
 528  * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
 529  * @gt: pointer to struct intel_gt
 530  *
 531  * Return: non-zero if the initialization failed.
 532  */
 533 int intel_engines_init_mmio(struct intel_gt *gt)
 534 {
 535         struct drm_i915_private *i915 = gt->i915;
 536         const unsigned int engine_mask = init_engine_mask(gt);
 537         unsigned int mask = 0;
 538         unsigned int i;
 539         int err;
 540
 541         drm_WARN_ON(&i915->drm, engine_mask == 0);
 542         drm_WARN_ON(&i915->drm, engine_mask &
 543                     GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
 544
 545         if (i915_inject_probe_failure(i915))
 546                 return -ENODEV;
 547
 548         for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
 549                 if (!HAS_ENGINE(gt, i))
 550                         continue;
 551
 552                 err = intel_engine_setup(gt, i);
 553                 if (err)
 554                         goto cleanup;
 555
 556                 mask |= BIT(i);
 557         }
 558
 559         /*
 560          * Catch failures to update intel_engines table when the new engines
 561          * are added to the driver by a warning and disabling the forgotten
 562          * engines.
 563          */
 564         if (drm_WARN_ON(&i915->drm, mask != engine_mask))
 565                 gt->info.engine_mask = mask;
 566
 567         gt->info.num_engines = hweight32(mask);
 568
 569         intel_gt_check_and_clear_faults(gt);
 570
 571         intel_setup_engine_capabilities(gt);
 572
 573         intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
 574
 575         return 0;
 576
 577 cleanup:
 578         intel_engines_free(gt);
 579         return err;
 580 }
 581
 582 void intel_engine_init_execlists(struct intel_engine_cs *engine)
 583 {
 584         struct intel_engine_execlists * const execlists = &engine->execlists;
 585
 586         execlists->port_mask = 1;
 587         GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
 588         GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
 589
 590         memset(execlists->pending, 0, sizeof(execlists->pending));
 591         execlists->active =
 592                 memset(execlists->inflight, 0, sizeof(execlists->inflight));
 593
 594         execlists->queue_priority_hint = INT_MIN;
 595         execlists->queue = RB_ROOT_CACHED;
 596 }
 597
 598 static void cleanup_status_page(struct intel_engine_cs *engine)
 599 {
 600         struct i915_vma *vma;
 601
 602         /* Prevent writes into HWSP after returning the page to the system */
 603         intel_engine_set_hwsp_writemask(engine, ~0u);
 604
 605         vma = fetch_and_zero(&engine->status_page.vma);
 606         if (!vma)
 607                 return;
 608
 609         if (!HWS_NEEDS_PHYSICAL(engine->i915))
 610                 i915_vma_unpin(vma);
 611
 612         i915_gem_object_unpin_map(vma->obj);
 613         i915_gem_object_put(vma->obj);
 614 }
 615
 616 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
 617                                 struct i915_vma *vma)
 618 {
 619         unsigned int flags;
 620
 621         if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
 622                 /*
 623                  * On g33, we cannot place HWS above 256MiB, so
 624                  * restrict its pinning to the low mappable arena.
 625                  * Though this restriction is not documented for
 626                  * gen4, gen5, or byt, they also behave similarly
 627                  * and hang if the HWS is placed at the top of the
 628                  * GTT. To generalise, it appears that all !llc
 629                  * platforms have issues with us placing the HWS
 630                  * above the mappable region (even though we never
 631                  * actually map it).
 632                  */
 633                 flags = PIN_MAPPABLE;
 634         else
 635                 flags = PIN_HIGH;
 636
 637         return i915_ggtt_pin(vma, 0, flags);
 638 }
 639
 640 static int init_status_page(struct intel_engine_cs *engine)
 641 {
 642         struct drm_i915_gem_object *obj;
 643         struct i915_vma *vma;
 644         void *vaddr;
 645         int ret;
 646
 647         /*
 648          * Though the HWS register does support 36bit addresses, historically
 649          * we have had hangs and corruption reported due to wild writes if
 650          * the HWS is placed above 4G. We only allow objects to be allocated
 651          * in GFP_DMA32 for i965, and no earlier physical address users had
 652          * access to more than 4G.
 653          */
 654         obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
 655         if (IS_ERR(obj)) {
 656                 drm_err(&engine->i915->drm,
 657                         "Failed to allocate status page\n");
 658                 return PTR_ERR(obj);
 659         }
 660
 661         i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
 662
 663         vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
 664         if (IS_ERR(vma)) {
 665                 ret = PTR_ERR(vma);
 666                 goto err;
 667         }
 668
 669         vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
 670         if (IS_ERR(vaddr)) {
 671                 ret = PTR_ERR(vaddr);
 672                 goto err;
 673         }
 674
 675         engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
 676         engine->status_page.vma = vma;
 677
 678         if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
 679                 ret = pin_ggtt_status_page(engine, vma);
 680                 if (ret)
 681                         goto err_unpin;
 682         }
 683
 684         return 0;
 685
 686 err_unpin:
 687         i915_gem_object_unpin_map(obj);
 688 err:
 689         i915_gem_object_put(obj);
 690         return ret;
 691 }
 692
 693 static int engine_setup_common(struct intel_engine_cs *engine)
 694 {
 695         int err;
 696
 697         init_llist_head(&engine->barrier_tasks);
 698
 699         err = init_status_page(engine);
 700         if (err)
 701                 return err;
 702
 703         intel_engine_init_active(engine, ENGINE_PHYSICAL);
 704         intel_engine_init_breadcrumbs(engine);
 705         intel_engine_init_execlists(engine);
 706         intel_engine_init_cmd_parser(engine);
 707         intel_engine_init__pm(engine);
 708         intel_engine_init_retire(engine);
 709
 710         /* Use the whole device by default */
 711         engine->sseu =
 712                 intel_sseu_from_device_info(&engine->gt->info.sseu);
 713
 714         intel_engine_init_workarounds(engine);
 715         intel_engine_init_whitelist(engine);
 716         intel_engine_init_ctx_wa(engine);
 717
 718         return 0;
 719 }
 720
 721 struct measure_breadcrumb {
 722         struct i915_request rq;
 723         struct intel_ring ring;
 724         u32 cs[2048];
 725 };
 726
 727 static int measure_breadcrumb_dw(struct intel_context *ce)
 728 {
 729         struct intel_engine_cs *engine = ce->engine;
 730         struct measure_breadcrumb *frame;
 731         int dw;
 732
 733         GEM_BUG_ON(!engine->gt->scratch);
 734
 735         frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 736         if (!frame)
 737                 return -ENOMEM;
 738
 739         frame->rq.engine = engine;
 740         frame->rq.context = ce;
 741         rcu_assign_pointer(frame->rq.timeline, ce->timeline);
 742
 743         frame->ring.vaddr = frame->cs;
 744         frame->ring.size = sizeof(frame->cs);
 745         frame->ring.wrap =
 746                 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
 747         frame->ring.effective_size = frame->ring.size;
 748         intel_ring_update_space(&frame->ring);
 749         frame->rq.ring = &frame->ring;
 750
 751         mutex_lock(&ce->timeline->mutex);
 752         spin_lock_irq(&engine->active.lock);
 753
 754         dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
 755
 756         spin_unlock_irq(&engine->active.lock);
 757         mutex_unlock(&ce->timeline->mutex);
 758
 759         GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
 760
 761         kfree(frame);
 762         return dw;
 763 }
 764
 765 void
 766 intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
 767 {
 768         INIT_LIST_HEAD(&engine->active.requests);
 769         INIT_LIST_HEAD(&engine->active.hold);
 770
 771         spin_lock_init(&engine->active.lock);
 772         lockdep_set_subclass(&engine->active.lock, subclass);
 773
 774         /*
 775          * Due to an interesting quirk in lockdep's internal debug tracking,
 776          * after setting a subclass we must ensure the lock is used. Otherwise,
 777          * nr_unused_locks is incremented once too often.
 778          */
 779 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 780         local_irq_disable();
 781         lock_map_acquire(&engine->active.lock.dep_map);
 782         lock_map_release(&engine->active.lock.dep_map);
 783         local_irq_enable();
 784 #endif
 785 }
 786
 787 static struct intel_context *
 788 create_kernel_context(struct intel_engine_cs *engine)
 789 {
 790         static struct lock_class_key kernel;
 791         struct intel_context *ce;
 792         int err;
 793
 794         ce = intel_context_create(engine);
 795         if (IS_ERR(ce))
 796                 return ce;
 797
 798         __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
 799
 800         err = intel_context_pin(ce); /* perma-pin so it is always available */
 801         if (err) {
 802                 intel_context_put(ce);
 803                 return ERR_PTR(err);
 804         }
 805
 806         /*
 807          * Give our perma-pinned kernel timelines a separate lockdep class,
 808          * so that we can use them from within the normal user timelines
 809          * should we need to inject GPU operations during their request
 810          * construction.
 811          */
 812         lockdep_set_class(&ce->timeline->mutex, &kernel);
 813
 814         return ce;
 815 }
 816
 817 /**
 818  * intel_engines_init_common - initialize cengine state which might require hw access
 819  * @engine: Engine to initialize.
 820  *
 821  * Initializes @engine@ structure members shared between legacy and execlists
 822  * submission modes which do require hardware access.
 823  *
 824  * Typcally done at later stages of submission mode specific engine setup.
 825  *
 826  * Returns zero on success or an error code on failure.
 827  */
 828 static int engine_init_common(struct intel_engine_cs *engine)
 829 {
 830         struct intel_context *ce;
 831         int ret;
 832
 833         engine->set_default_submission(engine);
 834
 835         /*
 836          * We may need to do things with the shrinker which
 837          * require us to immediately switch back to the default
 838          * context. This can cause a problem as pinning the
 839          * default context also requires GTT space which may not
 840          * be available. To avoid this we always pin the default
 841          * context.
 842          */
 843         ce = create_kernel_context(engine);
 844         if (IS_ERR(ce))
 845                 return PTR_ERR(ce);
 846
 847         ret = measure_breadcrumb_dw(ce);
 848         if (ret < 0)
 849                 goto err_context;
 850
 851         engine->emit_fini_breadcrumb_dw = ret;
 852         engine->kernel_context = ce;
 853
 854         return 0;
 855
 856 err_context:
 857         intel_context_put(ce);
 858         return ret;
 859 }
 860
 861 int intel_engines_init(struct intel_gt *gt)
 862 {
 863         int (*setup)(struct intel_engine_cs *engine);
 864         struct intel_engine_cs *engine;
 865         enum intel_engine_id id;
 866         int err;
 867
 868         if (HAS_EXECLISTS(gt->i915))
 869                 setup = intel_execlists_submission_setup;
 870         else
 871                 setup = intel_ring_submission_setup;
 872
 873         for_each_engine(engine, gt, id) {
 874                 err = engine_setup_common(engine);
 875                 if (err)
 876                         return err;
 877
 878                 err = setup(engine);
 879                 if (err)
 880                         return err;
 881
 882                 err = engine_init_common(engine);
 883                 if (err)
 884                         return err;
 885
 886                 intel_engine_add_user(engine);
 887         }
 888
 889         return 0;
 890 }
 891
 892 /**
 893  * intel_engines_cleanup_common - cleans up the engine state created by
 894  *                                the common initiailizers.
 895  * @engine: Engine to cleanup.
 896  *
 897  * This cleans up everything created by the common helpers.
 898  */
 899 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 900 {
 901         GEM_BUG_ON(!list_empty(&engine->active.requests));
 902         tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
 903
 904         cleanup_status_page(engine);
 905
 906         intel_engine_fini_retire(engine);
 907         intel_engine_fini_breadcrumbs(engine);
 908         intel_engine_cleanup_cmd_parser(engine);
 909
 910         if (engine->default_state)
 911                 fput(engine->default_state);
 912
 913         if (engine->kernel_context) {
 914                 intel_context_unpin(engine->kernel_context);
 915                 intel_context_put(engine->kernel_context);
 916         }
 917         GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
 918
 919         intel_wa_list_free(&engine->ctx_wa_list);
 920         intel_wa_list_free(&engine->wa_list);
 921         intel_wa_list_free(&engine->whitelist);
 922 }
 923
 924 /**
 925  * intel_engine_resume - re-initializes the HW state of the engine
 926  * @engine: Engine to resume.
 927  *
 928  * Returns zero on success or an error code on failure.
 929  */
 930 int intel_engine_resume(struct intel_engine_cs *engine)
 931 {
 932         intel_engine_apply_workarounds(engine);
 933         intel_engine_apply_whitelist(engine);
 934
 935         return engine->resume(engine);
 936 }
 937
 938 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
 939 {
 940         struct drm_i915_private *i915 = engine->i915;
 941
 942         u64 acthd;
 943
 944         if (INTEL_GEN(i915) >= 8)
 945                 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
 946         else if (INTEL_GEN(i915) >= 4)
 947                 acthd = ENGINE_READ(engine, RING_ACTHD);
 948         else
 949                 acthd = ENGINE_READ(engine, ACTHD);
 950
 951         return acthd;
 952 }
 953
 954 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
 955 {
 956         u64 bbaddr;
 957
 958         if (INTEL_GEN(engine->i915) >= 8)
 959                 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
 960         else
 961                 bbaddr = ENGINE_READ(engine, RING_BBADDR);
 962
 963         return bbaddr;
 964 }
 965
 966 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
 967 {
 968         if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
 969                 return 0;
 970
 971         /*
 972          * If we are doing a normal GPU reset, we can take our time and allow
 973          * the engine to quiesce. We've stopped submission to the engine, and
 974          * if we wait long enough an innocent context should complete and
 975          * leave the engine idle. So they should not be caught unaware by
 976          * the forthcoming GPU reset (which usually follows the stop_cs)!
 977          */
 978         return READ_ONCE(engine->props.stop_timeout_ms);
 979 }
 980
 981 int intel_engine_stop_cs(struct intel_engine_cs *engine)
 982 {
 983         struct intel_uncore *uncore = engine->uncore;
 984         const u32 base = engine->mmio_base;
 985         const i915_reg_t mode = RING_MI_MODE(base);
 986         int err;
 987
 988         if (INTEL_GEN(engine->i915) < 3)
 989                 return -ENODEV;
 990
 991         ENGINE_TRACE(engine, "\n");
 992
 993         intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
 994
 995         err = 0;
 996         if (__intel_wait_for_register_fw(uncore,
 997                                          mode, MODE_IDLE, MODE_IDLE,
 998                                          1000, stop_timeout(engine),
 999                                          NULL)) {
1000                 ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n");
1001                 err = -ETIMEDOUT;
1002         }
1003
1004         /* A final mmio read to let GPU writes be hopefully flushed to memory */
1005         intel_uncore_posting_read_fw(uncore, mode);
1006
1007         return err;
1008 }
1009
1010 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1011 {
1012         ENGINE_TRACE(engine, "\n");
1013
1014         ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1015 }
1016
1017 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1018 {
1019         switch (type) {
1020         case I915_CACHE_NONE: return " uncached";
1021         case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1022         case I915_CACHE_L3_LLC: return " L3+LLC";
1023         case I915_CACHE_WT: return " WT";
1024         default: return "";
1025         }
1026 }
1027
1028 static u32
1029 read_subslice_reg(const struct intel_engine_cs *engine,
1030                   int slice, int subslice, i915_reg_t reg)
1031 {
1032         struct drm_i915_private *i915 = engine->i915;
1033         struct intel_uncore *uncore = engine->uncore;
1034         u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
1035         enum forcewake_domains fw_domains;
1036
1037         if (INTEL_GEN(i915) >= 11) {
1038                 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1039                 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1040         } else {
1041                 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1042                 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1043         }
1044
1045         fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
1046                                                     FW_REG_READ);
1047         fw_domains |= intel_uncore_forcewake_for_reg(uncore,
1048                                                      GEN8_MCR_SELECTOR,
1049                                                      FW_REG_READ | FW_REG_WRITE);
1050
1051         spin_lock_irq(&uncore->lock);
1052         intel_uncore_forcewake_get__locked(uncore, fw_domains);
1053
1054         old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
1055
1056         mcr &= ~mcr_mask;
1057         mcr |= mcr_ss;
1058         intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1059
1060         val = intel_uncore_read_fw(uncore, reg);
1061
1062         mcr &= ~mcr_mask;
1063         mcr |= old_mcr & mcr_mask;
1064
1065         intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1066
1067         intel_uncore_forcewake_put__locked(uncore, fw_domains);
1068         spin_unlock_irq(&uncore->lock);
1069
1070         return val;
1071 }
1072
1073 /* NB: please notice the memset */
1074 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1075                                struct intel_instdone *instdone)
1076 {
1077         struct drm_i915_private *i915 = engine->i915;
1078         const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
1079         struct intel_uncore *uncore = engine->uncore;
1080         u32 mmio_base = engine->mmio_base;
1081         int slice;
1082         int subslice;
1083
1084         memset(instdone, 0, sizeof(*instdone));
1085
1086         switch (INTEL_GEN(i915)) {
1087         default:
1088                 instdone->instdone =
1089                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1090
1091                 if (engine->id != RCS0)
1092                         break;
1093
1094                 instdone->slice_common =
1095                         intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1096                 if (INTEL_GEN(i915) >= 12) {
1097                         instdone->slice_common_extra[0] =
1098                                 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1099                         instdone->slice_common_extra[1] =
1100                                 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1101                 }
1102                 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
1103                         instdone->sampler[slice][subslice] =
1104                                 read_subslice_reg(engine, slice, subslice,
1105                                                   GEN7_SAMPLER_INSTDONE);
1106                         instdone->row[slice][subslice] =
1107                                 read_subslice_reg(engine, slice, subslice,
1108                                                   GEN7_ROW_INSTDONE);
1109                 }
1110                 break;
1111         case 7:
1112                 instdone->instdone =
1113                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1114
1115                 if (engine->id != RCS0)
1116                         break;
1117
1118                 instdone->slice_common =
1119                         intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1120                 instdone->sampler[0][0] =
1121                         intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1122                 instdone->row[0][0] =
1123                         intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1124
1125                 break;
1126         case 6:
1127         case 5:
1128         case 4:
1129                 instdone->instdone =
1130                         intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1131                 if (engine->id == RCS0)
1132                         /* HACK: Using the wrong struct member */
1133                         instdone->slice_common =
1134                                 intel_uncore_read(uncore, GEN4_INSTDONE1);
1135                 break;
1136         case 3:
1137         case 2:
1138                 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1139                 break;
1140         }
1141 }
1142
1143 static bool ring_is_idle(struct intel_engine_cs *engine)
1144 {
1145         bool idle = true;
1146
1147         if (I915_SELFTEST_ONLY(!engine->mmio_base))
1148                 return true;
1149
1150         if (!intel_engine_pm_get_if_awake(engine))
1151                 return true;
1152
1153         /* First check that no commands are left in the ring */
1154         if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1155             (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1156                 idle = false;
1157
1158         /* No bit for gen2, so assume the CS parser is idle */
1159         if (INTEL_GEN(engine->i915) > 2 &&
1160             !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1161                 idle = false;
1162
1163         intel_engine_pm_put(engine);
1164
1165         return idle;
1166 }
1167
1168 void intel_engine_flush_submission(struct intel_engine_cs *engine)
1169 {
1170         struct tasklet_struct *t = &engine->execlists.tasklet;
1171
1172         if (!t->func)
1173                 return;
1174
1175         /* Synchronise and wait for the tasklet on another CPU */
1176         tasklet_kill(t);
1177
1178         /* Having cancelled the tasklet, ensure that is run */
1179         local_bh_disable();
1180         if (tasklet_trylock(t)) {
1181                 /* Must wait for any GPU reset in progress. */
1182                 if (__tasklet_is_enabled(t))
1183                         t->func(t->data);
1184                 tasklet_unlock(t);
1185         }
1186         local_bh_enable();
1187 }
1188
1189 /**
1190  * intel_engine_is_idle() - Report if the engine has finished process all work
1191  * @engine: the intel_engine_cs
1192  *
1193  * Return true if there are no requests pending, nothing left to be submitted
1194  * to hardware, and that the engine is idle.
1195  */
1196 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1197 {
1198         /* More white lies, if wedged, hw state is inconsistent */
1199         if (intel_gt_is_wedged(engine->gt))
1200                 return true;
1201
1202         if (!intel_engine_pm_is_awake(engine))
1203                 return true;
1204
1205         /* Waiting to drain ELSP? */
1206         if (execlists_active(&engine->execlists)) {
1207                 synchronize_hardirq(engine->i915->drm.pdev->irq);
1208
1209                 intel_engine_flush_submission(engine);
1210
1211                 if (execlists_active(&engine->execlists))
1212                         return false;
1213         }
1214
1215         /* ELSP is empty, but there are ready requests? E.g. after reset */
1216         if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
1217                 return false;
1218
1219         /* Ring stopped? */
1220         return ring_is_idle(engine);
1221 }
1222
1223 bool intel_engines_are_idle(struct intel_gt *gt)
1224 {
1225         struct intel_engine_cs *engine;
1226         enum intel_engine_id id;
1227
1228         /*
1229          * If the driver is wedged, HW state may be very inconsistent and
1230          * report that it is still busy, even though we have stopped using it.
1231          */
1232         if (intel_gt_is_wedged(gt))
1233                 return true;
1234
1235         /* Already parked (and passed an idleness test); must still be idle */
1236         if (!READ_ONCE(gt->awake))
1237                 return true;
1238
1239         for_each_engine(engine, gt, id) {
1240                 if (!intel_engine_is_idle(engine))
1241                         return false;
1242         }
1243
1244         return true;
1245 }
1246
1247 void intel_engines_reset_default_submission(struct intel_gt *gt)
1248 {
1249         struct intel_engine_cs *engine;
1250         enum intel_engine_id id;
1251
1252         for_each_engine(engine, gt, id)
1253                 engine->set_default_submission(engine);
1254 }
1255
1256 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1257 {
1258         switch (INTEL_GEN(engine->i915)) {
1259         case 2:
1260                 return false; /* uses physical not virtual addresses */
1261         case 3:
1262                 /* maybe only uses physical not virtual addresses */
1263                 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1264         case 4:
1265                 return !IS_I965G(engine->i915); /* who knows! */
1266         case 6:
1267                 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1268         default:
1269                 return true;
1270         }
1271 }
1272
1273 static int print_sched_attr(const struct i915_sched_attr *attr,
1274                             char *buf, int x, int len)
1275 {
1276         if (attr->priority == I915_PRIORITY_INVALID)
1277                 return x;
1278
1279         x += snprintf(buf + x, len - x,
1280                       " prio=%d", attr->priority);
1281
1282         return x;
1283 }
1284
1285 static void print_request(struct drm_printer *m,
1286                           struct i915_request *rq,
1287                           const char *prefix)
1288 {
1289         const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
1290         char buf[80] = "";
1291         int x = 0;
1292
1293         x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
1294
1295         drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n",
1296                    prefix,
1297                    rq->fence.context, rq->fence.seqno,
1298                    i915_request_completed(rq) ? "!" :
1299                    i915_request_started(rq) ? "*" :
1300                    "",
1301                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1302                             &rq->fence.flags) ? "+" :
1303                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
1304                             &rq->fence.flags) ? "-" :
1305                    "",
1306                    buf,
1307                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
1308                    name);
1309 }
1310
1311 static struct intel_timeline *get_timeline(struct i915_request *rq)
1312 {
1313         struct intel_timeline *tl;
1314
1315         /*
1316          * Even though we are holding the engine->active.lock here, there
1317          * is no control over the submission queue per-se and we are
1318          * inspecting the active state at a random point in time, with an
1319          * unknown queue. Play safe and make sure the timeline remains valid.
1320          * (Only being used for pretty printing, one extra kref shouldn't
1321          * cause a camel stampede!)
1322          */
1323         rcu_read_lock();
1324         tl = rcu_dereference(rq->timeline);
1325         if (!kref_get_unless_zero(&tl->kref))
1326                 tl = NULL;
1327         rcu_read_unlock();
1328
1329         return tl;
1330 }
1331
1332 static int print_ring(char *buf, int sz, struct i915_request *rq)
1333 {
1334         int len = 0;
1335
1336         if (!i915_request_signaled(rq)) {
1337                 struct intel_timeline *tl = get_timeline(rq);
1338
1339                 len = scnprintf(buf, sz,
1340                                 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1341                                 i915_ggtt_offset(rq->ring->vma),
1342                                 tl ? tl->hwsp_offset : 0,
1343                                 hwsp_seqno(rq),
1344                                 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1345                                                       1000 * 1000));
1346
1347                 if (tl)
1348                         intel_timeline_put(tl);
1349         }
1350
1351         return len;
1352 }
1353
1354 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1355 {
1356         const size_t rowsize = 8 * sizeof(u32);
1357         const void *prev = NULL;
1358         bool skip = false;
1359         size_t pos;
1360
1361         for (pos = 0; pos < len; pos += rowsize) {
1362                 char line[128];
1363
1364                 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1365                         if (!skip) {
1366                                 drm_printf(m, "*\n");
1367                                 skip = true;
1368                         }
1369                         continue;
1370                 }
1371
1372                 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1373                                                 rowsize, sizeof(u32),
1374                                                 line, sizeof(line),
1375                                                 false) >= sizeof(line));
1376                 drm_printf(m, "[%04zx] %s\n", pos, line);
1377
1378                 prev = buf + pos;
1379                 skip = false;
1380         }
1381 }
1382
1383 static const char *repr_timer(const struct timer_list *t)
1384 {
1385         if (!READ_ONCE(t->expires))
1386                 return "inactive";
1387
1388         if (timer_pending(t))
1389                 return "active";
1390
1391         return "expired";
1392 }
1393
1394 static void intel_engine_print_registers(struct intel_engine_cs *engine,
1395                                          struct drm_printer *m)
1396 {
1397         struct drm_i915_private *dev_priv = engine->i915;
1398         struct intel_engine_execlists * const execlists = &engine->execlists;
1399         u64 addr;
1400
1401         if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
1402                 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1403         if (HAS_EXECLISTS(dev_priv)) {
1404                 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1405                            ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1406                 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1407                            ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1408         }
1409         drm_printf(m, "\tRING_START: 0x%08x\n",
1410                    ENGINE_READ(engine, RING_START));
1411         drm_printf(m, "\tRING_HEAD:  0x%08x\n",
1412                    ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1413         drm_printf(m, "\tRING_TAIL:  0x%08x\n",
1414                    ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1415         drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
1416                    ENGINE_READ(engine, RING_CTL),
1417                    ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1418         if (INTEL_GEN(engine->i915) > 2) {
1419                 drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
1420                            ENGINE_READ(engine, RING_MI_MODE),
1421                            ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1422         }
1423
1424         if (INTEL_GEN(dev_priv) >= 6) {
1425                 drm_printf(m, "\tRING_IMR:   0x%08x\n",
1426                            ENGINE_READ(engine, RING_IMR));
1427                 drm_printf(m, "\tRING_ESR:   0x%08x\n",
1428                            ENGINE_READ(engine, RING_ESR));
1429                 drm_printf(m, "\tRING_EMR:   0x%08x\n",
1430                            ENGINE_READ(engine, RING_EMR));
1431                 drm_printf(m, "\tRING_EIR:   0x%08x\n",
1432                            ENGINE_READ(engine, RING_EIR));
1433         }
1434
1435         addr = intel_engine_get_active_head(engine);
1436         drm_printf(m, "\tACTHD:  0x%08x_%08x\n",
1437                    upper_32_bits(addr), lower_32_bits(addr));
1438         addr = intel_engine_get_last_batch_head(engine);
1439         drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1440                    upper_32_bits(addr), lower_32_bits(addr));
1441         if (INTEL_GEN(dev_priv) >= 8)
1442                 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1443         else if (INTEL_GEN(dev_priv) >= 4)
1444                 addr = ENGINE_READ(engine, RING_DMA_FADD);
1445         else
1446                 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1447         drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1448                    upper_32_bits(addr), lower_32_bits(addr));
1449         if (INTEL_GEN(dev_priv) >= 4) {
1450                 drm_printf(m, "\tIPEIR: 0x%08x\n",
1451                            ENGINE_READ(engine, RING_IPEIR));
1452                 drm_printf(m, "\tIPEHR: 0x%08x\n",
1453                            ENGINE_READ(engine, RING_IPEHR));
1454         } else {
1455                 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1456                 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1457         }
1458
1459         if (HAS_EXECLISTS(dev_priv)) {
1460                 struct i915_request * const *port, *rq;
1461                 const u32 *hws =
1462                         &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1463                 const u8 num_entries = execlists->csb_size;
1464                 unsigned int idx;
1465                 u8 read, write;
1466
1467                 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1468                            yesno(test_bit(TASKLET_STATE_SCHED,
1469                                           &engine->execlists.tasklet.state)),
1470                            enableddisabled(!atomic_read(&engine->execlists.tasklet.count)),
1471                            repr_timer(&engine->execlists.preempt),
1472                            repr_timer(&engine->execlists.timer));
1473
1474                 read = execlists->csb_head;
1475                 write = READ_ONCE(*execlists->csb_write);
1476
1477                 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1478                            ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1479                            ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1480                            read, write, num_entries);
1481
1482                 if (read >= num_entries)
1483                         read = 0;
1484                 if (write >= num_entries)
1485                         write = 0;
1486                 if (read > write)
1487                         write += num_entries;
1488                 while (read < write) {
1489                         idx = ++read % num_entries;
1490                         drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
1491                                    idx, hws[idx * 2], hws[idx * 2 + 1]);
1492                 }
1493
1494                 execlists_active_lock_bh(execlists);
1495                 rcu_read_lock();
1496                 for (port = execlists->active; (rq = *port); port++) {
1497                         char hdr[160];
1498                         int len;
1499
1500                         len = scnprintf(hdr, sizeof(hdr),
1501                                         "\t\tActive[%d]:  ccid:%08x%s%s, ",
1502                                         (int)(port - execlists->active),
1503                                         rq->context->lrc.ccid,
1504                                         intel_context_is_closed(rq->context) ? "!" : "",
1505                                         intel_context_is_banned(rq->context) ? "*" : "");
1506                         len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1507                         scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1508                         print_request(m, rq, hdr);
1509                 }
1510                 for (port = execlists->pending; (rq = *port); port++) {
1511                         char hdr[160];
1512                         int len;
1513
1514                         len = scnprintf(hdr, sizeof(hdr),
1515                                         "\t\tPending[%d]: ccid:%08x%s%s, ",
1516                                         (int)(port - execlists->pending),
1517                                         rq->context->lrc.ccid,
1518                                         intel_context_is_closed(rq->context) ? "!" : "",
1519                                         intel_context_is_banned(rq->context) ? "*" : "");
1520                         len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1521                         scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1522                         print_request(m, rq, hdr);
1523                 }
1524                 rcu_read_unlock();
1525                 execlists_active_unlock_bh(execlists);
1526         } else if (INTEL_GEN(dev_priv) > 6) {
1527                 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1528                            ENGINE_READ(engine, RING_PP_DIR_BASE));
1529                 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1530                            ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
1531                 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1532                            ENGINE_READ(engine, RING_PP_DIR_DCLV));
1533         }
1534 }
1535
1536 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1537 {
1538         void *ring;
1539         int size;
1540
1541         drm_printf(m,
1542                    "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1543                    rq->head, rq->postfix, rq->tail,
1544                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
1545                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
1546
1547         size = rq->tail - rq->head;
1548         if (rq->tail < rq->head)
1549                 size += rq->ring->size;
1550
1551         ring = kmalloc(size, GFP_ATOMIC);
1552         if (ring) {
1553                 const void *vaddr = rq->ring->vaddr;
1554                 unsigned int head = rq->head;
1555                 unsigned int len = 0;
1556
1557                 if (rq->tail < head) {
1558                         len = rq->ring->size - head;
1559                         memcpy(ring, vaddr + head, len);
1560                         head = 0;
1561                 }
1562                 memcpy(ring + len, vaddr + head, size - len);
1563
1564                 hexdump(m, ring, size);
1565                 kfree(ring);
1566         }
1567 }
1568
1569 static unsigned long list_count(struct list_head *list)
1570 {
1571         struct list_head *pos;
1572         unsigned long count = 0;
1573
1574         list_for_each(pos, list)
1575                 count++;
1576
1577         return count;
1578 }
1579
1580 void intel_engine_dump(struct intel_engine_cs *engine,
1581                        struct drm_printer *m,
1582                        const char *header, ...)
1583 {
1584         struct i915_gpu_error * const error = &engine->i915->gpu_error;
1585         struct i915_request *rq;
1586         intel_wakeref_t wakeref;
1587         unsigned long flags;
1588         ktime_t dummy;
1589
1590         if (header) {
1591                 va_list ap;
1592
1593                 va_start(ap, header);
1594                 drm_vprintf(m, header, &ap);
1595                 va_end(ap);
1596         }
1597
1598         if (intel_gt_is_wedged(engine->gt))
1599                 drm_printf(m, "*** WEDGED ***\n");
1600
1601         drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
1602         drm_printf(m, "\tBarriers?: %s\n",
1603                    yesno(!llist_empty(&engine->barrier_tasks)));
1604         drm_printf(m, "\tLatency: %luus\n",
1605                    ewma__engine_latency_read(&engine->latency));
1606         if (intel_engine_supports_stats(engine))
1607                 drm_printf(m, "\tRuntime: %llums\n",
1608                            ktime_to_ms(intel_engine_get_busy_time(engine,
1609                                                                   &dummy)));
1610         drm_printf(m, "\tForcewake: %x domains, %d active\n",
1611                    engine->fw_domain, atomic_read(&engine->fw_active));
1612
1613         rcu_read_lock();
1614         rq = READ_ONCE(engine->heartbeat.systole);
1615         if (rq)
1616                 drm_printf(m, "\tHeartbeat: %d ms ago\n",
1617                            jiffies_to_msecs(jiffies - rq->emitted_jiffies));
1618         rcu_read_unlock();
1619         drm_printf(m, "\tReset count: %d (global %d)\n",
1620                    i915_reset_engine_count(error, engine),
1621                    i915_reset_count(error));
1622
1623         drm_printf(m, "\tRequests:\n");
1624
1625         spin_lock_irqsave(&engine->active.lock, flags);
1626         rq = intel_engine_find_active_request(engine);
1627         if (rq) {
1628                 struct intel_timeline *tl = get_timeline(rq);
1629
1630                 print_request(m, rq, "\t\tactive ");
1631
1632                 drm_printf(m, "\t\tring->start:  0x%08x\n",
1633                            i915_ggtt_offset(rq->ring->vma));
1634                 drm_printf(m, "\t\tring->head:   0x%08x\n",
1635                            rq->ring->head);
1636                 drm_printf(m, "\t\tring->tail:   0x%08x\n",
1637                            rq->ring->tail);
1638                 drm_printf(m, "\t\tring->emit:   0x%08x\n",
1639                            rq->ring->emit);
1640                 drm_printf(m, "\t\tring->space:  0x%08x\n",
1641                            rq->ring->space);
1642
1643                 if (tl) {
1644                         drm_printf(m, "\t\tring->hwsp:   0x%08x\n",
1645                                    tl->hwsp_offset);
1646                         intel_timeline_put(tl);
1647                 }
1648
1649                 print_request_ring(m, rq);
1650
1651                 if (rq->context->lrc_reg_state) {
1652                         drm_printf(m, "Logical Ring Context:\n");
1653                         hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
1654                 }
1655         }
1656         drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold));
1657         spin_unlock_irqrestore(&engine->active.lock, flags);
1658
1659         drm_printf(m, "\tMMIO base:  0x%08x\n", engine->mmio_base);
1660         wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
1661         if (wakeref) {
1662                 intel_engine_print_registers(engine, m);
1663                 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1664         } else {
1665                 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
1666         }
1667
1668         intel_execlists_show_requests(engine, m, print_request, 8);
1669
1670         drm_printf(m, "HWSP:\n");
1671         hexdump(m, engine->status_page.addr, PAGE_SIZE);
1672
1673         drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
1674
1675         intel_engine_print_breadcrumbs(engine, m);
1676 }
1677
1678 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine,
1679                                             ktime_t *now)
1680 {
1681         ktime_t total = engine->stats.total;
1682
1683         /*
1684          * If the engine is executing something at the moment
1685          * add it to the total.
1686          */
1687         *now = ktime_get();
1688         if (atomic_read(&engine->stats.active))
1689                 total = ktime_add(total, ktime_sub(*now, engine->stats.start));
1690
1691         return total;
1692 }
1693
1694 /**
1695  * intel_engine_get_busy_time() - Return current accumulated engine busyness
1696  * @engine: engine to report on
1697  * @now: monotonic timestamp of sampling
1698  *
1699  * Returns accumulated time @engine was busy since engine stats were enabled.
1700  */
1701 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
1702 {
1703         unsigned int seq;
1704         ktime_t total;
1705
1706         do {
1707                 seq = read_seqbegin(&engine->stats.lock);
1708                 total = __intel_engine_get_busy_time(engine, now);
1709         } while (read_seqretry(&engine->stats.lock, seq));
1710
1711         return total;
1712 }
1713
1714 static bool match_ring(struct i915_request *rq)
1715 {
1716         u32 ring = ENGINE_READ(rq->engine, RING_START);
1717
1718         return ring == i915_ggtt_offset(rq->ring->vma);
1719 }
1720
1721 struct i915_request *
1722 intel_engine_find_active_request(struct intel_engine_cs *engine)
1723 {
1724         struct i915_request *request, *active = NULL;
1725
1726         /*
1727          * We are called by the error capture, reset and to dump engine
1728          * state at random points in time. In particular, note that neither is
1729          * crucially ordered with an interrupt. After a hang, the GPU is dead
1730          * and we assume that no more writes can happen (we waited long enough
1731          * for all writes that were in transaction to be flushed) - adding an
1732          * extra delay for a recent interrupt is pointless. Hence, we do
1733          * not need an engine->irq_seqno_barrier() before the seqno reads.
1734          * At all other times, we must assume the GPU is still running, but
1735          * we only care about the snapshot of this moment.
1736          */
1737         lockdep_assert_held(&engine->active.lock);
1738
1739         rcu_read_lock();
1740         request = execlists_active(&engine->execlists);
1741         if (request) {
1742                 struct intel_timeline *tl = request->context->timeline;
1743
1744                 list_for_each_entry_from_reverse(request, &tl->requests, link) {
1745                         if (i915_request_completed(request))
1746                                 break;
1747
1748                         active = request;
1749                 }
1750         }
1751         rcu_read_unlock();
1752         if (active)
1753                 return active;
1754
1755         list_for_each_entry(request, &engine->active.requests, sched.link) {
1756                 if (i915_request_completed(request))
1757                         continue;
1758
1759                 if (!i915_request_started(request))
1760                         continue;
1761
1762                 /* More than one preemptible request may match! */
1763                 if (!match_ring(request))
1764                         continue;
1765
1766                 active = request;
1767                 break;
1768         }
1769
1770         return active;
1771 }
1772
1773 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1774 #include "mock_engine.c"
1775 #include "selftest_engine.c"
1776 #include "selftest_engine_cs.c"
1777 #endif