2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <drm/drm_print.h>
27 #include "gem/i915_gem_context.h"
31 #include "intel_context.h"
32 #include "intel_engine.h"
33 #include "intel_engine_pm.h"
34 #include "intel_engine_user.h"
36 #include "intel_gt_requests.h"
37 #include "intel_gt_pm.h"
38 #include "intel_lrc.h"
39 #include "intel_reset.h"
40 #include "intel_ring.h"
42 /* Haswell does have the CXT_SIZE register however it does not appear to be
43 * valid. Now, docs explain in dwords what is in the context object. The full
44 * size is 70720 bytes, however, the power context and execlist context will
45 * never be saved (power context is stored elsewhere, and execlists don't work
46 * on HSW) - so the final size, including the extra state required for the
47 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
49 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
51 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
52 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
53 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
54 #define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE)
55 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
57 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
59 #define MAX_MMIO_BASES 3
64 /* mmio bases table *must* be sorted in reverse gen order */
65 struct engine_mmio_base {
68 } mmio_bases[MAX_MMIO_BASES];
71 static const struct engine_info intel_engines[] = {
74 .class = RENDER_CLASS,
77 { .gen = 1, .base = RENDER_RING_BASE }
82 .class = COPY_ENGINE_CLASS,
85 { .gen = 6, .base = BLT_RING_BASE }
90 .class = VIDEO_DECODE_CLASS,
93 { .gen = 11, .base = GEN11_BSD_RING_BASE },
94 { .gen = 6, .base = GEN6_BSD_RING_BASE },
95 { .gen = 4, .base = BSD_RING_BASE }
100 .class = VIDEO_DECODE_CLASS,
103 { .gen = 11, .base = GEN11_BSD2_RING_BASE },
104 { .gen = 8, .base = GEN8_BSD2_RING_BASE }
109 .class = VIDEO_DECODE_CLASS,
112 { .gen = 11, .base = GEN11_BSD3_RING_BASE }
117 .class = VIDEO_DECODE_CLASS,
120 { .gen = 11, .base = GEN11_BSD4_RING_BASE }
125 .class = VIDEO_ENHANCEMENT_CLASS,
128 { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
129 { .gen = 7, .base = VEBOX_RING_BASE }
134 .class = VIDEO_ENHANCEMENT_CLASS,
137 { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
143 * intel_engine_context_size() - return the size of the context for an engine
145 * @class: engine class
147 * Each engine class may require a different amount of space for a context
150 * Return: size (in bytes) of an engine class specific context image
152 * Note: this size includes the HWSP, which is part of the context image
153 * in LRC mode, but does not include the "shared data page" used with
154 * GuC submission. The caller should account for this if using the GuC.
156 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
158 struct intel_uncore *uncore = gt->uncore;
161 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
165 switch (INTEL_GEN(gt->i915)) {
167 MISSING_CASE(INTEL_GEN(gt->i915));
168 return DEFAULT_LR_CONTEXT_RENDER_SIZE;
171 return GEN11_LR_CONTEXT_RENDER_SIZE;
173 return GEN10_LR_CONTEXT_RENDER_SIZE;
175 return GEN9_LR_CONTEXT_RENDER_SIZE;
177 return GEN8_LR_CONTEXT_RENDER_SIZE;
179 if (IS_HASWELL(gt->i915))
180 return HSW_CXT_TOTAL_SIZE;
182 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
183 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
186 cxt_size = intel_uncore_read(uncore, CXT_SIZE);
187 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
192 * There is a discrepancy here between the size reported
193 * by the register and the size of the context layout
194 * in the docs. Both are described as authorative!
196 * The discrepancy is on the order of a few cachelines,
197 * but the total is under one page (4k), which is our
198 * minimum allocation anyway so it should all come
201 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
202 drm_dbg(>->i915->drm,
203 "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
204 INTEL_GEN(gt->i915), cxt_size * 64,
206 return round_up(cxt_size * 64, PAGE_SIZE);
209 /* For the special day when i810 gets merged. */
217 case VIDEO_DECODE_CLASS:
218 case VIDEO_ENHANCEMENT_CLASS:
219 case COPY_ENGINE_CLASS:
220 if (INTEL_GEN(gt->i915) < 8)
222 return GEN8_LR_CONTEXT_OTHER_SIZE;
226 static u32 __engine_mmio_base(struct drm_i915_private *i915,
227 const struct engine_mmio_base *bases)
231 for (i = 0; i < MAX_MMIO_BASES; i++)
232 if (INTEL_GEN(i915) >= bases[i].gen)
235 GEM_BUG_ON(i == MAX_MMIO_BASES);
236 GEM_BUG_ON(!bases[i].base);
238 return bases[i].base;
241 static void __sprint_engine_name(struct intel_engine_cs *engine)
244 * Before we know what the uABI name for this engine will be,
245 * we still would like to keep track of this engine in the debug logs.
246 * We throw in a ' here as a reminder that this isn't its final name.
248 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
249 intel_engine_class_repr(engine->class),
250 engine->instance) >= sizeof(engine->name));
253 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
256 * Though they added more rings on g4x/ilk, they did not add
257 * per-engine HWSTAM until gen6.
259 if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
262 if (INTEL_GEN(engine->i915) >= 3)
263 ENGINE_WRITE(engine, RING_HWSTAM, mask);
265 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
268 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
270 /* Mask off all writes into the unknown HWSP */
271 intel_engine_set_hwsp_writemask(engine, ~0u);
274 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
276 const struct engine_info *info = &intel_engines[id];
277 struct drm_i915_private *i915 = gt->i915;
278 struct intel_engine_cs *engine;
280 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
281 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
283 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
286 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
289 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
292 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
295 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
299 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
302 engine->legacy_idx = INVALID_ENGINE;
303 engine->mask = BIT(id);
306 engine->uncore = gt->uncore;
307 engine->hw_id = engine->guc_id = info->hw_id;
308 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
310 engine->class = info->class;
311 engine->instance = info->instance;
312 __sprint_engine_name(engine);
314 engine->props.heartbeat_interval_ms =
315 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
316 engine->props.max_busywait_duration_ns =
317 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
318 engine->props.preempt_timeout_ms =
319 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
320 engine->props.stop_timeout_ms =
321 CONFIG_DRM_I915_STOP_TIMEOUT;
322 engine->props.timeslice_duration_ms =
323 CONFIG_DRM_I915_TIMESLICE_DURATION;
325 /* Override to uninterruptible for OpenCL workloads. */
326 if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
327 engine->props.preempt_timeout_ms = 0;
329 engine->defaults = engine->props; /* never to change again */
331 engine->context_size = intel_engine_context_size(gt, engine->class);
332 if (WARN_ON(engine->context_size > BIT(20)))
333 engine->context_size = 0;
334 if (engine->context_size)
335 DRIVER_CAPS(i915)->has_logical_contexts = true;
337 /* Nothing to do here, execute in order of dependencies */
338 engine->schedule = NULL;
340 ewma__engine_latency_init(&engine->latency);
341 seqlock_init(&engine->stats.lock);
343 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
345 /* Scrub mmio state on takeover */
346 intel_engine_sanitize_mmio(engine);
348 gt->engine_class[info->class][info->instance] = engine;
349 gt->engine[id] = engine;
354 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
356 struct drm_i915_private *i915 = engine->i915;
358 if (engine->class == VIDEO_DECODE_CLASS) {
360 * HEVC support is present on first engine instance
361 * before Gen11 and on all instances afterwards.
363 if (INTEL_GEN(i915) >= 11 ||
364 (INTEL_GEN(i915) >= 9 && engine->instance == 0))
365 engine->uabi_capabilities |=
366 I915_VIDEO_CLASS_CAPABILITY_HEVC;
369 * SFC block is present only on even logical engine
372 if ((INTEL_GEN(i915) >= 11 &&
373 engine->gt->info.vdbox_sfc_access & engine->mask) ||
374 (INTEL_GEN(i915) >= 9 && engine->instance == 0))
375 engine->uabi_capabilities |=
376 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
377 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
378 if (INTEL_GEN(i915) >= 9)
379 engine->uabi_capabilities |=
380 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
384 static void intel_setup_engine_capabilities(struct intel_gt *gt)
386 struct intel_engine_cs *engine;
387 enum intel_engine_id id;
389 for_each_engine(engine, gt, id)
390 __setup_engine_capabilities(engine);
394 * intel_engines_release() - free the resources allocated for Command Streamers
395 * @gt: pointer to struct intel_gt
397 void intel_engines_release(struct intel_gt *gt)
399 struct intel_engine_cs *engine;
400 enum intel_engine_id id;
403 * Before we release the resources held by engine, we must be certain
404 * that the HW is no longer accessing them -- having the GPU scribble
405 * to or read from a page being used for something else causes no end
408 * The GPU should be reset by this point, but assume the worst just
409 * in case we aborted before completely initialising the engines.
411 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
412 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
413 __intel_gt_reset(gt, ALL_ENGINES);
415 /* Decouple the backend; but keep the layout for late GPU resets */
416 for_each_engine(engine, gt, id) {
417 if (!engine->release)
420 intel_wakeref_wait_for_idle(&engine->wakeref);
421 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
423 engine->release(engine);
424 engine->release = NULL;
426 memset(&engine->reset, 0, sizeof(engine->reset));
430 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
432 if (!engine->request_pool)
435 kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
438 void intel_engines_free(struct intel_gt *gt)
440 struct intel_engine_cs *engine;
441 enum intel_engine_id id;
443 /* Free the requests! dma-resv keeps fences around for an eternity */
446 for_each_engine(engine, gt, id) {
447 intel_engine_free_request_pool(engine);
449 gt->engine[id] = NULL;
454 * Determine which engines are fused off in our particular hardware.
455 * Note that we have a catch-22 situation where we need to be able to access
456 * the blitter forcewake domain to read the engine fuses, but at the same time
457 * we need to know which engines are available on the system to know which
458 * forcewake domains are present. We solve this by intializing the forcewake
459 * domains based on the full engine mask in the platform capabilities before
460 * calling this function and pruning the domains for fused-off engines
463 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
465 struct drm_i915_private *i915 = gt->i915;
466 struct intel_gt_info *info = >->info;
467 struct intel_uncore *uncore = gt->uncore;
468 unsigned int logical_vdbox = 0;
474 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
476 if (INTEL_GEN(i915) < 11)
477 return info->engine_mask;
479 media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
481 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
482 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
483 GEN11_GT_VEBOX_DISABLE_SHIFT;
485 for (i = 0; i < I915_MAX_VCS; i++) {
486 if (!HAS_ENGINE(gt, _VCS(i))) {
487 vdbox_mask &= ~BIT(i);
491 if (!(BIT(i) & vdbox_mask)) {
492 info->engine_mask &= ~BIT(_VCS(i));
493 drm_dbg(&i915->drm, "vcs%u fused off\n", i);
498 * In Gen11, only even numbered logical VDBOXes are
499 * hooked up to an SFC (Scaler & Format Converter) unit.
500 * In TGL each VDBOX has access to an SFC.
502 if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
503 gt->info.vdbox_sfc_access |= BIT(i);
505 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
506 vdbox_mask, VDBOX_MASK(gt));
507 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
509 for (i = 0; i < I915_MAX_VECS; i++) {
510 if (!HAS_ENGINE(gt, _VECS(i))) {
511 vebox_mask &= ~BIT(i);
515 if (!(BIT(i) & vebox_mask)) {
516 info->engine_mask &= ~BIT(_VECS(i));
517 drm_dbg(&i915->drm, "vecs%u fused off\n", i);
520 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
521 vebox_mask, VEBOX_MASK(gt));
522 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
524 return info->engine_mask;
528 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
529 * @gt: pointer to struct intel_gt
531 * Return: non-zero if the initialization failed.
533 int intel_engines_init_mmio(struct intel_gt *gt)
535 struct drm_i915_private *i915 = gt->i915;
536 const unsigned int engine_mask = init_engine_mask(gt);
537 unsigned int mask = 0;
541 drm_WARN_ON(&i915->drm, engine_mask == 0);
542 drm_WARN_ON(&i915->drm, engine_mask &
543 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
545 if (i915_inject_probe_failure(i915))
548 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
549 if (!HAS_ENGINE(gt, i))
552 err = intel_engine_setup(gt, i);
560 * Catch failures to update intel_engines table when the new engines
561 * are added to the driver by a warning and disabling the forgotten
564 if (drm_WARN_ON(&i915->drm, mask != engine_mask))
565 gt->info.engine_mask = mask;
567 gt->info.num_engines = hweight32(mask);
569 intel_gt_check_and_clear_faults(gt);
571 intel_setup_engine_capabilities(gt);
573 intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
578 intel_engines_free(gt);
582 void intel_engine_init_execlists(struct intel_engine_cs *engine)
584 struct intel_engine_execlists * const execlists = &engine->execlists;
586 execlists->port_mask = 1;
587 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
588 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
590 memset(execlists->pending, 0, sizeof(execlists->pending));
592 memset(execlists->inflight, 0, sizeof(execlists->inflight));
594 execlists->queue_priority_hint = INT_MIN;
595 execlists->queue = RB_ROOT_CACHED;
598 static void cleanup_status_page(struct intel_engine_cs *engine)
600 struct i915_vma *vma;
602 /* Prevent writes into HWSP after returning the page to the system */
603 intel_engine_set_hwsp_writemask(engine, ~0u);
605 vma = fetch_and_zero(&engine->status_page.vma);
609 if (!HWS_NEEDS_PHYSICAL(engine->i915))
612 i915_gem_object_unpin_map(vma->obj);
613 i915_gem_object_put(vma->obj);
616 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
617 struct i915_vma *vma)
621 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
623 * On g33, we cannot place HWS above 256MiB, so
624 * restrict its pinning to the low mappable arena.
625 * Though this restriction is not documented for
626 * gen4, gen5, or byt, they also behave similarly
627 * and hang if the HWS is placed at the top of the
628 * GTT. To generalise, it appears that all !llc
629 * platforms have issues with us placing the HWS
630 * above the mappable region (even though we never
633 flags = PIN_MAPPABLE;
637 return i915_ggtt_pin(vma, 0, flags);
640 static int init_status_page(struct intel_engine_cs *engine)
642 struct drm_i915_gem_object *obj;
643 struct i915_vma *vma;
648 * Though the HWS register does support 36bit addresses, historically
649 * we have had hangs and corruption reported due to wild writes if
650 * the HWS is placed above 4G. We only allow objects to be allocated
651 * in GFP_DMA32 for i965, and no earlier physical address users had
652 * access to more than 4G.
654 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
656 drm_err(&engine->i915->drm,
657 "Failed to allocate status page\n");
661 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
663 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
669 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
671 ret = PTR_ERR(vaddr);
675 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
676 engine->status_page.vma = vma;
678 if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
679 ret = pin_ggtt_status_page(engine, vma);
687 i915_gem_object_unpin_map(obj);
689 i915_gem_object_put(obj);
693 static int engine_setup_common(struct intel_engine_cs *engine)
697 init_llist_head(&engine->barrier_tasks);
699 err = init_status_page(engine);
703 intel_engine_init_active(engine, ENGINE_PHYSICAL);
704 intel_engine_init_breadcrumbs(engine);
705 intel_engine_init_execlists(engine);
706 intel_engine_init_cmd_parser(engine);
707 intel_engine_init__pm(engine);
708 intel_engine_init_retire(engine);
710 /* Use the whole device by default */
712 intel_sseu_from_device_info(&engine->gt->info.sseu);
714 intel_engine_init_workarounds(engine);
715 intel_engine_init_whitelist(engine);
716 intel_engine_init_ctx_wa(engine);
721 struct measure_breadcrumb {
722 struct i915_request rq;
723 struct intel_ring ring;
727 static int measure_breadcrumb_dw(struct intel_context *ce)
729 struct intel_engine_cs *engine = ce->engine;
730 struct measure_breadcrumb *frame;
733 GEM_BUG_ON(!engine->gt->scratch);
735 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
739 frame->rq.engine = engine;
740 frame->rq.context = ce;
741 rcu_assign_pointer(frame->rq.timeline, ce->timeline);
743 frame->ring.vaddr = frame->cs;
744 frame->ring.size = sizeof(frame->cs);
746 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
747 frame->ring.effective_size = frame->ring.size;
748 intel_ring_update_space(&frame->ring);
749 frame->rq.ring = &frame->ring;
751 mutex_lock(&ce->timeline->mutex);
752 spin_lock_irq(&engine->active.lock);
754 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
756 spin_unlock_irq(&engine->active.lock);
757 mutex_unlock(&ce->timeline->mutex);
759 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
766 intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
768 INIT_LIST_HEAD(&engine->active.requests);
769 INIT_LIST_HEAD(&engine->active.hold);
771 spin_lock_init(&engine->active.lock);
772 lockdep_set_subclass(&engine->active.lock, subclass);
775 * Due to an interesting quirk in lockdep's internal debug tracking,
776 * after setting a subclass we must ensure the lock is used. Otherwise,
777 * nr_unused_locks is incremented once too often.
779 #ifdef CONFIG_DEBUG_LOCK_ALLOC
781 lock_map_acquire(&engine->active.lock.dep_map);
782 lock_map_release(&engine->active.lock.dep_map);
787 static struct intel_context *
788 create_pinned_context(struct intel_engine_cs *engine,
790 struct lock_class_key *key,
793 struct intel_context *ce;
796 ce = intel_context_create(engine);
800 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
801 ce->timeline = page_pack_bits(NULL, hwsp);
803 err = intel_context_pin(ce); /* perma-pin so it is always available */
805 intel_context_put(ce);
810 * Give our perma-pinned kernel timelines a separate lockdep class,
811 * so that we can use them from within the normal user timelines
812 * should we need to inject GPU operations during their request
815 lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
820 static struct intel_context *
821 create_kernel_context(struct intel_engine_cs *engine)
823 static struct lock_class_key kernel;
825 return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
826 &kernel, "kernel_context");
830 * intel_engines_init_common - initialize cengine state which might require hw access
831 * @engine: Engine to initialize.
833 * Initializes @engine@ structure members shared between legacy and execlists
834 * submission modes which do require hardware access.
836 * Typcally done at later stages of submission mode specific engine setup.
838 * Returns zero on success or an error code on failure.
840 static int engine_init_common(struct intel_engine_cs *engine)
842 struct intel_context *ce;
845 engine->set_default_submission(engine);
848 * We may need to do things with the shrinker which
849 * require us to immediately switch back to the default
850 * context. This can cause a problem as pinning the
851 * default context also requires GTT space which may not
852 * be available. To avoid this we always pin the default
855 ce = create_kernel_context(engine);
859 ret = measure_breadcrumb_dw(ce);
863 engine->emit_fini_breadcrumb_dw = ret;
864 engine->kernel_context = ce;
869 intel_context_put(ce);
873 int intel_engines_init(struct intel_gt *gt)
875 int (*setup)(struct intel_engine_cs *engine);
876 struct intel_engine_cs *engine;
877 enum intel_engine_id id;
880 if (HAS_EXECLISTS(gt->i915))
881 setup = intel_execlists_submission_setup;
883 setup = intel_ring_submission_setup;
885 for_each_engine(engine, gt, id) {
886 err = engine_setup_common(engine);
894 err = engine_init_common(engine);
898 intel_engine_add_user(engine);
905 * intel_engines_cleanup_common - cleans up the engine state created by
906 * the common initiailizers.
907 * @engine: Engine to cleanup.
909 * This cleans up everything created by the common helpers.
911 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
913 GEM_BUG_ON(!list_empty(&engine->active.requests));
914 tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
916 cleanup_status_page(engine);
918 intel_engine_fini_retire(engine);
919 intel_engine_fini_breadcrumbs(engine);
920 intel_engine_cleanup_cmd_parser(engine);
922 if (engine->default_state)
923 fput(engine->default_state);
925 if (engine->kernel_context) {
926 intel_context_unpin(engine->kernel_context);
927 intel_context_put(engine->kernel_context);
929 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
931 intel_wa_list_free(&engine->ctx_wa_list);
932 intel_wa_list_free(&engine->wa_list);
933 intel_wa_list_free(&engine->whitelist);
937 * intel_engine_resume - re-initializes the HW state of the engine
938 * @engine: Engine to resume.
940 * Returns zero on success or an error code on failure.
942 int intel_engine_resume(struct intel_engine_cs *engine)
944 intel_engine_apply_workarounds(engine);
945 intel_engine_apply_whitelist(engine);
947 return engine->resume(engine);
950 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
952 struct drm_i915_private *i915 = engine->i915;
956 if (INTEL_GEN(i915) >= 8)
957 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
958 else if (INTEL_GEN(i915) >= 4)
959 acthd = ENGINE_READ(engine, RING_ACTHD);
961 acthd = ENGINE_READ(engine, ACTHD);
966 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
970 if (INTEL_GEN(engine->i915) >= 8)
971 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
973 bbaddr = ENGINE_READ(engine, RING_BBADDR);
978 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
980 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
984 * If we are doing a normal GPU reset, we can take our time and allow
985 * the engine to quiesce. We've stopped submission to the engine, and
986 * if we wait long enough an innocent context should complete and
987 * leave the engine idle. So they should not be caught unaware by
988 * the forthcoming GPU reset (which usually follows the stop_cs)!
990 return READ_ONCE(engine->props.stop_timeout_ms);
993 int intel_engine_stop_cs(struct intel_engine_cs *engine)
995 struct intel_uncore *uncore = engine->uncore;
996 const u32 base = engine->mmio_base;
997 const i915_reg_t mode = RING_MI_MODE(base);
1000 if (INTEL_GEN(engine->i915) < 3)
1003 ENGINE_TRACE(engine, "\n");
1005 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1008 if (__intel_wait_for_register_fw(uncore,
1009 mode, MODE_IDLE, MODE_IDLE,
1010 1000, stop_timeout(engine),
1012 ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n");
1016 /* A final mmio read to let GPU writes be hopefully flushed to memory */
1017 intel_uncore_posting_read_fw(uncore, mode);
1022 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1024 ENGINE_TRACE(engine, "\n");
1026 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1029 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1032 case I915_CACHE_NONE: return " uncached";
1033 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1034 case I915_CACHE_L3_LLC: return " L3+LLC";
1035 case I915_CACHE_WT: return " WT";
1041 read_subslice_reg(const struct intel_engine_cs *engine,
1042 int slice, int subslice, i915_reg_t reg)
1044 struct drm_i915_private *i915 = engine->i915;
1045 struct intel_uncore *uncore = engine->uncore;
1046 u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
1047 enum forcewake_domains fw_domains;
1049 if (INTEL_GEN(i915) >= 11) {
1050 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1051 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1053 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1054 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1057 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
1059 fw_domains |= intel_uncore_forcewake_for_reg(uncore,
1061 FW_REG_READ | FW_REG_WRITE);
1063 spin_lock_irq(&uncore->lock);
1064 intel_uncore_forcewake_get__locked(uncore, fw_domains);
1066 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
1070 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1072 val = intel_uncore_read_fw(uncore, reg);
1075 mcr |= old_mcr & mcr_mask;
1077 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1079 intel_uncore_forcewake_put__locked(uncore, fw_domains);
1080 spin_unlock_irq(&uncore->lock);
1085 /* NB: please notice the memset */
1086 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1087 struct intel_instdone *instdone)
1089 struct drm_i915_private *i915 = engine->i915;
1090 const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
1091 struct intel_uncore *uncore = engine->uncore;
1092 u32 mmio_base = engine->mmio_base;
1096 memset(instdone, 0, sizeof(*instdone));
1098 switch (INTEL_GEN(i915)) {
1100 instdone->instdone =
1101 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1103 if (engine->id != RCS0)
1106 instdone->slice_common =
1107 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1108 if (INTEL_GEN(i915) >= 12) {
1109 instdone->slice_common_extra[0] =
1110 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1111 instdone->slice_common_extra[1] =
1112 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1114 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
1115 instdone->sampler[slice][subslice] =
1116 read_subslice_reg(engine, slice, subslice,
1117 GEN7_SAMPLER_INSTDONE);
1118 instdone->row[slice][subslice] =
1119 read_subslice_reg(engine, slice, subslice,
1124 instdone->instdone =
1125 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1127 if (engine->id != RCS0)
1130 instdone->slice_common =
1131 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1132 instdone->sampler[0][0] =
1133 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1134 instdone->row[0][0] =
1135 intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1141 instdone->instdone =
1142 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1143 if (engine->id == RCS0)
1144 /* HACK: Using the wrong struct member */
1145 instdone->slice_common =
1146 intel_uncore_read(uncore, GEN4_INSTDONE1);
1150 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1155 static bool ring_is_idle(struct intel_engine_cs *engine)
1159 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1162 if (!intel_engine_pm_get_if_awake(engine))
1165 /* First check that no commands are left in the ring */
1166 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1167 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1170 /* No bit for gen2, so assume the CS parser is idle */
1171 if (INTEL_GEN(engine->i915) > 2 &&
1172 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1175 intel_engine_pm_put(engine);
1180 void intel_engine_flush_submission(struct intel_engine_cs *engine)
1182 struct tasklet_struct *t = &engine->execlists.tasklet;
1187 /* Synchronise and wait for the tasklet on another CPU */
1190 /* Having cancelled the tasklet, ensure that is run */
1192 if (tasklet_trylock(t)) {
1193 /* Must wait for any GPU reset in progress. */
1194 if (__tasklet_is_enabled(t))
1202 * intel_engine_is_idle() - Report if the engine has finished process all work
1203 * @engine: the intel_engine_cs
1205 * Return true if there are no requests pending, nothing left to be submitted
1206 * to hardware, and that the engine is idle.
1208 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1210 /* More white lies, if wedged, hw state is inconsistent */
1211 if (intel_gt_is_wedged(engine->gt))
1214 if (!intel_engine_pm_is_awake(engine))
1217 /* Waiting to drain ELSP? */
1218 if (execlists_active(&engine->execlists)) {
1219 synchronize_hardirq(engine->i915->drm.pdev->irq);
1221 intel_engine_flush_submission(engine);
1223 if (execlists_active(&engine->execlists))
1227 /* ELSP is empty, but there are ready requests? E.g. after reset */
1228 if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
1232 return ring_is_idle(engine);
1235 bool intel_engines_are_idle(struct intel_gt *gt)
1237 struct intel_engine_cs *engine;
1238 enum intel_engine_id id;
1241 * If the driver is wedged, HW state may be very inconsistent and
1242 * report that it is still busy, even though we have stopped using it.
1244 if (intel_gt_is_wedged(gt))
1247 /* Already parked (and passed an idleness test); must still be idle */
1248 if (!READ_ONCE(gt->awake))
1251 for_each_engine(engine, gt, id) {
1252 if (!intel_engine_is_idle(engine))
1259 void intel_engines_reset_default_submission(struct intel_gt *gt)
1261 struct intel_engine_cs *engine;
1262 enum intel_engine_id id;
1264 for_each_engine(engine, gt, id)
1265 engine->set_default_submission(engine);
1268 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1270 switch (INTEL_GEN(engine->i915)) {
1272 return false; /* uses physical not virtual addresses */
1274 /* maybe only uses physical not virtual addresses */
1275 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1277 return !IS_I965G(engine->i915); /* who knows! */
1279 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1285 static int print_sched_attr(const struct i915_sched_attr *attr,
1286 char *buf, int x, int len)
1288 if (attr->priority == I915_PRIORITY_INVALID)
1291 x += snprintf(buf + x, len - x,
1292 " prio=%d", attr->priority);
1297 static void print_request(struct drm_printer *m,
1298 struct i915_request *rq,
1301 const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
1305 x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
1307 drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n",
1309 rq->fence.context, rq->fence.seqno,
1310 i915_request_completed(rq) ? "!" :
1311 i915_request_started(rq) ? "*" :
1313 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1314 &rq->fence.flags) ? "+" :
1315 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
1316 &rq->fence.flags) ? "-" :
1319 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
1323 static struct intel_timeline *get_timeline(struct i915_request *rq)
1325 struct intel_timeline *tl;
1328 * Even though we are holding the engine->active.lock here, there
1329 * is no control over the submission queue per-se and we are
1330 * inspecting the active state at a random point in time, with an
1331 * unknown queue. Play safe and make sure the timeline remains valid.
1332 * (Only being used for pretty printing, one extra kref shouldn't
1333 * cause a camel stampede!)
1336 tl = rcu_dereference(rq->timeline);
1337 if (!kref_get_unless_zero(&tl->kref))
1344 static int print_ring(char *buf, int sz, struct i915_request *rq)
1348 if (!i915_request_signaled(rq)) {
1349 struct intel_timeline *tl = get_timeline(rq);
1351 len = scnprintf(buf, sz,
1352 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1353 i915_ggtt_offset(rq->ring->vma),
1354 tl ? tl->hwsp_offset : 0,
1356 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1360 intel_timeline_put(tl);
1366 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1368 const size_t rowsize = 8 * sizeof(u32);
1369 const void *prev = NULL;
1373 for (pos = 0; pos < len; pos += rowsize) {
1376 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1378 drm_printf(m, "*\n");
1384 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1385 rowsize, sizeof(u32),
1387 false) >= sizeof(line));
1388 drm_printf(m, "[%04zx] %s\n", pos, line);
1395 static const char *repr_timer(const struct timer_list *t)
1397 if (!READ_ONCE(t->expires))
1400 if (timer_pending(t))
1406 static void intel_engine_print_registers(struct intel_engine_cs *engine,
1407 struct drm_printer *m)
1409 struct drm_i915_private *dev_priv = engine->i915;
1410 struct intel_engine_execlists * const execlists = &engine->execlists;
1413 if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
1414 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1415 if (HAS_EXECLISTS(dev_priv)) {
1416 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1417 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1418 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1419 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1421 drm_printf(m, "\tRING_START: 0x%08x\n",
1422 ENGINE_READ(engine, RING_START));
1423 drm_printf(m, "\tRING_HEAD: 0x%08x\n",
1424 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1425 drm_printf(m, "\tRING_TAIL: 0x%08x\n",
1426 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1427 drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
1428 ENGINE_READ(engine, RING_CTL),
1429 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1430 if (INTEL_GEN(engine->i915) > 2) {
1431 drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
1432 ENGINE_READ(engine, RING_MI_MODE),
1433 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1436 if (INTEL_GEN(dev_priv) >= 6) {
1437 drm_printf(m, "\tRING_IMR: 0x%08x\n",
1438 ENGINE_READ(engine, RING_IMR));
1439 drm_printf(m, "\tRING_ESR: 0x%08x\n",
1440 ENGINE_READ(engine, RING_ESR));
1441 drm_printf(m, "\tRING_EMR: 0x%08x\n",
1442 ENGINE_READ(engine, RING_EMR));
1443 drm_printf(m, "\tRING_EIR: 0x%08x\n",
1444 ENGINE_READ(engine, RING_EIR));
1447 addr = intel_engine_get_active_head(engine);
1448 drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
1449 upper_32_bits(addr), lower_32_bits(addr));
1450 addr = intel_engine_get_last_batch_head(engine);
1451 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1452 upper_32_bits(addr), lower_32_bits(addr));
1453 if (INTEL_GEN(dev_priv) >= 8)
1454 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1455 else if (INTEL_GEN(dev_priv) >= 4)
1456 addr = ENGINE_READ(engine, RING_DMA_FADD);
1458 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1459 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1460 upper_32_bits(addr), lower_32_bits(addr));
1461 if (INTEL_GEN(dev_priv) >= 4) {
1462 drm_printf(m, "\tIPEIR: 0x%08x\n",
1463 ENGINE_READ(engine, RING_IPEIR));
1464 drm_printf(m, "\tIPEHR: 0x%08x\n",
1465 ENGINE_READ(engine, RING_IPEHR));
1467 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1468 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1471 if (HAS_EXECLISTS(dev_priv)) {
1472 struct i915_request * const *port, *rq;
1474 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1475 const u8 num_entries = execlists->csb_size;
1479 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1480 yesno(test_bit(TASKLET_STATE_SCHED,
1481 &engine->execlists.tasklet.state)),
1482 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)),
1483 repr_timer(&engine->execlists.preempt),
1484 repr_timer(&engine->execlists.timer));
1486 read = execlists->csb_head;
1487 write = READ_ONCE(*execlists->csb_write);
1489 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1490 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1491 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1492 read, write, num_entries);
1494 if (read >= num_entries)
1496 if (write >= num_entries)
1499 write += num_entries;
1500 while (read < write) {
1501 idx = ++read % num_entries;
1502 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
1503 idx, hws[idx * 2], hws[idx * 2 + 1]);
1506 execlists_active_lock_bh(execlists);
1508 for (port = execlists->active; (rq = *port); port++) {
1512 len = scnprintf(hdr, sizeof(hdr),
1513 "\t\tActive[%d]: ccid:%08x%s%s, ",
1514 (int)(port - execlists->active),
1515 rq->context->lrc.ccid,
1516 intel_context_is_closed(rq->context) ? "!" : "",
1517 intel_context_is_banned(rq->context) ? "*" : "");
1518 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1519 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1520 print_request(m, rq, hdr);
1522 for (port = execlists->pending; (rq = *port); port++) {
1526 len = scnprintf(hdr, sizeof(hdr),
1527 "\t\tPending[%d]: ccid:%08x%s%s, ",
1528 (int)(port - execlists->pending),
1529 rq->context->lrc.ccid,
1530 intel_context_is_closed(rq->context) ? "!" : "",
1531 intel_context_is_banned(rq->context) ? "*" : "");
1532 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1533 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1534 print_request(m, rq, hdr);
1537 execlists_active_unlock_bh(execlists);
1538 } else if (INTEL_GEN(dev_priv) > 6) {
1539 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1540 ENGINE_READ(engine, RING_PP_DIR_BASE));
1541 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1542 ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
1543 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1544 ENGINE_READ(engine, RING_PP_DIR_DCLV));
1548 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1554 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1555 rq->head, rq->postfix, rq->tail,
1556 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
1557 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
1559 size = rq->tail - rq->head;
1560 if (rq->tail < rq->head)
1561 size += rq->ring->size;
1563 ring = kmalloc(size, GFP_ATOMIC);
1565 const void *vaddr = rq->ring->vaddr;
1566 unsigned int head = rq->head;
1567 unsigned int len = 0;
1569 if (rq->tail < head) {
1570 len = rq->ring->size - head;
1571 memcpy(ring, vaddr + head, len);
1574 memcpy(ring + len, vaddr + head, size - len);
1576 hexdump(m, ring, size);
1581 static unsigned long list_count(struct list_head *list)
1583 struct list_head *pos;
1584 unsigned long count = 0;
1586 list_for_each(pos, list)
1592 void intel_engine_dump(struct intel_engine_cs *engine,
1593 struct drm_printer *m,
1594 const char *header, ...)
1596 struct i915_gpu_error * const error = &engine->i915->gpu_error;
1597 struct i915_request *rq;
1598 intel_wakeref_t wakeref;
1599 unsigned long flags;
1605 va_start(ap, header);
1606 drm_vprintf(m, header, &ap);
1610 if (intel_gt_is_wedged(engine->gt))
1611 drm_printf(m, "*** WEDGED ***\n");
1613 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
1614 drm_printf(m, "\tBarriers?: %s\n",
1615 yesno(!llist_empty(&engine->barrier_tasks)));
1616 drm_printf(m, "\tLatency: %luus\n",
1617 ewma__engine_latency_read(&engine->latency));
1618 if (intel_engine_supports_stats(engine))
1619 drm_printf(m, "\tRuntime: %llums\n",
1620 ktime_to_ms(intel_engine_get_busy_time(engine,
1622 drm_printf(m, "\tForcewake: %x domains, %d active\n",
1623 engine->fw_domain, atomic_read(&engine->fw_active));
1626 rq = READ_ONCE(engine->heartbeat.systole);
1628 drm_printf(m, "\tHeartbeat: %d ms ago\n",
1629 jiffies_to_msecs(jiffies - rq->emitted_jiffies));
1631 drm_printf(m, "\tReset count: %d (global %d)\n",
1632 i915_reset_engine_count(error, engine),
1633 i915_reset_count(error));
1635 drm_printf(m, "\tRequests:\n");
1637 spin_lock_irqsave(&engine->active.lock, flags);
1638 rq = intel_engine_find_active_request(engine);
1640 struct intel_timeline *tl = get_timeline(rq);
1642 print_request(m, rq, "\t\tactive ");
1644 drm_printf(m, "\t\tring->start: 0x%08x\n",
1645 i915_ggtt_offset(rq->ring->vma));
1646 drm_printf(m, "\t\tring->head: 0x%08x\n",
1648 drm_printf(m, "\t\tring->tail: 0x%08x\n",
1650 drm_printf(m, "\t\tring->emit: 0x%08x\n",
1652 drm_printf(m, "\t\tring->space: 0x%08x\n",
1656 drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
1658 intel_timeline_put(tl);
1661 print_request_ring(m, rq);
1663 if (rq->context->lrc_reg_state) {
1664 drm_printf(m, "Logical Ring Context:\n");
1665 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
1668 drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold));
1669 spin_unlock_irqrestore(&engine->active.lock, flags);
1671 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
1672 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
1674 intel_engine_print_registers(engine, m);
1675 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1677 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
1680 intel_execlists_show_requests(engine, m, print_request, 8);
1682 drm_printf(m, "HWSP:\n");
1683 hexdump(m, engine->status_page.addr, PAGE_SIZE);
1685 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
1687 intel_engine_print_breadcrumbs(engine, m);
1690 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine,
1693 ktime_t total = engine->stats.total;
1696 * If the engine is executing something at the moment
1697 * add it to the total.
1700 if (atomic_read(&engine->stats.active))
1701 total = ktime_add(total, ktime_sub(*now, engine->stats.start));
1707 * intel_engine_get_busy_time() - Return current accumulated engine busyness
1708 * @engine: engine to report on
1709 * @now: monotonic timestamp of sampling
1711 * Returns accumulated time @engine was busy since engine stats were enabled.
1713 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
1719 seq = read_seqbegin(&engine->stats.lock);
1720 total = __intel_engine_get_busy_time(engine, now);
1721 } while (read_seqretry(&engine->stats.lock, seq));
1726 static bool match_ring(struct i915_request *rq)
1728 u32 ring = ENGINE_READ(rq->engine, RING_START);
1730 return ring == i915_ggtt_offset(rq->ring->vma);
1733 struct i915_request *
1734 intel_engine_find_active_request(struct intel_engine_cs *engine)
1736 struct i915_request *request, *active = NULL;
1739 * We are called by the error capture, reset and to dump engine
1740 * state at random points in time. In particular, note that neither is
1741 * crucially ordered with an interrupt. After a hang, the GPU is dead
1742 * and we assume that no more writes can happen (we waited long enough
1743 * for all writes that were in transaction to be flushed) - adding an
1744 * extra delay for a recent interrupt is pointless. Hence, we do
1745 * not need an engine->irq_seqno_barrier() before the seqno reads.
1746 * At all other times, we must assume the GPU is still running, but
1747 * we only care about the snapshot of this moment.
1749 lockdep_assert_held(&engine->active.lock);
1752 request = execlists_active(&engine->execlists);
1754 struct intel_timeline *tl = request->context->timeline;
1756 list_for_each_entry_from_reverse(request, &tl->requests, link) {
1757 if (i915_request_completed(request))
1767 list_for_each_entry(request, &engine->active.requests, sched.link) {
1768 if (i915_request_completed(request))
1771 if (!i915_request_started(request))
1774 /* More than one preemptible request may match! */
1775 if (!match_ring(request))
1785 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1786 #include "mock_engine.c"
1787 #include "selftest_engine.c"
1788 #include "selftest_engine_cs.c"