drivers/gpu/drm/i915/gt/gen8_ppgtt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <linux/log2.h>
   7
   8 #include "gen8_ppgtt.h"
   9 #include "i915_scatterlist.h"
  10 #include "i915_trace.h"
  11 #include "i915_pvinfo.h"
  12 #include "i915_vgpu.h"
  13 #include "intel_gt.h"
  14 #include "intel_gtt.h"
  15
  16 static u64 gen8_pde_encode(const dma_addr_t addr,
  17                            const enum i915_cache_level level)
  18 {
  19         u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
  20
  21         if (level != I915_CACHE_NONE)
  22                 pde |= PPAT_CACHED_PDE;
  23         else
  24                 pde |= PPAT_UNCACHED;
  25
  26         return pde;
  27 }
  28
  29 static u64 gen8_pte_encode(dma_addr_t addr,
  30                            enum i915_cache_level level,
  31                            u32 flags)
  32 {
  33         gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
  34
  35         if (unlikely(flags & PTE_READ_ONLY))
  36                 pte &= ~_PAGE_RW;
  37
  38         switch (level) {
  39         case I915_CACHE_NONE:
  40                 pte |= PPAT_UNCACHED;
  41                 break;
  42         case I915_CACHE_WT:
  43                 pte |= PPAT_DISPLAY_ELLC;
  44                 break;
  45         default:
  46                 pte |= PPAT_CACHED;
  47                 break;
  48         }
  49
  50         return pte;
  51 }
  52
  53 static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
  54 {
  55         struct drm_i915_private *i915 = ppgtt->vm.i915;
  56         struct intel_uncore *uncore = ppgtt->vm.gt->uncore;
  57         enum vgt_g2v_type msg;
  58         int i;
  59
  60         if (create)
  61                 atomic_inc(px_used(ppgtt->pd)); /* never remove */
  62         else
  63                 atomic_dec(px_used(ppgtt->pd));
  64
  65         mutex_lock(&i915->vgpu.lock);
  66
  67         if (i915_vm_is_4lvl(&ppgtt->vm)) {
  68                 const u64 daddr = px_dma(ppgtt->pd);
  69
  70                 intel_uncore_write(uncore,
  71                                    vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
  72                 intel_uncore_write(uncore,
  73                                    vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
  74
  75                 msg = create ?
  76                         VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
  77                         VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY;
  78         } else {
  79                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
  80                         const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
  81
  82                         intel_uncore_write(uncore,
  83                                            vgtif_reg(pdp[i].lo),
  84                                            lower_32_bits(daddr));
  85                         intel_uncore_write(uncore,
  86                                            vgtif_reg(pdp[i].hi),
  87                                            upper_32_bits(daddr));
  88                 }
  89
  90                 msg = create ?
  91                         VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
  92                         VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY;
  93         }
  94
  95         /* g2v_notify atomically (via hv trap) consumes the message packet. */
  96         intel_uncore_write(uncore, vgtif_reg(g2v_notify), msg);
  97
  98         mutex_unlock(&i915->vgpu.lock);
  99 }
 100
 101 /* Index shifts into the pagetable are offset by GEN8_PTE_SHIFT [12] */
 102 #define GEN8_PAGE_SIZE (SZ_4K) /* page and page-directory sizes are the same */
 103 #define GEN8_PTE_SHIFT (ilog2(GEN8_PAGE_SIZE))
 104 #define GEN8_PDES (GEN8_PAGE_SIZE / sizeof(u64))
 105 #define gen8_pd_shift(lvl) ((lvl) * ilog2(GEN8_PDES))
 106 #define gen8_pd_index(i, lvl) i915_pde_index((i), gen8_pd_shift(lvl))
 107 #define __gen8_pte_shift(lvl) (GEN8_PTE_SHIFT + gen8_pd_shift(lvl))
 108 #define __gen8_pte_index(a, lvl) i915_pde_index((a), __gen8_pte_shift(lvl))
 109
 110 #define as_pd(x) container_of((x), typeof(struct i915_page_directory), pt)
 111
 112 static inline unsigned int
 113 gen8_pd_range(u64 start, u64 end, int lvl, unsigned int *idx)
 114 {
 115         const int shift = gen8_pd_shift(lvl);
 116         const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);
 117
 118         GEM_BUG_ON(start >= end);
 119         end += ~mask >> gen8_pd_shift(1);
 120
 121         *idx = i915_pde_index(start, shift);
 122         if ((start ^ end) & mask)
 123                 return GEN8_PDES - *idx;
 124         else
 125                 return i915_pde_index(end, shift) - *idx;
 126 }
 127
 128 static inline bool gen8_pd_contains(u64 start, u64 end, int lvl)
 129 {
 130         const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);
 131
 132         GEM_BUG_ON(start >= end);
 133         return (start ^ end) & mask && (start & ~mask) == 0;
 134 }
 135
 136 static inline unsigned int gen8_pt_count(u64 start, u64 end)
 137 {
 138         GEM_BUG_ON(start >= end);
 139         if ((start ^ end) >> gen8_pd_shift(1))
 140                 return GEN8_PDES - (start & (GEN8_PDES - 1));
 141         else
 142                 return end - start;
 143 }
 144
 145 static inline unsigned int
 146 gen8_pd_top_count(const struct i915_address_space *vm)
 147 {
 148         unsigned int shift = __gen8_pte_shift(vm->top);
 149         return (vm->total + (1ull << shift) - 1) >> shift;
 150 }
 151
 152 static inline struct i915_page_directory *
 153 gen8_pdp_for_page_index(struct i915_address_space * const vm, const u64 idx)
 154 {
 155         struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
 156
 157         if (vm->top == 2)
 158                 return ppgtt->pd;
 159         else
 160                 return i915_pd_entry(ppgtt->pd, gen8_pd_index(idx, vm->top));
 161 }
 162
 163 static inline struct i915_page_directory *
 164 gen8_pdp_for_page_address(struct i915_address_space * const vm, const u64 addr)
 165 {
 166         return gen8_pdp_for_page_index(vm, addr >> GEN8_PTE_SHIFT);
 167 }
 168
 169 static void __gen8_ppgtt_cleanup(struct i915_address_space *vm,
 170                                  struct i915_page_directory *pd,
 171                                  int count, int lvl)
 172 {
 173         if (lvl) {
 174                 void **pde = pd->entry;
 175
 176                 do {
 177                         if (!*pde)
 178                                 continue;
 179
 180                         __gen8_ppgtt_cleanup(vm, *pde, GEN8_PDES, lvl - 1);
 181                 } while (pde++, --count);
 182         }
 183
 184         free_px(vm, pd);
 185 }
 186
 187 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 188 {
 189         struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 190
 191         if (intel_vgpu_active(vm->i915))
 192                 gen8_ppgtt_notify_vgt(ppgtt, false);
 193
 194         __gen8_ppgtt_cleanup(vm, ppgtt->pd, gen8_pd_top_count(vm), vm->top);
 195         free_scratch(vm);
 196 }
 197
 198 static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm,
 199                               struct i915_page_directory * const pd,
 200                               u64 start, const u64 end, int lvl)
 201 {
 202         const struct i915_page_scratch * const scratch = &vm->scratch[lvl];
 203         unsigned int idx, len;
 204
 205         GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT);
 206
 207         len = gen8_pd_range(start, end, lvl--, &idx);
 208         DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
 209             __func__, vm, lvl + 1, start, end,
 210             idx, len, atomic_read(px_used(pd)));
 211         GEM_BUG_ON(!len || len >= atomic_read(px_used(pd)));
 212
 213         do {
 214                 struct i915_page_table *pt = pd->entry[idx];
 215
 216                 if (atomic_fetch_inc(&pt->used) >> gen8_pd_shift(1) &&
 217                     gen8_pd_contains(start, end, lvl)) {
 218                         DBG("%s(%p):{ lvl:%d, idx:%d, start:%llx, end:%llx } removing pd\n",
 219                             __func__, vm, lvl + 1, idx, start, end);
 220                         clear_pd_entry(pd, idx, scratch);
 221                         __gen8_ppgtt_cleanup(vm, as_pd(pt), I915_PDES, lvl);
 222                         start += (u64)I915_PDES << gen8_pd_shift(lvl);
 223                         continue;
 224                 }
 225
 226                 if (lvl) {
 227                         start = __gen8_ppgtt_clear(vm, as_pd(pt),
 228                                                    start, end, lvl);
 229                 } else {
 230                         unsigned int count;
 231                         u64 *vaddr;
 232
 233                         count = gen8_pt_count(start, end);
 234                         DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d } removing pte\n",
 235                             __func__, vm, lvl, start, end,
 236                             gen8_pd_index(start, 0), count,
 237                             atomic_read(&pt->used));
 238                         GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
 239
 240                         vaddr = kmap_atomic_px(pt);
 241                         memset64(vaddr + gen8_pd_index(start, 0),
 242                                  vm->scratch[0].encode,
 243                                  count);
 244                         kunmap_atomic(vaddr);
 245
 246                         atomic_sub(count, &pt->used);
 247                         start += count;
 248                 }
 249
 250                 if (release_pd_entry(pd, idx, pt, scratch))
 251                         free_px(vm, pt);
 252         } while (idx++, --len);
 253
 254         return start;
 255 }
 256
 257 static void gen8_ppgtt_clear(struct i915_address_space *vm,
 258                              u64 start, u64 length)
 259 {
 260         GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
 261         GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
 262         GEM_BUG_ON(range_overflows(start, length, vm->total));
 263
 264         start >>= GEN8_PTE_SHIFT;
 265         length >>= GEN8_PTE_SHIFT;
 266         GEM_BUG_ON(length == 0);
 267
 268         __gen8_ppgtt_clear(vm, i915_vm_to_ppgtt(vm)->pd,
 269                            start, start + length, vm->top);
 270 }
 271
 272 static void __gen8_ppgtt_alloc(struct i915_address_space * const vm,
 273                                struct i915_vm_pt_stash *stash,
 274                                struct i915_page_directory * const pd,
 275                                u64 * const start, const u64 end, int lvl)
 276 {
 277         unsigned int idx, len;
 278
 279         GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT);
 280
 281         len = gen8_pd_range(*start, end, lvl--, &idx);
 282         DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
 283             __func__, vm, lvl + 1, *start, end,
 284             idx, len, atomic_read(px_used(pd)));
 285         GEM_BUG_ON(!len || (idx + len - 1) >> gen8_pd_shift(1));
 286
 287         spin_lock(&pd->lock);
 288         GEM_BUG_ON(!atomic_read(px_used(pd))); /* Must be pinned! */
 289         do {
 290                 struct i915_page_table *pt = pd->entry[idx];
 291
 292                 if (!pt) {
 293                         spin_unlock(&pd->lock);
 294
 295                         DBG("%s(%p):{ lvl:%d, idx:%d } allocating new tree\n",
 296                             __func__, vm, lvl + 1, idx);
 297
 298                         pt = stash->pt[!!lvl];
 299                         GEM_BUG_ON(!pt);
 300
 301                         if (lvl ||
 302                             gen8_pt_count(*start, end) < I915_PDES ||
 303                             intel_vgpu_active(vm->i915))
 304                                 fill_px(pt, vm->scratch[lvl].encode);
 305
 306                         spin_lock(&pd->lock);
 307                         if (likely(!pd->entry[idx])) {
 308                                 stash->pt[!!lvl] = pt->stash;
 309                                 atomic_set(&pt->used, 0);
 310                                 set_pd_entry(pd, idx, pt);
 311                         } else {
 312                                 pt = pd->entry[idx];
 313                         }
 314                 }
 315
 316                 if (lvl) {
 317                         atomic_inc(&pt->used);
 318                         spin_unlock(&pd->lock);
 319
 320                         __gen8_ppgtt_alloc(vm, stash,
 321                                            as_pd(pt), start, end, lvl);
 322
 323                         spin_lock(&pd->lock);
 324                         atomic_dec(&pt->used);
 325                         GEM_BUG_ON(!atomic_read(&pt->used));
 326                 } else {
 327                         unsigned int count = gen8_pt_count(*start, end);
 328
 329                         DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d } inserting pte\n",
 330                             __func__, vm, lvl, *start, end,
 331                             gen8_pd_index(*start, 0), count,
 332                             atomic_read(&pt->used));
 333
 334                         atomic_add(count, &pt->used);
 335                         /* All other pdes may be simultaneously removed */
 336                         GEM_BUG_ON(atomic_read(&pt->used) > NALLOC * I915_PDES);
 337                         *start += count;
 338                 }
 339         } while (idx++, --len);
 340         spin_unlock(&pd->lock);
 341 }
 342
 343 static void gen8_ppgtt_alloc(struct i915_address_space *vm,
 344                              struct i915_vm_pt_stash *stash,
 345                              u64 start, u64 length)
 346 {
 347         GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
 348         GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
 349         GEM_BUG_ON(range_overflows(start, length, vm->total));
 350
 351         start >>= GEN8_PTE_SHIFT;
 352         length >>= GEN8_PTE_SHIFT;
 353         GEM_BUG_ON(length == 0);
 354
 355         __gen8_ppgtt_alloc(vm, stash, i915_vm_to_ppgtt(vm)->pd,
 356                            &start, start + length, vm->top);
 357 }
 358
 359 static __always_inline void
 360 write_pte(gen8_pte_t *pte, const gen8_pte_t val)
 361 {
 362         /* Magic delays? Or can we refine these to flush all in one pass? */
 363         *pte = val;
 364         wmb(); /* cpu to cache */
 365         clflush(pte); /* cache to memory */
 366         wmb(); /* visible to all */
 367 }
 368
 369 static __always_inline u64
 370 gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
 371                       struct i915_page_directory *pdp,
 372                       struct sgt_dma *iter,
 373                       u64 idx,
 374                       enum i915_cache_level cache_level,
 375                       u32 flags)
 376 {
 377         struct i915_page_directory *pd;
 378         const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
 379         gen8_pte_t *vaddr;
 380
 381         pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
 382         vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
 383         do {
 384                 GEM_BUG_ON(iter->sg->length < I915_GTT_PAGE_SIZE);
 385                 write_pte(&vaddr[gen8_pd_index(idx, 0)],
 386                           pte_encode | iter->dma);
 387
 388                 iter->dma += I915_GTT_PAGE_SIZE;
 389                 if (iter->dma >= iter->max) {
 390                         iter->sg = __sg_next(iter->sg);
 391                         if (!iter->sg) {
 392                                 idx = 0;
 393                                 break;
 394                         }
 395
 396                         iter->dma = sg_dma_address(iter->sg);
 397                         iter->max = iter->dma + iter->sg->length;
 398                 }
 399
 400                 if (gen8_pd_index(++idx, 0) == 0) {
 401                         if (gen8_pd_index(idx, 1) == 0) {
 402                                 /* Limited by sg length for 3lvl */
 403                                 if (gen8_pd_index(idx, 2) == 0)
 404                                         break;
 405
 406                                 pd = pdp->entry[gen8_pd_index(idx, 2)];
 407                         }
 408
 409                         kunmap_atomic(vaddr);
 410                         vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
 411                 }
 412         } while (1);
 413         kunmap_atomic(vaddr);
 414
 415         return idx;
 416 }
 417
 418 static void gen8_ppgtt_insert_huge(struct i915_vma *vma,
 419                                    struct sgt_dma *iter,
 420                                    enum i915_cache_level cache_level,
 421                                    u32 flags)
 422 {
 423         const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
 424         u64 start = vma->node.start;
 425         dma_addr_t rem = iter->sg->length;
 426
 427         GEM_BUG_ON(!i915_vm_is_4lvl(vma->vm));
 428
 429         do {
 430                 struct i915_page_directory * const pdp =
 431                         gen8_pdp_for_page_address(vma->vm, start);
 432                 struct i915_page_directory * const pd =
 433                         i915_pd_entry(pdp, __gen8_pte_index(start, 2));
 434                 gen8_pte_t encode = pte_encode;
 435                 unsigned int maybe_64K = -1;
 436                 unsigned int page_size;
 437                 gen8_pte_t *vaddr;
 438                 u16 index;
 439
 440                 if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
 441                     IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
 442                     rem >= I915_GTT_PAGE_SIZE_2M &&
 443                     !__gen8_pte_index(start, 0)) {
 444                         index = __gen8_pte_index(start, 1);
 445                         encode |= GEN8_PDE_PS_2M;
 446                         page_size = I915_GTT_PAGE_SIZE_2M;
 447
 448                         vaddr = kmap_atomic_px(pd);
 449                 } else {
 450                         struct i915_page_table *pt =
 451                                 i915_pt_entry(pd, __gen8_pte_index(start, 1));
 452
 453                         index = __gen8_pte_index(start, 0);
 454                         page_size = I915_GTT_PAGE_SIZE;
 455
 456                         if (!index &&
 457                             vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
 458                             IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
 459                             (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
 460                              rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))
 461                                 maybe_64K = __gen8_pte_index(start, 1);
 462
 463                         vaddr = kmap_atomic_px(pt);
 464                 }
 465
 466                 do {
 467                         GEM_BUG_ON(iter->sg->length < page_size);
 468                         write_pte(&vaddr[index++], encode | iter->dma);
 469
 470                         start += page_size;
 471                         iter->dma += page_size;
 472                         rem -= page_size;
 473                         if (iter->dma >= iter->max) {
 474                                 iter->sg = __sg_next(iter->sg);
 475                                 if (!iter->sg)
 476                                         break;
 477
 478                                 rem = iter->sg->length;
 479                                 iter->dma = sg_dma_address(iter->sg);
 480                                 iter->max = iter->dma + rem;
 481
 482                                 if (maybe_64K != -1 && index < I915_PDES &&
 483                                     !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
 484                                       (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
 485                                        rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE)))
 486                                         maybe_64K = -1;
 487
 488                                 if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
 489                                         break;
 490                         }
 491                 } while (rem >= page_size && index < I915_PDES);
 492
 493                 kunmap_atomic(vaddr);
 494
 495                 /*
 496                  * Is it safe to mark the 2M block as 64K? -- Either we have
 497                  * filled whole page-table with 64K entries, or filled part of
 498                  * it and have reached the end of the sg table and we have
 499                  * enough padding.
 500                  */
 501                 if (maybe_64K != -1 &&
 502                     (index == I915_PDES ||
 503                      (i915_vm_has_scratch_64K(vma->vm) &&
 504                       !iter->sg && IS_ALIGNED(vma->node.start +
 505                                               vma->node.size,
 506                                               I915_GTT_PAGE_SIZE_2M)))) {
 507                         vaddr = kmap_atomic_px(pd);
 508                         vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
 509                         kunmap_atomic(vaddr);
 510                         page_size = I915_GTT_PAGE_SIZE_64K;
 511
 512                         /*
 513                          * We write all 4K page entries, even when using 64K
 514                          * pages. In order to verify that the HW isn't cheating
 515                          * by using the 4K PTE instead of the 64K PTE, we want
 516                          * to remove all the surplus entries. If the HW skipped
 517                          * the 64K PTE, it will read/write into the scratch page
 518                          * instead - which we detect as missing results during
 519                          * selftests.
 520                          */
 521                         if (I915_SELFTEST_ONLY(vma->vm->scrub_64K)) {
 522                                 u16 i;
 523
 524                                 encode = vma->vm->scratch[0].encode;
 525                                 vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K));
 526
 527                                 for (i = 1; i < index; i += 16)
 528                                         memset64(vaddr + i, encode, 15);
 529
 530                                 kunmap_atomic(vaddr);
 531                         }
 532                 }
 533
 534                 vma->page_sizes.gtt |= page_size;
 535         } while (iter->sg);
 536 }
 537
 538 static void gen8_ppgtt_insert(struct i915_address_space *vm,
 539                               struct i915_vma *vma,
 540                               enum i915_cache_level cache_level,
 541                               u32 flags)
 542 {
 543         struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
 544         struct sgt_dma iter = sgt_dma(vma);
 545
 546         if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
 547                 gen8_ppgtt_insert_huge(vma, &iter, cache_level, flags);
 548         } else  {
 549                 u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
 550
 551                 do {
 552                         struct i915_page_directory * const pdp =
 553                                 gen8_pdp_for_page_index(vm, idx);
 554
 555                         idx = gen8_ppgtt_insert_pte(ppgtt, pdp, &iter, idx,
 556                                                     cache_level, flags);
 557                 } while (idx);
 558
 559                 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 560         }
 561 }
 562
 563 static int gen8_init_scratch(struct i915_address_space *vm)
 564 {
 565         int ret;
 566         int i;
 567
 568         /*
 569          * If everybody agrees to not to write into the scratch page,
 570          * we can reuse it for all vm, keeping contexts and processes separate.
 571          */
 572         if (vm->has_read_only && vm->gt->vm && !i915_is_ggtt(vm->gt->vm)) {
 573                 struct i915_address_space *clone = vm->gt->vm;
 574
 575                 GEM_BUG_ON(!clone->has_read_only);
 576
 577                 vm->scratch_order = clone->scratch_order;
 578                 memcpy(vm->scratch, clone->scratch, sizeof(vm->scratch));
 579                 px_dma(&vm->scratch[0]) = 0; /* no xfer of ownership */
 580                 return 0;
 581         }
 582
 583         ret = setup_scratch_page(vm, __GFP_HIGHMEM);
 584         if (ret)
 585                 return ret;
 586
 587         vm->scratch[0].encode =
 588                 gen8_pte_encode(px_dma(&vm->scratch[0]),
 589                                 I915_CACHE_LLC, vm->has_read_only);
 590
 591         for (i = 1; i <= vm->top; i++) {
 592                 if (unlikely(setup_page_dma(vm, px_base(&vm->scratch[i]))))
 593                         goto free_scratch;
 594
 595                 fill_px(&vm->scratch[i], vm->scratch[i - 1].encode);
 596                 vm->scratch[i].encode =
 597                         gen8_pde_encode(px_dma(&vm->scratch[i]),
 598                                         I915_CACHE_LLC);
 599         }
 600
 601         return 0;
 602
 603 free_scratch:
 604         free_scratch(vm);
 605         return -ENOMEM;
 606 }
 607
 608 static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
 609 {
 610         struct i915_address_space *vm = &ppgtt->vm;
 611         struct i915_page_directory *pd = ppgtt->pd;
 612         unsigned int idx;
 613
 614         GEM_BUG_ON(vm->top != 2);
 615         GEM_BUG_ON(gen8_pd_top_count(vm) != GEN8_3LVL_PDPES);
 616
 617         for (idx = 0; idx < GEN8_3LVL_PDPES; idx++) {
 618                 struct i915_page_directory *pde;
 619
 620                 pde = alloc_pd(vm);
 621                 if (IS_ERR(pde))
 622                         return PTR_ERR(pde);
 623
 624                 fill_px(pde, vm->scratch[1].encode);
 625                 set_pd_entry(pd, idx, pde);
 626                 atomic_inc(px_used(pde)); /* keep pinned */
 627         }
 628         wmb();
 629
 630         return 0;
 631 }
 632
 633 static struct i915_page_directory *
 634 gen8_alloc_top_pd(struct i915_address_space *vm)
 635 {
 636         const unsigned int count = gen8_pd_top_count(vm);
 637         struct i915_page_directory *pd;
 638
 639         GEM_BUG_ON(count > ARRAY_SIZE(pd->entry));
 640
 641         pd = __alloc_pd(offsetof(typeof(*pd), entry[count]));
 642         if (unlikely(!pd))
 643                 return ERR_PTR(-ENOMEM);
 644
 645         if (unlikely(setup_page_dma(vm, px_base(pd)))) {
 646                 kfree(pd);
 647                 return ERR_PTR(-ENOMEM);
 648         }
 649
 650         fill_page_dma(px_base(pd), vm->scratch[vm->top].encode, count);
 651         atomic_inc(px_used(pd)); /* mark as pinned */
 652         return pd;
 653 }
 654
 655 /*
 656  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 657  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 658  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 659  * space.
 660  *
 661  */
 662 struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
 663 {
 664         struct i915_ppgtt *ppgtt;
 665         int err;
 666
 667         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 668         if (!ppgtt)
 669                 return ERR_PTR(-ENOMEM);
 670
 671         ppgtt_init(ppgtt, gt);
 672         ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
 673         ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
 674
 675         /*
 676          * From bdw, there is hw support for read-only pages in the PPGTT.
 677          *
 678          * Gen11 has HSDES#:1807136187 unresolved. Disable ro support
 679          * for now.
 680          *
 681          * Gen12 has inherited the same read-only fault issue from gen11.
 682          */
 683         ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
 684
 685         /*
 686          * There are only few exceptions for gen >=6. chv and bxt.
 687          * And we are not sure about the latter so play safe for now.
 688          */
 689         if (IS_CHERRYVIEW(gt->i915) || IS_BROXTON(gt->i915))
 690                 ppgtt->vm.pt_kmap_wc = true;
 691
 692         err = gen8_init_scratch(&ppgtt->vm);
 693         if (err)
 694                 goto err_free;
 695
 696         ppgtt->pd = gen8_alloc_top_pd(&ppgtt->vm);
 697         if (IS_ERR(ppgtt->pd)) {
 698                 err = PTR_ERR(ppgtt->pd);
 699                 goto err_free_scratch;
 700         }
 701
 702         if (!i915_vm_is_4lvl(&ppgtt->vm)) {
 703                 err = gen8_preallocate_top_level_pdp(ppgtt);
 704                 if (err)
 705                         goto err_free_pd;
 706         }
 707
 708         ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
 709         ppgtt->vm.insert_entries = gen8_ppgtt_insert;
 710         ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
 711         ppgtt->vm.clear_range = gen8_ppgtt_clear;
 712
 713         ppgtt->vm.pte_encode = gen8_pte_encode;
 714
 715         if (intel_vgpu_active(gt->i915))
 716                 gen8_ppgtt_notify_vgt(ppgtt, true);
 717
 718         ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
 719
 720         return ppgtt;
 721
 722 err_free_pd:
 723         __gen8_ppgtt_cleanup(&ppgtt->vm, ppgtt->pd,
 724                              gen8_pd_top_count(&ppgtt->vm), ppgtt->vm.top);
 725 err_free_scratch:
 726         free_scratch(&ppgtt->vm);
 727 err_free:
 728         kfree(ppgtt);
 729         return ERR_PTR(err);
 730 }