1 // SPDX-License-Identifier: MIT
3 * Copyright © 2014 Intel Corporation
6 #include "gen8_engine_cs.h"
9 #include "intel_gpu_commands.h"
10 #include "intel_ring.h"
12 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
14 bool vf_flush_wa = false, dc_flush_wa = false;
18 flags |= PIPE_CONTROL_CS_STALL;
20 if (mode & EMIT_FLUSH) {
21 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
22 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
23 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
24 flags |= PIPE_CONTROL_FLUSH_ENABLE;
27 if (mode & EMIT_INVALIDATE) {
28 flags |= PIPE_CONTROL_TLB_INVALIDATE;
29 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
30 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
31 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
32 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
33 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
34 flags |= PIPE_CONTROL_QW_WRITE;
35 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
38 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
41 if (GRAPHICS_VER(rq->engine->i915) == 9)
44 /* WaForGAMHang:kbl */
45 if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0))
57 cs = intel_ring_begin(rq, len);
62 cs = gen8_emit_pipe_control(cs, 0, 0);
65 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
68 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
71 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
73 intel_ring_advance(rq, cs);
78 int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode)
82 cs = intel_ring_begin(rq, 4);
86 cmd = MI_FLUSH_DW + 1;
89 * We always require a command barrier so that subsequent
90 * commands, such as breadcrumb interrupts, are strictly ordered
91 * wrt the contents of the write cache being flushed to memory
92 * (and thus being coherent from the CPU).
94 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
96 if (mode & EMIT_INVALIDATE) {
97 cmd |= MI_INVALIDATE_TLB;
98 if (rq->engine->class == VIDEO_DECODE_CLASS)
99 cmd |= MI_INVALIDATE_BSD;
103 *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
104 *cs++ = 0; /* upper addr */
105 *cs++ = 0; /* value */
106 intel_ring_advance(rq, cs);
111 int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode)
113 if (mode & EMIT_FLUSH) {
117 flags |= PIPE_CONTROL_CS_STALL;
119 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
120 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
121 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
122 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
123 flags |= PIPE_CONTROL_FLUSH_ENABLE;
124 flags |= PIPE_CONTROL_QW_WRITE;
125 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
127 cs = intel_ring_begin(rq, 6);
131 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
132 intel_ring_advance(rq, cs);
135 if (mode & EMIT_INVALIDATE) {
139 flags |= PIPE_CONTROL_CS_STALL;
141 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
142 flags |= PIPE_CONTROL_TLB_INVALIDATE;
143 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
144 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
145 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
146 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
147 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148 flags |= PIPE_CONTROL_QW_WRITE;
149 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
151 cs = intel_ring_begin(rq, 6);
155 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
156 intel_ring_advance(rq, cs);
162 static u32 preparser_disable(bool state)
164 return MI_ARB_CHECK | 1 << 8 | state;
167 static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
169 static const i915_reg_t vd[] = {
176 static const i915_reg_t ve[] = {
181 if (engine->class == VIDEO_DECODE_CLASS)
182 return vd[engine->instance];
184 if (engine->class == VIDEO_ENHANCEMENT_CLASS)
185 return ve[engine->instance];
187 GEM_BUG_ON("unknown aux_inv reg\n");
188 return INVALID_MMIO_REG;
191 static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
193 *cs++ = MI_LOAD_REGISTER_IMM(1);
194 *cs++ = i915_mmio_reg_offset(inv_reg);
201 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
203 if (mode & EMIT_FLUSH) {
207 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
208 flags |= PIPE_CONTROL_FLUSH_L3;
209 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
210 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
211 /* Wa_1409600907:tgl */
212 flags |= PIPE_CONTROL_DEPTH_STALL;
213 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
214 flags |= PIPE_CONTROL_FLUSH_ENABLE;
216 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
217 flags |= PIPE_CONTROL_QW_WRITE;
219 flags |= PIPE_CONTROL_CS_STALL;
221 cs = intel_ring_begin(rq, 6);
225 cs = gen12_emit_pipe_control(cs,
226 PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
227 flags, LRC_PPHWSP_SCRATCH_ADDR);
228 intel_ring_advance(rq, cs);
231 if (mode & EMIT_INVALIDATE) {
235 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
236 flags |= PIPE_CONTROL_TLB_INVALIDATE;
237 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
238 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
239 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
244 flags |= PIPE_CONTROL_QW_WRITE;
246 flags |= PIPE_CONTROL_CS_STALL;
248 cs = intel_ring_begin(rq, 8 + 4);
253 * Prevent the pre-parser from skipping past the TLB
254 * invalidate and loading a stale page for the batch
255 * buffer / request payload.
257 *cs++ = preparser_disable(true);
259 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
261 /* hsdes: 1809175790 */
262 cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs);
264 *cs++ = preparser_disable(false);
265 intel_ring_advance(rq, cs);
271 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
273 intel_engine_mask_t aux_inv = 0;
277 if (mode & EMIT_INVALIDATE)
279 if (mode & EMIT_INVALIDATE)
280 aux_inv = rq->engine->mask & ~BIT(BCS0);
282 cmd += 2 * hweight8(aux_inv) + 2;
284 cs = intel_ring_begin(rq, cmd);
288 if (mode & EMIT_INVALIDATE)
289 *cs++ = preparser_disable(true);
291 cmd = MI_FLUSH_DW + 1;
294 * We always require a command barrier so that subsequent
295 * commands, such as breadcrumb interrupts, are strictly ordered
296 * wrt the contents of the write cache being flushed to memory
297 * (and thus being coherent from the CPU).
299 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
301 if (mode & EMIT_INVALIDATE) {
302 cmd |= MI_INVALIDATE_TLB;
303 if (rq->engine->class == VIDEO_DECODE_CLASS)
304 cmd |= MI_INVALIDATE_BSD;
308 *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
309 *cs++ = 0; /* upper addr */
310 *cs++ = 0; /* value */
312 if (aux_inv) { /* hsdes: 1809175790 */
313 struct intel_engine_cs *engine;
316 *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
317 for_each_engine_masked(engine, rq->engine->gt,
319 *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
325 if (mode & EMIT_INVALIDATE)
326 *cs++ = preparser_disable(false);
328 intel_ring_advance(rq, cs);
333 static u32 preempt_address(struct intel_engine_cs *engine)
335 return (i915_ggtt_offset(engine->status_page.vma) +
336 I915_GEM_HWS_PREEMPT_ADDR);
339 static u32 hwsp_offset(const struct i915_request *rq)
341 const struct intel_timeline *tl;
343 /* Before the request is executed, the timeline is fixed */
344 tl = rcu_dereference_protected(rq->timeline,
345 !i915_request_signaled(rq));
347 /* See the comment in i915_request_active_seqno(). */
348 return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno);
351 int gen8_emit_init_breadcrumb(struct i915_request *rq)
355 GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq));
356 if (!i915_request_timeline(rq)->has_initial_breadcrumb)
359 cs = intel_ring_begin(rq, 6);
363 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
364 *cs++ = hwsp_offset(rq);
366 *cs++ = rq->fence.seqno - 1;
369 * Check if we have been preempted before we even get started.
371 * After this point i915_request_started() reports true, even if
372 * we get preempted and so are no longer running.
374 * i915_request_started() is used during preemption processing
375 * to decide if the request is currently inside the user payload
376 * or spinning on a kernel semaphore (or earlier). For no-preemption
377 * requests, we do allow preemption on the semaphore before the user
378 * payload, but do not allow preemption once the request is started.
380 * i915_request_started() is similarly used during GPU hangs to
381 * determine if the user's payload was guilty, and if so, the
382 * request is banned. Before the request is started, it is assumed
383 * to be unharmed and an innocent victim of another's hang.
386 *cs++ = MI_ARB_CHECK;
388 intel_ring_advance(rq, cs);
390 /* Record the updated position of the request's payload */
391 rq->infix = intel_ring_offset(rq, cs);
393 __set_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);
398 int gen8_emit_bb_start_noarb(struct i915_request *rq,
400 const unsigned int flags)
404 cs = intel_ring_begin(rq, 4);
409 * WaDisableCtxRestoreArbitration:bdw,chv
411 * We don't need to perform MI_ARB_ENABLE as often as we do (in
412 * particular all the gen that do not need the w/a at all!), if we
413 * took care to make sure that on every switch into this context
414 * (both ordinary and for preemption) that arbitrartion was enabled
415 * we would be fine. However, for gen8 there is another w/a that
416 * requires us to not preempt inside GPGPU execution, so we keep
417 * arbitration disabled for gen8 batches. Arbitration will be
418 * re-enabled before we close the request
419 * (engine->emit_fini_breadcrumb).
421 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
423 /* FIXME(BDW+): Address space and security selectors. */
424 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
425 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
426 *cs++ = lower_32_bits(offset);
427 *cs++ = upper_32_bits(offset);
429 intel_ring_advance(rq, cs);
434 int gen8_emit_bb_start(struct i915_request *rq,
436 const unsigned int flags)
440 if (unlikely(i915_request_has_nopreempt(rq)))
441 return gen8_emit_bb_start_noarb(rq, offset, len, flags);
443 cs = intel_ring_begin(rq, 6);
447 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
449 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
450 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
451 *cs++ = lower_32_bits(offset);
452 *cs++ = upper_32_bits(offset);
454 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
457 intel_ring_advance(rq, cs);
462 static void assert_request_valid(struct i915_request *rq)
464 struct intel_ring *ring __maybe_unused = rq->ring;
466 /* Can we unwind this request without appearing to go forwards? */
467 GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0);
471 * Reserve space for 2 NOOPs at the end of each request to be
472 * used as a workaround for not being allowed to do lite
473 * restore with HEAD==TAIL (WaIdleLiteRestore).
475 static u32 *gen8_emit_wa_tail(struct i915_request *rq, u32 *cs)
477 /* Ensure there's always at least one preemption point per-request. */
478 *cs++ = MI_ARB_CHECK;
480 rq->wa_tail = intel_ring_offset(rq, cs);
482 /* Check that entire request is less than half the ring */
483 assert_request_valid(rq);
488 static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs)
490 *cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */
491 *cs++ = MI_SEMAPHORE_WAIT |
492 MI_SEMAPHORE_GLOBAL_GTT |
494 MI_SEMAPHORE_SAD_EQ_SDD;
496 *cs++ = preempt_address(rq->engine);
503 static __always_inline u32*
504 gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
506 *cs++ = MI_USER_INTERRUPT;
508 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
509 if (intel_engine_has_semaphores(rq->engine))
510 cs = emit_preempt_busywait(rq, cs);
512 rq->tail = intel_ring_offset(rq, cs);
513 assert_ring_tail_valid(rq->ring, rq->tail);
515 return gen8_emit_wa_tail(rq, cs);
518 static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
520 return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
523 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
525 return gen8_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
528 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
530 cs = gen8_emit_pipe_control(cs,
531 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
532 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
533 PIPE_CONTROL_DC_FLUSH_ENABLE,
536 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
537 cs = gen8_emit_ggtt_write_rcs(cs,
540 PIPE_CONTROL_FLUSH_ENABLE |
541 PIPE_CONTROL_CS_STALL);
543 return gen8_emit_fini_breadcrumb_tail(rq, cs);
546 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
548 cs = gen8_emit_ggtt_write_rcs(cs,
551 PIPE_CONTROL_CS_STALL |
552 PIPE_CONTROL_TILE_CACHE_FLUSH |
553 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
554 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
555 PIPE_CONTROL_DC_FLUSH_ENABLE |
556 PIPE_CONTROL_FLUSH_ENABLE);
558 return gen8_emit_fini_breadcrumb_tail(rq, cs);
562 * Note that the CS instruction pre-parser will not stall on the breadcrumb
563 * flush and will continue pre-fetching the instructions after it before the
564 * memory sync is completed. On pre-gen12 HW, the pre-parser will stop at
565 * BB_START/END instructions, so, even though we might pre-fetch the pre-amble
566 * of the next request before the memory has been flushed, we're guaranteed that
567 * we won't access the batch itself too early.
568 * However, on gen12+ the parser can pre-fetch across the BB_START/END commands,
569 * so, if the current request is modifying an instruction in the next request on
570 * the same intel_context, we might pre-fetch and then execute the pre-update
571 * instruction. To avoid this, the users of self-modifying code should either
572 * disable the parser around the code emitting the memory writes, via a new flag
573 * added to MI_ARB_CHECK, or emit the writes from a different intel_context. For
574 * the in-kernel use-cases we've opted to use a separate context, see
575 * reloc_gpu() as an example.
576 * All the above applies only to the instructions themselves. Non-inline data
577 * used by the instructions is not pre-fetched.
580 static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)
582 *cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */
583 *cs++ = MI_SEMAPHORE_WAIT_TOKEN |
584 MI_SEMAPHORE_GLOBAL_GTT |
586 MI_SEMAPHORE_SAD_EQ_SDD;
588 *cs++ = preempt_address(rq->engine);
595 static __always_inline u32*
596 gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
598 *cs++ = MI_USER_INTERRUPT;
600 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
601 if (intel_engine_has_semaphores(rq->engine))
602 cs = gen12_emit_preempt_busywait(rq, cs);
604 rq->tail = intel_ring_offset(rq, cs);
605 assert_ring_tail_valid(rq->ring, rq->tail);
607 return gen8_emit_wa_tail(rq, cs);
610 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
612 /* XXX Stalling flush before seqno write; post-sync not */
613 cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
614 return gen12_emit_fini_breadcrumb_tail(rq, cs);
617 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
619 cs = gen12_emit_ggtt_write_rcs(cs,
622 PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
623 PIPE_CONTROL_CS_STALL |
624 PIPE_CONTROL_TILE_CACHE_FLUSH |
625 PIPE_CONTROL_FLUSH_L3 |
626 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
627 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
628 /* Wa_1409600907:tgl */
629 PIPE_CONTROL_DEPTH_STALL |
630 PIPE_CONTROL_DC_FLUSH_ENABLE |
631 PIPE_CONTROL_FLUSH_ENABLE);
633 return gen12_emit_fini_breadcrumb_tail(rq, cs);