drivers/gpu/drm/i915/gt/gen6_ppgtt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <linux/log2.h>
   7
   8 #include "gen6_ppgtt.h"
   9 #include "i915_scatterlist.h"
  10 #include "i915_trace.h"
  11 #include "i915_vgpu.h"
  12 #include "intel_gt.h"
  13
  14 /* Write pde (index) from the page directory @pd to the page table @pt */
  15 static inline void gen6_write_pde(const struct gen6_ppgtt *ppgtt,
  16                                   const unsigned int pde,
  17                                   const struct i915_page_table *pt)
  18 {
  19         /* Caller needs to make sure the write completes if necessary */
  20         iowrite32(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
  21                   ppgtt->pd_addr + pde);
  22 }
  23
  24 void gen7_ppgtt_enable(struct intel_gt *gt)
  25 {
  26         struct drm_i915_private *i915 = gt->i915;
  27         struct intel_uncore *uncore = gt->uncore;
  28         struct intel_engine_cs *engine;
  29         enum intel_engine_id id;
  30         u32 ecochk;
  31
  32         intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
  33
  34         ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
  35         if (IS_HASWELL(i915)) {
  36                 ecochk |= ECOCHK_PPGTT_WB_HSW;
  37         } else {
  38                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
  39                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
  40         }
  41         intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
  42
  43         for_each_engine(engine, gt, id) {
  44                 /* GFX_MODE is per-ring on gen7+ */
  45                 ENGINE_WRITE(engine,
  46                              RING_MODE_GEN7,
  47                              _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
  48         }
  49 }
  50
  51 void gen6_ppgtt_enable(struct intel_gt *gt)
  52 {
  53         struct intel_uncore *uncore = gt->uncore;
  54
  55         intel_uncore_rmw(uncore,
  56                          GAC_ECO_BITS,
  57                          0,
  58                          ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
  59
  60         intel_uncore_rmw(uncore,
  61                          GAB_CTL,
  62                          0,
  63                          GAB_CTL_CONT_AFTER_PAGEFAULT);
  64
  65         intel_uncore_rmw(uncore,
  66                          GAM_ECOCHK,
  67                          0,
  68                          ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
  69
  70         if (HAS_PPGTT(uncore->i915)) /* may be disabled for VT-d */
  71                 intel_uncore_write(uncore,
  72                                    GFX_MODE,
  73                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
  74 }
  75
  76 /* PPGTT support for Sandybdrige/Gen6 and later */
  77 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
  78                                    u64 start, u64 length)
  79 {
  80         struct gen6_ppgtt * const ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
  81         const unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
  82         const gen6_pte_t scratch_pte = vm->scratch[0].encode;
  83         unsigned int pde = first_entry / GEN6_PTES;
  84         unsigned int pte = first_entry % GEN6_PTES;
  85         unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
  86
  87         while (num_entries) {
  88                 struct i915_page_table * const pt =
  89                         i915_pt_entry(ppgtt->base.pd, pde++);
  90                 const unsigned int count = min(num_entries, GEN6_PTES - pte);
  91                 gen6_pte_t *vaddr;
  92
  93                 GEM_BUG_ON(px_base(pt) == px_base(&vm->scratch[1]));
  94
  95                 num_entries -= count;
  96
  97                 GEM_BUG_ON(count > atomic_read(&pt->used));
  98                 if (!atomic_sub_return(count, &pt->used))
  99                         ppgtt->scan_for_unused_pt = true;
 100
 101                 /*
 102                  * Note that the hw doesn't support removing PDE on the fly
 103                  * (they are cached inside the context with no means to
 104                  * invalidate the cache), so we can only reset the PTE
 105                  * entries back to scratch.
 106                  */
 107
 108                 vaddr = kmap_atomic_px(pt);
 109                 memset32(vaddr + pte, scratch_pte, count);
 110                 kunmap_atomic(vaddr);
 111
 112                 pte = 0;
 113         }
 114 }
 115
 116 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 117                                       struct i915_vma *vma,
 118                                       enum i915_cache_level cache_level,
 119                                       u32 flags)
 120 {
 121         struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 122         struct i915_page_directory * const pd = ppgtt->pd;
 123         unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
 124         unsigned int act_pt = first_entry / GEN6_PTES;
 125         unsigned int act_pte = first_entry % GEN6_PTES;
 126         const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
 127         struct sgt_dma iter = sgt_dma(vma);
 128         gen6_pte_t *vaddr;
 129
 130         GEM_BUG_ON(pd->entry[act_pt] == &vm->scratch[1]);
 131
 132         vaddr = kmap_atomic_px(i915_pt_entry(pd, act_pt));
 133         do {
 134                 GEM_BUG_ON(iter.sg->length < I915_GTT_PAGE_SIZE);
 135                 vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
 136
 137                 iter.dma += I915_GTT_PAGE_SIZE;
 138                 if (iter.dma == iter.max) {
 139                         iter.sg = __sg_next(iter.sg);
 140                         if (!iter.sg)
 141                                 break;
 142
 143                         iter.dma = sg_dma_address(iter.sg);
 144                         iter.max = iter.dma + iter.sg->length;
 145                 }
 146
 147                 if (++act_pte == GEN6_PTES) {
 148                         kunmap_atomic(vaddr);
 149                         vaddr = kmap_atomic_px(i915_pt_entry(pd, ++act_pt));
 150                         act_pte = 0;
 151                 }
 152         } while (1);
 153         kunmap_atomic(vaddr);
 154
 155         vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 156 }
 157
 158 static void gen6_flush_pd(struct gen6_ppgtt *ppgtt, u64 start, u64 end)
 159 {
 160         struct i915_page_directory * const pd = ppgtt->base.pd;
 161         struct i915_page_table *pt;
 162         unsigned int pde;
 163
 164         start = round_down(start, SZ_64K);
 165         end = round_up(end, SZ_64K) - start;
 166
 167         mutex_lock(&ppgtt->flush);
 168
 169         gen6_for_each_pde(pt, pd, start, end, pde)
 170                 gen6_write_pde(ppgtt, pde, pt);
 171
 172         mb();
 173         ioread32(ppgtt->pd_addr + pde - 1);
 174         gen6_ggtt_invalidate(ppgtt->base.vm.gt->ggtt);
 175         mb();
 176
 177         mutex_unlock(&ppgtt->flush);
 178 }
 179
 180 static void gen6_alloc_va_range(struct i915_address_space *vm,
 181                                 struct i915_vm_pt_stash *stash,
 182                                 u64 start, u64 length)
 183 {
 184         struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
 185         struct i915_page_directory * const pd = ppgtt->base.pd;
 186         struct i915_page_table *pt;
 187         bool flush = false;
 188         u64 from = start;
 189         unsigned int pde;
 190
 191         spin_lock(&pd->lock);
 192         gen6_for_each_pde(pt, pd, start, length, pde) {
 193                 const unsigned int count = gen6_pte_count(start, length);
 194
 195                 if (px_base(pt) == px_base(&vm->scratch[1])) {
 196                         spin_unlock(&pd->lock);
 197
 198                         pt = stash->pt[0];
 199                         GEM_BUG_ON(!pt);
 200
 201                         fill32_px(pt, vm->scratch[0].encode);
 202
 203                         spin_lock(&pd->lock);
 204                         if (pd->entry[pde] == &vm->scratch[1]) {
 205                                 stash->pt[0] = pt->stash;
 206                                 atomic_set(&pt->used, 0);
 207                                 pd->entry[pde] = pt;
 208                         } else {
 209                                 pt = pd->entry[pde];
 210                         }
 211
 212                         flush = true;
 213                 }
 214
 215                 atomic_add(count, &pt->used);
 216         }
 217         spin_unlock(&pd->lock);
 218
 219         if (flush && i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND)) {
 220                 intel_wakeref_t wakeref;
 221
 222                 with_intel_runtime_pm(&vm->i915->runtime_pm, wakeref)
 223                         gen6_flush_pd(ppgtt, from, start);
 224         }
 225 }
 226
 227 static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt)
 228 {
 229         struct i915_address_space * const vm = &ppgtt->base.vm;
 230         struct i915_page_directory * const pd = ppgtt->base.pd;
 231         int ret;
 232
 233         ret = setup_scratch_page(vm, __GFP_HIGHMEM);
 234         if (ret)
 235                 return ret;
 236
 237         vm->scratch[0].encode =
 238                 vm->pte_encode(px_dma(&vm->scratch[0]),
 239                                I915_CACHE_NONE, PTE_READ_ONLY);
 240
 241         if (unlikely(setup_page_dma(vm, px_base(&vm->scratch[1])))) {
 242                 cleanup_scratch_page(vm);
 243                 return -ENOMEM;
 244         }
 245
 246         fill32_px(&vm->scratch[1], vm->scratch[0].encode);
 247         memset_p(pd->entry, &vm->scratch[1], I915_PDES);
 248
 249         return 0;
 250 }
 251
 252 static void gen6_ppgtt_free_pd(struct gen6_ppgtt *ppgtt)
 253 {
 254         struct i915_page_directory * const pd = ppgtt->base.pd;
 255         struct i915_page_dma * const scratch =
 256                 px_base(&ppgtt->base.vm.scratch[1]);
 257         struct i915_page_table *pt;
 258         u32 pde;
 259
 260         gen6_for_all_pdes(pt, pd, pde)
 261                 if (px_base(pt) != scratch)
 262                         free_px(&ppgtt->base.vm, pt);
 263 }
 264
 265 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 266 {
 267         struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
 268
 269         __i915_vma_put(ppgtt->vma);
 270
 271         gen6_ppgtt_free_pd(ppgtt);
 272         free_scratch(vm);
 273
 274         mutex_destroy(&ppgtt->flush);
 275         mutex_destroy(&ppgtt->pin_mutex);
 276         kfree(ppgtt->base.pd);
 277 }
 278
 279 static int pd_vma_set_pages(struct i915_vma *vma)
 280 {
 281         vma->pages = ERR_PTR(-ENODEV);
 282         return 0;
 283 }
 284
 285 static void pd_vma_clear_pages(struct i915_vma *vma)
 286 {
 287         GEM_BUG_ON(!vma->pages);
 288
 289         vma->pages = NULL;
 290 }
 291
 292 static void pd_vma_bind(struct i915_address_space *vm,
 293                         struct i915_vm_pt_stash *stash,
 294                         struct i915_vma *vma,
 295                         enum i915_cache_level cache_level,
 296                         u32 unused)
 297 {
 298         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
 299         struct gen6_ppgtt *ppgtt = vma->private;
 300         u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE;
 301
 302         px_base(ppgtt->base.pd)->ggtt_offset = ggtt_offset * sizeof(gen6_pte_t);
 303         ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + ggtt_offset;
 304
 305         gen6_flush_pd(ppgtt, 0, ppgtt->base.vm.total);
 306 }
 307
 308 static void pd_vma_unbind(struct i915_address_space *vm, struct i915_vma *vma)
 309 {
 310         struct gen6_ppgtt *ppgtt = vma->private;
 311         struct i915_page_directory * const pd = ppgtt->base.pd;
 312         struct i915_page_dma * const scratch =
 313                 px_base(&ppgtt->base.vm.scratch[1]);
 314         struct i915_page_table *pt;
 315         unsigned int pde;
 316
 317         if (!ppgtt->scan_for_unused_pt)
 318                 return;
 319
 320         /* Free all no longer used page tables */
 321         gen6_for_all_pdes(pt, ppgtt->base.pd, pde) {
 322                 if (px_base(pt) == scratch || atomic_read(&pt->used))
 323                         continue;
 324
 325                 free_px(&ppgtt->base.vm, pt);
 326                 pd->entry[pde] = scratch;
 327         }
 328
 329         ppgtt->scan_for_unused_pt = false;
 330 }
 331
 332 static const struct i915_vma_ops pd_vma_ops = {
 333         .set_pages = pd_vma_set_pages,
 334         .clear_pages = pd_vma_clear_pages,
 335         .bind_vma = pd_vma_bind,
 336         .unbind_vma = pd_vma_unbind,
 337 };
 338
 339 static struct i915_vma *pd_vma_create(struct gen6_ppgtt *ppgtt, int size)
 340 {
 341         struct i915_ggtt *ggtt = ppgtt->base.vm.gt->ggtt;
 342         struct i915_vma *vma;
 343
 344         GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
 345         GEM_BUG_ON(size > ggtt->vm.total);
 346
 347         vma = i915_vma_alloc();
 348         if (!vma)
 349                 return ERR_PTR(-ENOMEM);
 350
 351         i915_active_init(&vma->active, NULL, NULL);
 352
 353         kref_init(&vma->ref);
 354         mutex_init(&vma->pages_mutex);
 355         vma->vm = i915_vm_get(&ggtt->vm);
 356         vma->ops = &pd_vma_ops;
 357         vma->private = ppgtt;
 358
 359         vma->size = size;
 360         vma->fence_size = size;
 361         atomic_set(&vma->flags, I915_VMA_GGTT);
 362         vma->ggtt_view.type = I915_GGTT_VIEW_ROTATED; /* prevent fencing */
 363
 364         INIT_LIST_HEAD(&vma->obj_link);
 365         INIT_LIST_HEAD(&vma->closed_link);
 366
 367         return vma;
 368 }
 369
 370 int gen6_ppgtt_pin(struct i915_ppgtt *base)
 371 {
 372         struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
 373         int err;
 374
 375         GEM_BUG_ON(!atomic_read(&ppgtt->base.vm.open));
 376
 377         /*
 378          * Workaround the limited maximum vma->pin_count and the aliasing_ppgtt
 379          * which will be pinned into every active context.
 380          * (When vma->pin_count becomes atomic, I expect we will naturally
 381          * need a larger, unpacked, type and kill this redundancy.)
 382          */
 383         if (atomic_add_unless(&ppgtt->pin_count, 1, 0))
 384                 return 0;
 385
 386         if (mutex_lock_interruptible(&ppgtt->pin_mutex))
 387                 return -EINTR;
 388
 389         /*
 390          * PPGTT PDEs reside in the GGTT and consists of 512 entries. The
 391          * allocator works in address space sizes, so it's multiplied by page
 392          * size. We allocate at the top of the GTT to avoid fragmentation.
 393          */
 394         err = 0;
 395         if (!atomic_read(&ppgtt->pin_count))
 396                 err = i915_ggtt_pin(ppgtt->vma, GEN6_PD_ALIGN, PIN_HIGH);
 397         if (!err)
 398                 atomic_inc(&ppgtt->pin_count);
 399         mutex_unlock(&ppgtt->pin_mutex);
 400
 401         return err;
 402 }
 403
 404 void gen6_ppgtt_unpin(struct i915_ppgtt *base)
 405 {
 406         struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
 407
 408         GEM_BUG_ON(!atomic_read(&ppgtt->pin_count));
 409         if (atomic_dec_and_test(&ppgtt->pin_count))
 410                 i915_vma_unpin(ppgtt->vma);
 411 }
 412
 413 void gen6_ppgtt_unpin_all(struct i915_ppgtt *base)
 414 {
 415         struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base);
 416
 417         if (!atomic_read(&ppgtt->pin_count))
 418                 return;
 419
 420         i915_vma_unpin(ppgtt->vma);
 421         atomic_set(&ppgtt->pin_count, 0);
 422 }
 423
 424 struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
 425 {
 426         struct i915_ggtt * const ggtt = gt->ggtt;
 427         struct gen6_ppgtt *ppgtt;
 428         int err;
 429
 430         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 431         if (!ppgtt)
 432                 return ERR_PTR(-ENOMEM);
 433
 434         mutex_init(&ppgtt->flush);
 435         mutex_init(&ppgtt->pin_mutex);
 436
 437         ppgtt_init(&ppgtt->base, gt);
 438         ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
 439         ppgtt->base.vm.top = 1;
 440
 441         ppgtt->base.vm.bind_async_flags = I915_VMA_LOCAL_BIND;
 442         ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
 443         ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
 444         ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
 445         ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
 446
 447         ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
 448
 449         ppgtt->base.pd = __alloc_pd(sizeof(*ppgtt->base.pd));
 450         if (!ppgtt->base.pd) {
 451                 err = -ENOMEM;
 452                 goto err_free;
 453         }
 454
 455         err = gen6_ppgtt_init_scratch(ppgtt);
 456         if (err)
 457                 goto err_pd;
 458
 459         ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
 460         if (IS_ERR(ppgtt->vma)) {
 461                 err = PTR_ERR(ppgtt->vma);
 462                 goto err_scratch;
 463         }
 464
 465         return &ppgtt->base;
 466
 467 err_scratch:
 468         free_scratch(&ppgtt->base.vm);
 469 err_pd:
 470         kfree(ppgtt->base.pd);
 471 err_free:
 472         mutex_destroy(&ppgtt->pin_mutex);
 473         kfree(ppgtt);
 474         return ERR_PTR(err);
 475 }