2 * SPDX-License-Identifier: MIT
4 * Copyright © 2016 Intel Corporation
7 #include <linux/highmem.h>
8 #include <linux/prime_numbers.h>
10 #include "gem/i915_gem_internal.h"
11 #include "gem/i915_gem_lmem.h"
12 #include "gem/i915_gem_region.h"
13 #include "gem/i915_gem_ttm.h"
14 #include "gem/i915_gem_ttm_move.h"
15 #include "gt/intel_engine_pm.h"
16 #include "gt/intel_gpu_commands.h"
17 #include "gt/intel_gt.h"
18 #include "gt/intel_gt_pm.h"
19 #include "gt/intel_migrate.h"
21 #include "i915_ttm_buddy_manager.h"
23 #include "huge_gem_object.h"
24 #include "i915_selftest.h"
25 #include "selftests/i915_random.h"
26 #include "selftests/igt_flush_test.h"
27 #include "selftests/igt_reset.h"
28 #include "selftests/igt_mmap.h"
39 static u64 swizzle_bit(unsigned int bit, u64 offset)
41 return (offset & BIT_ULL(bit)) >> (bit - 6);
44 static u64 tiled_offset(const struct tile *tile, u64 v)
48 if (tile->tiling == I915_TILING_NONE)
51 y = div64_u64_rem(v, tile->stride, &x);
52 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
54 if (tile->tiling == I915_TILING_X) {
56 v += div64_u64_rem(x, tile->width, &x) << tile->size;
58 } else if (tile->width == 128) {
59 const unsigned int ytile_span = 16;
60 const unsigned int ytile_height = 512;
63 v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
66 const unsigned int ytile_span = 32;
67 const unsigned int ytile_height = 256;
70 v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
74 switch (tile->swizzle) {
75 case I915_BIT_6_SWIZZLE_9:
76 v ^= swizzle_bit(9, v);
78 case I915_BIT_6_SWIZZLE_9_10:
79 v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v);
81 case I915_BIT_6_SWIZZLE_9_11:
82 v ^= swizzle_bit(9, v) ^ swizzle_bit(11, v);
84 case I915_BIT_6_SWIZZLE_9_10_11:
85 v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v) ^ swizzle_bit(11, v);
92 static int check_partial_mapping(struct drm_i915_gem_object *obj,
93 const struct tile *tile,
94 struct rnd_state *prng)
96 const unsigned long npages = obj->base.size / PAGE_SIZE;
97 struct drm_i915_private *i915 = to_i915(obj->base.dev);
98 struct i915_gtt_view view;
100 unsigned long offset;
108 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
110 pr_err("Failed to set tiling mode=%u, stride=%u, err=%d\n",
111 tile->tiling, tile->stride, err);
115 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
116 GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
118 i915_gem_object_lock(obj, NULL);
119 err = i915_gem_object_set_to_gtt_domain(obj, true);
120 i915_gem_object_unlock(obj);
122 pr_err("Failed to flush to GTT write domain; err=%d\n", err);
126 page = i915_prandom_u32_max_state(npages, prng);
127 view = compute_partial_view(obj, page, MIN_CHUNK_PAGES);
129 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
131 pr_err("Failed to pin partial view: offset=%lu; err=%d\n",
132 page, (int)PTR_ERR(vma));
136 n = page - view.partial.offset;
137 GEM_BUG_ON(n >= view.partial.size);
139 io = i915_vma_pin_iomap(vma);
142 pr_err("Failed to iomap partial view: offset=%lu; err=%d\n",
143 page, (int)PTR_ERR(io));
148 iowrite32(page, io + n * PAGE_SIZE / sizeof(*io));
149 i915_vma_unpin_iomap(vma);
151 offset = tiled_offset(tile, page << PAGE_SHIFT);
152 if (offset >= obj->base.size)
155 intel_gt_flush_ggtt_writes(to_gt(i915));
157 p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
158 cpu = kmap(p) + offset_in_page(offset);
159 drm_clflush_virt_range(cpu, sizeof(*cpu));
160 if (*cpu != (u32)page) {
161 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%lu + %u [0x%lx]) of 0x%x, found 0x%x\n",
165 vma->size >> PAGE_SHIFT,
166 tile->tiling ? tile_row_pages(obj) : 0,
167 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
168 offset >> PAGE_SHIFT,
169 (unsigned int)offset_in_page(offset),
175 drm_clflush_virt_range(cpu, sizeof(*cpu));
179 i915_gem_object_lock(obj, NULL);
180 i915_vma_destroy(vma);
181 i915_gem_object_unlock(obj);
185 static int check_partial_mappings(struct drm_i915_gem_object *obj,
186 const struct tile *tile,
187 unsigned long end_time)
189 const unsigned int nreal = obj->scratch / PAGE_SIZE;
190 const unsigned long npages = obj->base.size / PAGE_SIZE;
191 struct drm_i915_private *i915 = to_i915(obj->base.dev);
192 struct i915_vma *vma;
196 err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
198 pr_err("Failed to set tiling mode=%u, stride=%u, err=%d\n",
199 tile->tiling, tile->stride, err);
203 GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
204 GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
206 i915_gem_object_lock(obj, NULL);
207 err = i915_gem_object_set_to_gtt_domain(obj, true);
208 i915_gem_object_unlock(obj);
210 pr_err("Failed to flush to GTT write domain; err=%d\n", err);
214 for_each_prime_number_from(page, 1, npages) {
215 struct i915_gtt_view view =
216 compute_partial_view(obj, page, MIN_CHUNK_PAGES);
217 unsigned long offset;
223 GEM_BUG_ON(view.partial.size > nreal);
226 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
228 pr_err("Failed to pin partial view: offset=%lu; err=%d\n",
229 page, (int)PTR_ERR(vma));
233 n = page - view.partial.offset;
234 GEM_BUG_ON(n >= view.partial.size);
236 io = i915_vma_pin_iomap(vma);
239 pr_err("Failed to iomap partial view: offset=%lu; err=%d\n",
240 page, (int)PTR_ERR(io));
244 iowrite32(page, io + n * PAGE_SIZE / sizeof(*io));
245 i915_vma_unpin_iomap(vma);
247 offset = tiled_offset(tile, page << PAGE_SHIFT);
248 if (offset >= obj->base.size)
251 intel_gt_flush_ggtt_writes(to_gt(i915));
253 p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
254 cpu = kmap(p) + offset_in_page(offset);
255 drm_clflush_virt_range(cpu, sizeof(*cpu));
256 if (*cpu != (u32)page) {
257 pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%lu + %u [0x%lx]) of 0x%x, found 0x%x\n",
261 vma->size >> PAGE_SHIFT,
262 tile->tiling ? tile_row_pages(obj) : 0,
263 vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
264 offset >> PAGE_SHIFT,
265 (unsigned int)offset_in_page(offset),
271 drm_clflush_virt_range(cpu, sizeof(*cpu));
276 i915_gem_object_lock(obj, NULL);
277 i915_vma_destroy(vma);
278 i915_gem_object_unlock(obj);
280 if (igt_timeout(end_time,
281 "%s: timed out after tiling=%d stride=%d\n",
282 __func__, tile->tiling, tile->stride))
290 setup_tile_size(struct tile *tile, struct drm_i915_private *i915)
292 if (GRAPHICS_VER(i915) <= 2) {
296 } else if (tile->tiling == I915_TILING_Y &&
297 HAS_128_BYTE_Y_TILING(i915)) {
307 if (GRAPHICS_VER(i915) < 4)
308 return 8192 / tile->width;
309 else if (GRAPHICS_VER(i915) < 7)
310 return 128 * I965_FENCE_MAX_PITCH_VAL / tile->width;
312 return 128 * GEN7_FENCE_MAX_PITCH_VAL / tile->width;
315 static int igt_partial_tiling(void *arg)
317 const unsigned int nreal = 1 << 12; /* largest tile row x2 */
318 struct drm_i915_private *i915 = arg;
319 struct drm_i915_gem_object *obj;
320 intel_wakeref_t wakeref;
324 if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
327 /* We want to check the page mapping and fencing of a large object
328 * mmapped through the GTT. The object we create is larger than can
329 * possibly be mmaped as a whole, and so we must use partial GGTT vma.
330 * We then check that a write through each partial GGTT vma ends up
331 * in the right set of pages within the object, and with the expected
332 * tiling, which we verify by manual swizzling.
335 obj = huge_gem_object(i915,
337 (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
341 err = i915_gem_object_pin_pages_unlocked(obj);
343 pr_err("Failed to allocate %u pages (%lu total), err=%d\n",
344 nreal, obj->base.size / PAGE_SIZE, err);
348 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
358 tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
359 tile.tiling = I915_TILING_NONE;
361 err = check_partial_mappings(obj, &tile, end);
362 if (err && err != -EINTR)
366 for (tiling = I915_TILING_X; tiling <= I915_TILING_Y; tiling++) {
368 unsigned int max_pitch;
372 if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
374 * The swizzling pattern is actually unknown as it
375 * varies based on physical address of each page.
376 * See i915_gem_detect_bit_6_swizzle().
380 tile.tiling = tiling;
383 tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;
386 tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;
390 GEM_BUG_ON(tile.swizzle == I915_BIT_6_SWIZZLE_UNKNOWN);
391 if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||
392 tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
395 max_pitch = setup_tile_size(&tile, i915);
397 for (pitch = max_pitch; pitch; pitch >>= 1) {
398 tile.stride = tile.width * pitch;
399 err = check_partial_mappings(obj, &tile, end);
405 if (pitch > 2 && GRAPHICS_VER(i915) >= 4) {
406 tile.stride = tile.width * (pitch - 1);
407 err = check_partial_mappings(obj, &tile, end);
414 if (pitch < max_pitch && GRAPHICS_VER(i915) >= 4) {
415 tile.stride = tile.width * (pitch + 1);
416 err = check_partial_mappings(obj, &tile, end);
424 if (GRAPHICS_VER(i915) >= 4) {
425 for_each_prime_number(pitch, max_pitch) {
426 tile.stride = tile.width * pitch;
427 err = check_partial_mappings(obj, &tile, end);
439 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
440 i915_gem_object_unpin_pages(obj);
442 i915_gem_object_put(obj);
446 static int igt_smoke_tiling(void *arg)
448 const unsigned int nreal = 1 << 12; /* largest tile row x2 */
449 struct drm_i915_private *i915 = arg;
450 struct drm_i915_gem_object *obj;
451 intel_wakeref_t wakeref;
452 I915_RND_STATE(prng);
457 if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
461 * igt_partial_tiling() does an exhastive check of partial tiling
462 * chunking, but will undoubtably run out of time. Here, we do a
463 * randomised search and hope over many runs of 1s with different
464 * seeds we will do a thorough check.
466 * Remember to look at the st_seed if we see a flip-flop in BAT!
469 if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
472 obj = huge_gem_object(i915,
474 (1 + next_prime_number(to_gt(i915)->ggtt->vm.total >> PAGE_SHIFT)) << PAGE_SHIFT);
478 err = i915_gem_object_pin_pages_unlocked(obj);
480 pr_err("Failed to allocate %u pages (%lu total), err=%d\n",
481 nreal, obj->base.size / PAGE_SIZE, err);
485 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
492 i915_prandom_u32_max_state(I915_TILING_Y + 1, &prng);
493 switch (tile.tiling) {
494 case I915_TILING_NONE:
499 tile.swizzle = I915_BIT_6_SWIZZLE_NONE;
503 tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_x;
506 tile.swizzle = to_gt(i915)->ggtt->bit_6_swizzle_y;
510 if (tile.swizzle == I915_BIT_6_SWIZZLE_9_17 ||
511 tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
514 if (tile.tiling != I915_TILING_NONE) {
515 unsigned int max_pitch = setup_tile_size(&tile, i915);
518 i915_prandom_u32_max_state(max_pitch, &prng);
519 tile.stride = (1 + tile.stride) * tile.width;
520 if (GRAPHICS_VER(i915) < 4)
521 tile.stride = rounddown_pow_of_two(tile.stride);
524 err = check_partial_mapping(obj, &tile, &prng);
529 } while (!__igt_timeout(end, NULL));
531 pr_info("%s: Completed %lu trials\n", __func__, count);
533 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
534 i915_gem_object_unpin_pages(obj);
536 i915_gem_object_put(obj);
540 static int make_obj_busy(struct drm_i915_gem_object *obj)
542 struct drm_i915_private *i915 = to_i915(obj->base.dev);
543 struct intel_engine_cs *engine;
545 for_each_uabi_engine(engine, i915) {
546 struct i915_request *rq;
547 struct i915_vma *vma;
548 struct i915_gem_ww_ctx ww;
551 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
555 i915_gem_ww_ctx_init(&ww, false);
557 err = i915_gem_object_lock(obj, &ww);
559 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER);
563 rq = intel_engine_create_kernel_request(engine);
569 err = i915_vma_move_to_active(vma, rq,
572 i915_request_add(rq);
576 if (err == -EDEADLK) {
577 err = i915_gem_ww_ctx_backoff(&ww);
581 i915_gem_ww_ctx_fini(&ww);
586 i915_gem_object_put(obj); /* leave it only alive via its active ref */
590 static enum i915_mmap_type default_mapping(struct drm_i915_private *i915)
593 return I915_MMAP_TYPE_FIXED;
595 return I915_MMAP_TYPE_GTT;
598 static struct drm_i915_gem_object *
599 create_sys_or_internal(struct drm_i915_private *i915,
602 if (HAS_LMEM(i915)) {
603 struct intel_memory_region *sys_region =
604 i915->mm.regions[INTEL_REGION_SMEM];
606 return __i915_gem_object_create_user(i915, size, &sys_region, 1);
609 return i915_gem_object_create_internal(i915, size);
612 static bool assert_mmap_offset(struct drm_i915_private *i915,
616 struct drm_i915_gem_object *obj;
620 obj = create_sys_or_internal(i915, size);
622 return expected && expected == PTR_ERR(obj);
624 ret = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
625 i915_gem_object_put(obj);
627 return ret == expected;
630 static void disable_retire_worker(struct drm_i915_private *i915)
632 i915_gem_driver_unregister__shrinker(i915);
633 intel_gt_pm_get(to_gt(i915));
634 cancel_delayed_work_sync(&to_gt(i915)->requests.retire_work);
637 static void restore_retire_worker(struct drm_i915_private *i915)
639 igt_flush_test(i915);
640 intel_gt_pm_put(to_gt(i915));
641 i915_gem_driver_register__shrinker(i915);
644 static void mmap_offset_lock(struct drm_i915_private *i915)
645 __acquires(&i915->drm.vma_offset_manager->vm_lock)
647 write_lock(&i915->drm.vma_offset_manager->vm_lock);
650 static void mmap_offset_unlock(struct drm_i915_private *i915)
651 __releases(&i915->drm.vma_offset_manager->vm_lock)
653 write_unlock(&i915->drm.vma_offset_manager->vm_lock);
656 static int igt_mmap_offset_exhaustion(void *arg)
658 struct drm_i915_private *i915 = arg;
659 struct drm_mm *mm = &i915->drm.vma_offset_manager->vm_addr_space_mm;
660 struct drm_i915_gem_object *obj;
661 struct drm_mm_node *hole, *next;
664 int enospc = HAS_LMEM(i915) ? -ENXIO : -ENOSPC;
666 /* Disable background reaper */
667 disable_retire_worker(i915);
668 GEM_BUG_ON(!to_gt(i915)->awake);
669 intel_gt_retire_requests(to_gt(i915));
670 i915_gem_drain_freed_objects(i915);
672 /* Trim the device mmap space to only a page */
673 mmap_offset_lock(i915);
674 loop = 1; /* PAGE_SIZE units */
675 list_for_each_entry_safe(hole, next, &mm->hole_stack, hole_stack) {
676 struct drm_mm_node *resv;
678 resv = kzalloc(sizeof(*resv), GFP_NOWAIT);
684 resv->start = drm_mm_hole_node_start(hole) + loop;
685 resv->size = hole->hole_size - loop;
694 pr_debug("Reserving hole [%llx + %llx]\n",
695 resv->start, resv->size);
697 err = drm_mm_reserve_node(mm, resv);
699 pr_err("Failed to trim VMA manager, err=%d\n", err);
704 GEM_BUG_ON(!list_is_singular(&mm->hole_stack));
705 mmap_offset_unlock(i915);
708 if (!assert_mmap_offset(i915, PAGE_SIZE, 0)) {
709 pr_err("Unable to insert object into single page hole\n");
715 if (!assert_mmap_offset(i915, 2 * PAGE_SIZE, enospc)) {
716 pr_err("Unexpectedly succeeded in inserting too large object into single page hole\n");
721 /* Fill the hole, further allocation attempts should then fail */
722 obj = create_sys_or_internal(i915, PAGE_SIZE);
725 pr_err("Unable to create object for reclaimed hole\n");
729 err = __assign_mmap_offset(obj, default_mapping(i915), &offset, NULL);
731 pr_err("Unable to insert object into reclaimed hole\n");
735 if (!assert_mmap_offset(i915, PAGE_SIZE, enospc)) {
736 pr_err("Unexpectedly succeeded in inserting object into no holes!\n");
741 i915_gem_object_put(obj);
743 /* Now fill with busy dead objects that we expect to reap */
744 for (loop = 0; loop < 3; loop++) {
745 if (intel_gt_is_wedged(to_gt(i915)))
748 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
754 err = make_obj_busy(obj);
756 pr_err("[loop %d] Failed to busy the object\n", loop);
762 mmap_offset_lock(i915);
764 drm_mm_for_each_node_safe(hole, next, mm) {
765 if (hole->color != -1ul)
768 drm_mm_remove_node(hole);
771 mmap_offset_unlock(i915);
772 restore_retire_worker(i915);
775 i915_gem_object_put(obj);
779 static int gtt_set(struct drm_i915_gem_object *obj)
781 struct i915_vma *vma;
785 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
789 intel_gt_pm_get(vma->vm->gt);
790 map = i915_vma_pin_iomap(vma);
797 memset_io(map, POISON_INUSE, obj->base.size);
798 i915_vma_unpin_iomap(vma);
801 intel_gt_pm_put(vma->vm->gt);
805 static int gtt_check(struct drm_i915_gem_object *obj)
807 struct i915_vma *vma;
811 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
815 intel_gt_pm_get(vma->vm->gt);
816 map = i915_vma_pin_iomap(vma);
823 if (memchr_inv((void __force *)map, POISON_FREE, obj->base.size)) {
824 pr_err("%s: Write via mmap did not land in backing store (GTT)\n",
825 obj->mm.region->name);
828 i915_vma_unpin_iomap(vma);
831 intel_gt_pm_put(vma->vm->gt);
835 static int wc_set(struct drm_i915_gem_object *obj)
839 vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
841 return PTR_ERR(vaddr);
843 memset(vaddr, POISON_INUSE, obj->base.size);
844 i915_gem_object_flush_map(obj);
845 i915_gem_object_unpin_map(obj);
850 static int wc_check(struct drm_i915_gem_object *obj)
855 vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
857 return PTR_ERR(vaddr);
859 if (memchr_inv(vaddr, POISON_FREE, obj->base.size)) {
860 pr_err("%s: Write via mmap did not land in backing store (WC)\n",
861 obj->mm.region->name);
864 i915_gem_object_unpin_map(obj);
869 static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
871 struct drm_i915_private *i915 = to_i915(obj->base.dev);
874 if (obj->ops->mmap_offset)
875 return type == I915_MMAP_TYPE_FIXED;
876 else if (type == I915_MMAP_TYPE_FIXED)
879 if (type == I915_MMAP_TYPE_GTT &&
880 !i915_ggtt_has_aperture(to_gt(i915)->ggtt))
883 i915_gem_object_lock(obj, NULL);
884 no_map = (type != I915_MMAP_TYPE_GTT &&
885 !i915_gem_object_has_struct_page(obj) &&
886 !i915_gem_object_has_iomem(obj));
887 i915_gem_object_unlock(obj);
892 #define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
893 static int __igt_mmap(struct drm_i915_private *i915,
894 struct drm_i915_gem_object *obj,
895 enum i915_mmap_type type)
897 struct vm_area_struct *area;
902 if (!can_mmap(obj, type))
911 err = __assign_mmap_offset(obj, type, &offset, NULL);
915 addr = igt_mmap_offset(i915, offset, obj->base.size, PROT_WRITE, MAP_SHARED);
916 if (IS_ERR_VALUE(addr))
919 pr_debug("igt_mmap(%s, %d) @ %lx\n", obj->mm.region->name, type, addr);
921 mmap_read_lock(current->mm);
922 area = vma_lookup(current->mm, addr);
923 mmap_read_unlock(current->mm);
925 pr_err("%s: Did not create a vm_area_struct for the mmap\n",
926 obj->mm.region->name);
931 for (i = 0; i < obj->base.size / sizeof(u32); i++) {
932 u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof(*ux)));
935 if (get_user(x, ux)) {
936 pr_err("%s: Unable to read from mmap, offset:%zd\n",
937 obj->mm.region->name, i * sizeof(x));
942 if (x != expand32(POISON_INUSE)) {
943 pr_err("%s: Read incorrect value from mmap, offset:%zd, found:%x, expected:%x\n",
944 obj->mm.region->name,
945 i * sizeof(x), x, expand32(POISON_INUSE));
950 x = expand32(POISON_FREE);
951 if (put_user(x, ux)) {
952 pr_err("%s: Unable to write to mmap, offset:%zd\n",
953 obj->mm.region->name, i * sizeof(x));
959 if (type == I915_MMAP_TYPE_GTT)
960 intel_gt_flush_ggtt_writes(to_gt(i915));
964 err = gtt_check(obj);
966 vm_munmap(addr, obj->base.size);
970 static int igt_mmap(void *arg)
972 struct drm_i915_private *i915 = arg;
973 struct intel_memory_region *mr;
974 enum intel_region_id id;
976 for_each_memory_region(mr, i915, id) {
977 unsigned long sizes[] = {
987 for (i = 0; i < ARRAY_SIZE(sizes); i++) {
988 struct drm_i915_gem_object *obj;
991 obj = __i915_gem_object_create_user(i915, sizes[i], &mr, 1);
992 if (obj == ERR_PTR(-ENODEV))
998 err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
1000 err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
1002 err = __igt_mmap(i915, obj, I915_MMAP_TYPE_FIXED);
1004 i915_gem_object_put(obj);
1013 static void igt_close_objects(struct drm_i915_private *i915,
1014 struct list_head *objects)
1016 struct drm_i915_gem_object *obj, *on;
1018 list_for_each_entry_safe(obj, on, objects, st_link) {
1019 i915_gem_object_lock(obj, NULL);
1020 if (i915_gem_object_has_pinned_pages(obj))
1021 i915_gem_object_unpin_pages(obj);
1022 /* No polluting the memory region between tests */
1023 __i915_gem_object_put_pages(obj);
1024 i915_gem_object_unlock(obj);
1025 list_del(&obj->st_link);
1026 i915_gem_object_put(obj);
1031 i915_gem_drain_freed_objects(i915);
1034 static void igt_make_evictable(struct list_head *objects)
1036 struct drm_i915_gem_object *obj;
1038 list_for_each_entry(obj, objects, st_link) {
1039 i915_gem_object_lock(obj, NULL);
1040 if (i915_gem_object_has_pinned_pages(obj))
1041 i915_gem_object_unpin_pages(obj);
1042 i915_gem_object_unlock(obj);
1048 static int igt_fill_mappable(struct intel_memory_region *mr,
1049 struct list_head *objects)
1057 struct drm_i915_gem_object *obj;
1059 obj = i915_gem_object_create_region(mr, size, 0, 0);
1065 list_add(&obj->st_link, objects);
1067 err = i915_gem_object_pin_pages_unlocked(obj);
1069 if (err != -ENXIO && err != -ENOMEM)
1072 if (size == mr->min_page_size) {
1081 total += obj->base.size;
1084 pr_info("%s filled=%lluMiB\n", __func__, total >> 20);
1088 igt_close_objects(mr->i915, objects);
1092 static int ___igt_mmap_migrate(struct drm_i915_private *i915,
1093 struct drm_i915_gem_object *obj,
1097 struct vm_area_struct *area;
1100 pr_info("igt_mmap(%s, %d) @ %lx\n",
1101 obj->mm.region->name, I915_MMAP_TYPE_FIXED, addr);
1103 mmap_read_lock(current->mm);
1104 area = vma_lookup(current->mm, addr);
1105 mmap_read_unlock(current->mm);
1107 pr_err("%s: Did not create a vm_area_struct for the mmap\n",
1108 obj->mm.region->name);
1113 for (i = 0; i < obj->base.size / sizeof(u32); i++) {
1114 u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof(*ux)));
1117 if (get_user(x, ux)) {
1120 pr_err("%s: Unable to read from mmap, offset:%zd\n",
1121 obj->mm.region->name, i * sizeof(x));
1129 pr_err("%s: Faulted unmappable memory\n",
1130 obj->mm.region->name);
1135 if (x != expand32(POISON_INUSE)) {
1136 pr_err("%s: Read incorrect value from mmap, offset:%zd, found:%x, expected:%x\n",
1137 obj->mm.region->name,
1138 i * sizeof(x), x, expand32(POISON_INUSE));
1143 x = expand32(POISON_FREE);
1144 if (put_user(x, ux)) {
1145 pr_err("%s: Unable to write to mmap, offset:%zd\n",
1146 obj->mm.region->name, i * sizeof(x));
1156 obj->flags &= ~I915_BO_ALLOC_GPU_ONLY;
1157 err = wc_check(obj);
1160 vm_munmap(addr, obj->base.size);
1164 #define IGT_MMAP_MIGRATE_TOPDOWN (1 << 0)
1165 #define IGT_MMAP_MIGRATE_FILL (1 << 1)
1166 #define IGT_MMAP_MIGRATE_EVICTABLE (1 << 2)
1167 #define IGT_MMAP_MIGRATE_UNFAULTABLE (1 << 3)
1168 #define IGT_MMAP_MIGRATE_FAIL_GPU (1 << 4)
1169 static int __igt_mmap_migrate(struct intel_memory_region **placements,
1171 struct intel_memory_region *expected_mr,
1174 struct drm_i915_private *i915 = placements[0]->i915;
1175 struct drm_i915_gem_object *obj;
1176 struct i915_request *rq = NULL;
1182 obj = __i915_gem_object_create_user(i915, PAGE_SIZE,
1186 return PTR_ERR(obj);
1188 if (flags & IGT_MMAP_MIGRATE_TOPDOWN)
1189 obj->flags |= I915_BO_ALLOC_GPU_ONLY;
1191 err = __assign_mmap_offset(obj, I915_MMAP_TYPE_FIXED, &offset, NULL);
1196 * This will eventually create a GEM context, due to opening dummy drm
1197 * file, which needs a tiny amount of mappable device memory for the top
1198 * level paging structures(and perhaps scratch), so make sure we
1199 * allocate early, to avoid tears.
1201 addr = igt_mmap_offset(i915, offset, obj->base.size,
1202 PROT_WRITE, MAP_SHARED);
1203 if (IS_ERR_VALUE(addr)) {
1208 if (flags & IGT_MMAP_MIGRATE_FILL) {
1209 err = igt_fill_mappable(placements[0], &objects);
1214 err = i915_gem_object_lock(obj, NULL);
1218 err = i915_gem_object_pin_pages(obj);
1220 i915_gem_object_unlock(obj);
1224 err = intel_context_migrate_clear(to_gt(i915)->migrate.context, NULL,
1225 obj->mm.pages->sgl, obj->cache_level,
1226 i915_gem_object_is_lmem(obj),
1227 expand32(POISON_INUSE), &rq);
1228 i915_gem_object_unpin_pages(obj);
1230 err = dma_resv_reserve_fences(obj->base.resv, 1);
1232 dma_resv_add_fence(obj->base.resv, &rq->fence,
1233 DMA_RESV_USAGE_KERNEL);
1234 i915_request_put(rq);
1236 i915_gem_object_unlock(obj);
1240 if (flags & IGT_MMAP_MIGRATE_EVICTABLE)
1241 igt_make_evictable(&objects);
1243 if (flags & IGT_MMAP_MIGRATE_FAIL_GPU) {
1244 err = i915_gem_object_lock(obj, NULL);
1249 * Ensure we only simulate the gpu failuire when faulting the
1252 err = i915_gem_object_wait_moving_fence(obj, true);
1253 i915_gem_object_unlock(obj);
1256 i915_ttm_migrate_set_failure_modes(true, false);
1259 err = ___igt_mmap_migrate(i915, obj, addr,
1260 flags & IGT_MMAP_MIGRATE_UNFAULTABLE);
1262 if (!err && obj->mm.region != expected_mr) {
1263 pr_err("%s region mismatch %s\n", __func__, expected_mr->name);
1267 if (flags & IGT_MMAP_MIGRATE_FAIL_GPU) {
1268 struct intel_gt *gt;
1271 i915_ttm_migrate_set_failure_modes(false, false);
1273 for_each_gt(gt, i915, id) {
1274 intel_wakeref_t wakeref;
1277 mutex_lock(>->reset.mutex);
1278 wedged = test_bit(I915_WEDGED, >->reset.flags);
1279 mutex_unlock(>->reset.mutex);
1281 pr_err("gt(%u) not wedged\n", id);
1286 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1287 igt_global_reset_lock(gt);
1288 intel_gt_reset(gt, ALL_ENGINES, NULL);
1289 igt_global_reset_unlock(gt);
1290 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1293 if (!i915_gem_object_has_unknown_state(obj)) {
1294 pr_err("object missing unknown_state\n");
1300 i915_gem_object_put(obj);
1301 igt_close_objects(i915, &objects);
1305 static int igt_mmap_migrate(void *arg)
1307 struct drm_i915_private *i915 = arg;
1308 struct intel_memory_region *system = i915->mm.regions[INTEL_REGION_SMEM];
1309 struct intel_memory_region *mr;
1310 enum intel_region_id id;
1312 for_each_memory_region(mr, i915, id) {
1313 struct intel_memory_region *mixed[] = { mr, system };
1314 struct intel_memory_region *single[] = { mr };
1315 struct ttm_resource_manager *man = mr->region_private;
1316 resource_size_t saved_io_size;
1326 * For testing purposes let's force small BAR, if not already
1329 saved_io_size = mr->io_size;
1330 if (mr->io_size == mr->total) {
1331 resource_size_t io_size = mr->io_size;
1333 io_size = rounddown_pow_of_two(io_size >> 1);
1334 if (io_size < PAGE_SIZE)
1337 mr->io_size = io_size;
1338 i915_ttm_buddy_man_force_visible_size(man,
1339 io_size >> PAGE_SHIFT);
1343 * Allocate in the mappable portion, should be no suprises here.
1345 err = __igt_mmap_migrate(mixed, ARRAY_SIZE(mixed), mr, 0);
1350 * Allocate in the non-mappable portion, but force migrating to
1351 * the mappable portion on fault (LMEM -> LMEM)
1353 err = __igt_mmap_migrate(single, ARRAY_SIZE(single), mr,
1354 IGT_MMAP_MIGRATE_TOPDOWN |
1355 IGT_MMAP_MIGRATE_FILL |
1356 IGT_MMAP_MIGRATE_EVICTABLE);
1361 * Allocate in the non-mappable portion, but force spilling into
1362 * system memory on fault (LMEM -> SMEM)
1364 err = __igt_mmap_migrate(mixed, ARRAY_SIZE(mixed), system,
1365 IGT_MMAP_MIGRATE_TOPDOWN |
1366 IGT_MMAP_MIGRATE_FILL);
1371 * Allocate in the non-mappable portion, but since the mappable
1372 * portion is already full, and we can't spill to system memory,
1373 * then we should expect the fault to fail.
1375 err = __igt_mmap_migrate(single, ARRAY_SIZE(single), mr,
1376 IGT_MMAP_MIGRATE_TOPDOWN |
1377 IGT_MMAP_MIGRATE_FILL |
1378 IGT_MMAP_MIGRATE_UNFAULTABLE);
1383 * Allocate in the non-mappable portion, but force migrating to
1384 * the mappable portion on fault (LMEM -> LMEM). We then also
1385 * simulate a gpu error when moving the pages when faulting the
1386 * pages, which should result in wedging the gpu and returning
1387 * SIGBUS in the fault handler, since we can't fallback to
1390 err = __igt_mmap_migrate(single, ARRAY_SIZE(single), mr,
1391 IGT_MMAP_MIGRATE_TOPDOWN |
1392 IGT_MMAP_MIGRATE_FILL |
1393 IGT_MMAP_MIGRATE_EVICTABLE |
1394 IGT_MMAP_MIGRATE_FAIL_GPU |
1395 IGT_MMAP_MIGRATE_UNFAULTABLE);
1397 mr->io_size = saved_io_size;
1398 i915_ttm_buddy_man_force_visible_size(man,
1399 mr->io_size >> PAGE_SHIFT);
1407 static const char *repr_mmap_type(enum i915_mmap_type type)
1410 case I915_MMAP_TYPE_GTT: return "gtt";
1411 case I915_MMAP_TYPE_WB: return "wb";
1412 case I915_MMAP_TYPE_WC: return "wc";
1413 case I915_MMAP_TYPE_UC: return "uc";
1414 case I915_MMAP_TYPE_FIXED: return "fixed";
1415 default: return "unknown";
1419 static bool can_access(struct drm_i915_gem_object *obj)
1423 i915_gem_object_lock(obj, NULL);
1424 access = i915_gem_object_has_struct_page(obj) ||
1425 i915_gem_object_has_iomem(obj);
1426 i915_gem_object_unlock(obj);
1431 static int __igt_mmap_access(struct drm_i915_private *i915,
1432 struct drm_i915_gem_object *obj,
1433 enum i915_mmap_type type)
1435 unsigned long __user *ptr;
1442 memset(&A, 0xAA, sizeof(A));
1443 memset(&B, 0xBB, sizeof(B));
1445 if (!can_mmap(obj, type) || !can_access(obj))
1448 err = __assign_mmap_offset(obj, type, &offset, NULL);
1452 addr = igt_mmap_offset(i915, offset, obj->base.size, PROT_WRITE, MAP_SHARED);
1453 if (IS_ERR_VALUE(addr))
1455 ptr = (unsigned long __user *)addr;
1457 err = __put_user(A, ptr);
1459 pr_err("%s(%s): failed to write into user mmap\n",
1460 obj->mm.region->name, repr_mmap_type(type));
1464 intel_gt_flush_ggtt_writes(to_gt(i915));
1466 err = access_process_vm(current, addr, &x, sizeof(x), 0);
1467 if (err != sizeof(x)) {
1468 pr_err("%s(%s): access_process_vm() read failed\n",
1469 obj->mm.region->name, repr_mmap_type(type));
1473 err = access_process_vm(current, addr, &B, sizeof(B), FOLL_WRITE);
1474 if (err != sizeof(B)) {
1475 pr_err("%s(%s): access_process_vm() write failed\n",
1476 obj->mm.region->name, repr_mmap_type(type));
1480 intel_gt_flush_ggtt_writes(to_gt(i915));
1482 err = __get_user(y, ptr);
1484 pr_err("%s(%s): failed to read from user mmap\n",
1485 obj->mm.region->name, repr_mmap_type(type));
1489 if (x != A || y != B) {
1490 pr_err("%s(%s): failed to read/write values, found (%lx, %lx)\n",
1491 obj->mm.region->name, repr_mmap_type(type),
1498 vm_munmap(addr, obj->base.size);
1502 static int igt_mmap_access(void *arg)
1504 struct drm_i915_private *i915 = arg;
1505 struct intel_memory_region *mr;
1506 enum intel_region_id id;
1508 for_each_memory_region(mr, i915, id) {
1509 struct drm_i915_gem_object *obj;
1515 obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
1516 if (obj == ERR_PTR(-ENODEV))
1520 return PTR_ERR(obj);
1522 err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_GTT);
1524 err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WB);
1526 err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WC);
1528 err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_UC);
1530 err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_FIXED);
1532 i915_gem_object_put(obj);
1540 static int __igt_mmap_gpu(struct drm_i915_private *i915,
1541 struct drm_i915_gem_object *obj,
1542 enum i915_mmap_type type)
1544 struct intel_engine_cs *engine;
1552 * Verify that the mmap access into the backing store aligns with
1553 * that of the GPU, i.e. that mmap is indeed writing into the same
1554 * page as being read by the GPU.
1557 if (!can_mmap(obj, type))
1566 err = __assign_mmap_offset(obj, type, &offset, NULL);
1570 addr = igt_mmap_offset(i915, offset, obj->base.size, PROT_WRITE, MAP_SHARED);
1571 if (IS_ERR_VALUE(addr))
1574 ux = u64_to_user_ptr((u64)addr);
1575 bbe = MI_BATCH_BUFFER_END;
1576 if (put_user(bbe, ux)) {
1577 pr_err("%s: Unable to write to mmap\n", obj->mm.region->name);
1582 if (type == I915_MMAP_TYPE_GTT)
1583 intel_gt_flush_ggtt_writes(to_gt(i915));
1585 for_each_uabi_engine(engine, i915) {
1586 struct i915_request *rq;
1587 struct i915_vma *vma;
1588 struct i915_gem_ww_ctx ww;
1590 vma = i915_vma_instance(obj, engine->kernel_context->vm, NULL);
1596 i915_gem_ww_ctx_init(&ww, false);
1598 err = i915_gem_object_lock(obj, &ww);
1600 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER);
1604 rq = i915_request_create(engine->kernel_context);
1610 err = i915_vma_move_to_active(vma, rq, 0);
1612 err = engine->emit_bb_start(rq, i915_vma_offset(vma), 0, 0);
1613 i915_request_get(rq);
1614 i915_request_add(rq);
1616 if (i915_request_wait(rq, 0, HZ / 5) < 0) {
1617 struct drm_printer p =
1618 drm_info_printer(engine->i915->drm.dev);
1620 pr_err("%s(%s, %s): Failed to execute batch\n",
1621 __func__, engine->name, obj->mm.region->name);
1622 intel_engine_dump(engine, &p,
1623 "%s\n", engine->name);
1625 intel_gt_set_wedged(engine->gt);
1628 i915_request_put(rq);
1631 i915_vma_unpin(vma);
1633 if (err == -EDEADLK) {
1634 err = i915_gem_ww_ctx_backoff(&ww);
1638 i915_gem_ww_ctx_fini(&ww);
1644 vm_munmap(addr, obj->base.size);
1648 static int igt_mmap_gpu(void *arg)
1650 struct drm_i915_private *i915 = arg;
1651 struct intel_memory_region *mr;
1652 enum intel_region_id id;
1654 for_each_memory_region(mr, i915, id) {
1655 struct drm_i915_gem_object *obj;
1661 obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
1662 if (obj == ERR_PTR(-ENODEV))
1666 return PTR_ERR(obj);
1668 err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
1670 err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
1672 err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_FIXED);
1674 i915_gem_object_put(obj);
1682 static int check_present_pte(pte_t *pte, unsigned long addr, void *data)
1684 if (!pte_present(*pte) || pte_none(*pte)) {
1685 pr_err("missing PTE:%lx\n",
1686 (addr - (unsigned long)data) >> PAGE_SHIFT);
1693 static int check_absent_pte(pte_t *pte, unsigned long addr, void *data)
1695 if (pte_present(*pte) && !pte_none(*pte)) {
1696 pr_err("present PTE:%lx; expected to be revoked\n",
1697 (addr - (unsigned long)data) >> PAGE_SHIFT);
1704 static int check_present(unsigned long addr, unsigned long len)
1706 return apply_to_page_range(current->mm, addr, len,
1707 check_present_pte, (void *)addr);
1710 static int check_absent(unsigned long addr, unsigned long len)
1712 return apply_to_page_range(current->mm, addr, len,
1713 check_absent_pte, (void *)addr);
1716 static int prefault_range(u64 start, u64 len)
1718 const char __user *addr, *end;
1719 char __maybe_unused c;
1722 addr = u64_to_user_ptr(start);
1725 for (; addr < end; addr += PAGE_SIZE) {
1726 err = __get_user(c, addr);
1731 return __get_user(c, end - 1);
1734 static int __igt_mmap_revoke(struct drm_i915_private *i915,
1735 struct drm_i915_gem_object *obj,
1736 enum i915_mmap_type type)
1742 if (!can_mmap(obj, type))
1745 err = __assign_mmap_offset(obj, type, &offset, NULL);
1749 addr = igt_mmap_offset(i915, offset, obj->base.size, PROT_WRITE, MAP_SHARED);
1750 if (IS_ERR_VALUE(addr))
1753 err = prefault_range(addr, obj->base.size);
1757 err = check_present(addr, obj->base.size);
1759 pr_err("%s: was not present\n", obj->mm.region->name);
1764 * After unbinding the object from the GGTT, its address may be reused
1765 * for other objects. Ergo we have to revoke the previous mmap PTE
1766 * access as it no longer points to the same object.
1768 i915_gem_object_lock(obj, NULL);
1769 err = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
1770 i915_gem_object_unlock(obj);
1772 pr_err("Failed to unbind object!\n");
1776 if (type != I915_MMAP_TYPE_GTT) {
1777 i915_gem_object_lock(obj, NULL);
1778 __i915_gem_object_put_pages(obj);
1779 i915_gem_object_unlock(obj);
1780 if (i915_gem_object_has_pages(obj)) {
1781 pr_err("Failed to put-pages object!\n");
1787 err = check_absent(addr, obj->base.size);
1789 pr_err("%s: was not absent\n", obj->mm.region->name);
1794 vm_munmap(addr, obj->base.size);
1798 static int igt_mmap_revoke(void *arg)
1800 struct drm_i915_private *i915 = arg;
1801 struct intel_memory_region *mr;
1802 enum intel_region_id id;
1804 for_each_memory_region(mr, i915, id) {
1805 struct drm_i915_gem_object *obj;
1811 obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
1812 if (obj == ERR_PTR(-ENODEV))
1816 return PTR_ERR(obj);
1818 err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
1820 err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
1822 err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_FIXED);
1824 i915_gem_object_put(obj);
1832 int i915_gem_mman_live_selftests(struct drm_i915_private *i915)
1834 static const struct i915_subtest tests[] = {
1835 SUBTEST(igt_partial_tiling),
1836 SUBTEST(igt_smoke_tiling),
1837 SUBTEST(igt_mmap_offset_exhaustion),
1839 SUBTEST(igt_mmap_migrate),
1840 SUBTEST(igt_mmap_access),
1841 SUBTEST(igt_mmap_revoke),
1842 SUBTEST(igt_mmap_gpu),
1845 return i915_live_subtests(tests, i915);