drivers/gpu/drm/i915/gem/i915_gem_object_blt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include "i915_gem_object_blt.h"
   7
   8 #include "i915_gem_clflush.h"
   9 #include "intel_drv.h"
  10
  11 int intel_emit_vma_fill_blt(struct i915_request *rq,
  12                             struct i915_vma *vma,
  13                             u32 value)
  14 {
  15         u32 *cs;
  16
  17         cs = intel_ring_begin(rq, 8);
  18         if (IS_ERR(cs))
  19                 return PTR_ERR(cs);
  20
  21         if (INTEL_GEN(rq->i915) >= 8) {
  22                 *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
  23                 *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
  24                 *cs++ = 0;
  25                 *cs++ = vma->size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
  26                 *cs++ = lower_32_bits(vma->node.start);
  27                 *cs++ = upper_32_bits(vma->node.start);
  28                 *cs++ = value;
  29                 *cs++ = MI_NOOP;
  30         } else {
  31                 *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
  32                 *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
  33                 *cs++ = 0;
  34                 *cs++ = vma->size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
  35                 *cs++ = vma->node.start;
  36                 *cs++ = value;
  37                 *cs++ = MI_NOOP;
  38                 *cs++ = MI_NOOP;
  39         }
  40
  41         intel_ring_advance(rq, cs);
  42
  43         return 0;
  44 }
  45
  46 int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
  47                              struct intel_context *ce,
  48                              u32 value)
  49 {
  50         struct drm_i915_private *i915 = to_i915(obj->base.dev);
  51         struct i915_gem_context *ctx = ce->gem_context;
  52         struct i915_address_space *vm;
  53         struct i915_request *rq;
  54         struct i915_vma *vma;
  55         int err;
  56
  57         /* XXX: ce->vm please */
  58         vm = ctx->ppgtt ? &ctx->ppgtt->vm : &i915->ggtt.vm;
  59
  60         vma = i915_vma_instance(obj, vm, NULL);
  61         if (IS_ERR(vma))
  62                 return PTR_ERR(vma);
  63
  64         err = i915_vma_pin(vma, 0, 0, PIN_USER);
  65         if (unlikely(err))
  66                 return err;
  67
  68         if (obj->cache_dirty & ~obj->cache_coherent) {
  69                 i915_gem_object_lock(obj);
  70                 i915_gem_clflush_object(obj, 0);
  71                 i915_gem_object_unlock(obj);
  72         }
  73
  74         rq = i915_request_create(ce);
  75         if (IS_ERR(rq)) {
  76                 err = PTR_ERR(rq);
  77                 goto out_unpin;
  78         }
  79
  80         err = i915_request_await_object(rq, obj, true);
  81         if (unlikely(err))
  82                 goto out_request;
  83
  84         if (ce->engine->emit_init_breadcrumb) {
  85                 err = ce->engine->emit_init_breadcrumb(rq);
  86                 if (unlikely(err))
  87                         goto out_request;
  88         }
  89
  90         i915_vma_lock(vma);
  91         err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
  92         i915_vma_unlock(vma);
  93         if (unlikely(err))
  94                 goto out_request;
  95
  96         err = intel_emit_vma_fill_blt(rq, vma, value);
  97 out_request:
  98         if (unlikely(err))
  99                 i915_request_skip(rq, err);
 100
 101         i915_request_add(rq);
 102 out_unpin:
 103         i915_vma_unpin(vma);
 104         return err;
 105 }
 106
 107 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 108 #include "selftests/i915_gem_object_blt.c"
 109 #endif