2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008,2010 Intel Corporation
7 #include <linux/intel-iommu.h>
8 #include <linux/dma-resv.h>
9 #include <linux/sync_file.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_syncobj.h>
14 #include "display/intel_frontbuffer.h"
16 #include "gem/i915_gem_ioctls.h"
17 #include "gt/intel_context.h"
18 #include "gt/intel_gpu_commands.h"
19 #include "gt/intel_gt.h"
20 #include "gt/intel_gt_buffer_pool.h"
21 #include "gt/intel_gt_pm.h"
22 #include "gt/intel_ring.h"
25 #include "i915_gem_clflush.h"
26 #include "i915_gem_context.h"
27 #include "i915_gem_ioctls.h"
28 #include "i915_sw_fence_work.h"
29 #include "i915_trace.h"
30 #include "i915_user_extensions.h"
36 /** This vma's place in the execbuf reservation list */
37 struct drm_i915_gem_exec_object2 *exec;
38 struct list_head bind_link;
39 struct list_head reloc_link;
41 struct hlist_node node;
49 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
52 #define __EXEC_OBJECT_HAS_PIN BIT(31)
53 #define __EXEC_OBJECT_HAS_FENCE BIT(30)
54 #define __EXEC_OBJECT_NEEDS_MAP BIT(29)
55 #define __EXEC_OBJECT_NEEDS_BIAS BIT(28)
56 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */
57 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
59 #define __EXEC_HAS_RELOC BIT(31)
60 #define __EXEC_ENGINE_PINNED BIT(30)
61 #define __EXEC_INTERNAL_FLAGS (~0u << 30)
62 #define UPDATE PIN_OFFSET_FIXED
64 #define BATCH_OFFSET_BIAS (256*1024)
66 #define __I915_EXEC_ILLEGAL_FLAGS \
67 (__I915_EXEC_UNKNOWN_FLAGS | \
68 I915_EXEC_CONSTANTS_MASK | \
69 I915_EXEC_RESOURCE_STREAMER)
71 /* Catch emission of unexpected errors for CI! */
72 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
75 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
81 * DOC: User command execution
83 * Userspace submits commands to be executed on the GPU as an instruction
84 * stream within a GEM object we call a batchbuffer. This instructions may
85 * refer to other GEM objects containing auxiliary state such as kernels,
86 * samplers, render targets and even secondary batchbuffers. Userspace does
87 * not know where in the GPU memory these objects reside and so before the
88 * batchbuffer is passed to the GPU for execution, those addresses in the
89 * batchbuffer and auxiliary objects are updated. This is known as relocation,
90 * or patching. To try and avoid having to relocate each object on the next
91 * execution, userspace is told the location of those objects in this pass,
92 * but this remains just a hint as the kernel may choose a new location for
93 * any object in the future.
95 * At the level of talking to the hardware, submitting a batchbuffer for the
96 * GPU to execute is to add content to a buffer from which the HW
97 * command streamer is reading.
99 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
100 * Execlists, this command is not placed on the same buffer as the
103 * 2. Add a command to invalidate caches to the buffer.
105 * 3. Add a batchbuffer start command to the buffer; the start command is
106 * essentially a token together with the GPU address of the batchbuffer
109 * 4. Add a pipeline flush to the buffer.
111 * 5. Add a memory write command to the buffer to record when the GPU
112 * is done executing the batchbuffer. The memory write writes the
113 * global sequence number of the request, ``i915_request::global_seqno``;
114 * the i915 driver uses the current value in the register to determine
115 * if the GPU has completed the batchbuffer.
117 * 6. Add a user interrupt command to the buffer. This command instructs
118 * the GPU to issue an interrupt when the command, pipeline flush and
119 * memory write are completed.
121 * 7. Inform the hardware of the additional commands added to the buffer
122 * (by updating the tail pointer).
124 * Processing an execbuf ioctl is conceptually split up into a few phases.
126 * 1. Validation - Ensure all the pointers, handles and flags are valid.
127 * 2. Reservation - Assign GPU address space for every object
128 * 3. Relocation - Update any addresses to point to the final locations
129 * 4. Serialisation - Order the request with respect to its dependencies
130 * 5. Construction - Construct a request to execute the batchbuffer
131 * 6. Submission (at some point in the future execution)
133 * Reserving resources for the execbuf is the most complicated phase. We
134 * neither want to have to migrate the object in the address space, nor do
135 * we want to have to update any relocations pointing to this object. Ideally,
136 * we want to leave the object where it is and for all the existing relocations
137 * to match. If the object is given a new address, or if userspace thinks the
138 * object is elsewhere, we have to parse all the relocation entries and update
139 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
140 * all the target addresses in all of its objects match the value in the
141 * relocation entries and that they all match the presumed offsets given by the
142 * list of execbuffer objects. Using this knowledge, we know that if we haven't
143 * moved any buffers, all the relocation entries are valid and we can skip
144 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
145 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
147 * The addresses written in the objects must match the corresponding
148 * reloc.presumed_offset which in turn must match the corresponding
151 * Any render targets written to in the batch must be flagged with
154 * To avoid stalling, execobject.offset should match the current
155 * address of that object within the active context.
157 * The reservation is done is multiple phases. First we try and keep any
158 * object already bound in its current location - so as long as meets the
159 * constraints imposed by the new execbuffer. Any object left unbound after the
160 * first pass is then fitted into any available idle space. If an object does
161 * not fit, all objects are removed from the reservation and the process rerun
162 * after sorting the objects into a priority order (more difficult to fit
163 * objects are tried first). Failing that, the entire VM is cleared and we try
164 * to fit the execbuf once last time before concluding that it simply will not
167 * A small complication to all of this is that we allow userspace not only to
168 * specify an alignment and a size for the object in the address space, but
169 * we also allow userspace to specify the exact offset. This objects are
170 * simpler to place (the location is known a priori) all we have to do is make
171 * sure the space is available.
173 * Once all the objects are in place, patching up the buried pointers to point
174 * to the final locations is a fairly simple job of walking over the relocation
175 * entry arrays, looking up the right address and rewriting the value into
176 * the object. Simple! ... The relocation entries are stored in user memory
177 * and so to access them we have to copy them into a local buffer. That copy
178 * has to avoid taking any pagefaults as they may lead back to a GEM object
179 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
180 * the relocation into multiple passes. First we try to do everything within an
181 * atomic context (avoid the pagefaults) which requires that we never wait. If
182 * we detect that we may wait, or if we need to fault, then we have to fallback
183 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
184 * bells yet?) Dropping the mutex means that we lose all the state we have
185 * built up so far for the execbuf and we must reset any global data. However,
186 * we do leave the objects pinned in their final locations - which is a
187 * potential issue for concurrent execbufs. Once we have left the mutex, we can
188 * allocate and copy all the relocation entries into a large array at our
189 * leisure, reacquire the mutex, reclaim all the objects and other state and
190 * then proceed to update any incorrect addresses with the objects.
192 * As we process the relocation entries, we maintain a record of whether the
193 * object is being written to. Using NORELOC, we expect userspace to provide
194 * this information instead. We also check whether we can skip the relocation
195 * by comparing the expected value inside the relocation entry with the target's
196 * final address. If they differ, we have to map the current object and rewrite
197 * the 4 or 8 byte pointer within.
199 * Serialising an execbuf is quite simple according to the rules of the GEM
200 * ABI. Execution within each context is ordered by the order of submission.
201 * Writes to any GEM object are in order of submission and are exclusive. Reads
202 * from a GEM object are unordered with respect to other reads, but ordered by
203 * writes. A write submitted after a read cannot occur before the read, and
204 * similarly any read submitted after a write cannot occur before the write.
205 * Writes are ordered between engines such that only one write occurs at any
206 * time (completing any reads beforehand) - using semaphores where available
207 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
208 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
209 * reads before starting, and any read (either using set-domain or pread) must
210 * flush all GPU writes before starting. (Note we only employ a barrier before,
211 * we currently rely on userspace not concurrently starting a new execution
212 * whilst reading or writing to an object. This may be an advantage or not
213 * depending on how much you trust userspace not to shoot themselves in the
214 * foot.) Serialisation may just result in the request being inserted into
215 * a DAG awaiting its turn, but most simple is to wait on the CPU until
216 * all dependencies are resolved.
218 * After all of that, is just a matter of closing the request and handing it to
219 * the hardware (well, leaving it in a queue to be executed). However, we also
220 * offer the ability for batchbuffers to be run with elevated privileges so
221 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
222 * Before any batch is given extra privileges we first must check that it
223 * contains no nefarious instructions, we check that each instruction is from
224 * our whitelist and all registers are also from an allowed list. We first
225 * copy the user's batchbuffer to a shadow (so that the user doesn't have
226 * access to it, either by the CPU or GPU as we scan it) and then parse each
227 * instruction. If everything is ok, we set a flag telling the hardware to run
228 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
232 struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
233 struct dma_fence *dma_fence;
235 struct dma_fence_chain *chain_fence;
238 struct i915_execbuffer {
239 struct drm_i915_private *i915; /** i915 backpointer */
240 struct drm_file *file; /** per-file lookup tables and limits */
241 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
242 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
245 struct intel_engine_cs *engine; /** engine to queue the request to */
246 struct intel_context *context; /* logical state for the request */
247 struct i915_gem_context *gem_context; /** caller's context */
249 struct i915_request *request; /** our request to build */
250 struct eb_vma *batch; /** identity of the batch obj/vma */
251 struct i915_vma *trampoline; /** trampoline used for chaining */
253 /** actual size of execobj[] as we may extend it for the cmdparser */
254 unsigned int buffer_count;
256 /** list of vma not yet bound during reservation phase */
257 struct list_head unbound;
259 /** list of vma that have execobj.relocation_count */
260 struct list_head relocs;
262 struct i915_gem_ww_ctx ww;
265 * Track the most recently used object for relocations, as we
266 * frequently have to perform multiple relocations within the same
270 struct drm_mm_node node; /** temporary GTT binding */
271 unsigned long vaddr; /** Current kmap address */
272 unsigned long page; /** Currently mapped page index */
273 unsigned int gen; /** Cached value of INTEL_GEN */
274 bool use_64bit_reloc : 1;
277 bool needs_unfenced : 1;
279 struct i915_request *rq;
281 unsigned int rq_size;
282 struct intel_gt_buffer_pool_node *pool;
285 struct intel_gt_buffer_pool_node *reloc_pool; /** relocation pool for -EDEADLK handling */
286 struct intel_context *reloc_context;
288 u64 invalid_flags; /** Set of execobj.flags that are invalid */
289 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
291 u64 batch_len; /** Length of batch within object */
292 u32 batch_start_offset; /** Location within object of batch */
293 u32 batch_flags; /** Flags composed for emit_bb_start() */
294 struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */
297 * Indicate either the size of the hastable used to resolve
298 * relocation handles, or if negative that we are using a direct
299 * index into the execobj[].
302 struct hlist_head *buckets; /** ht for relocation handles */
304 struct eb_fence *fences;
305 unsigned long num_fences;
308 static int eb_parse(struct i915_execbuffer *eb);
309 static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb,
311 static void eb_unpin_engine(struct i915_execbuffer *eb);
313 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
315 return intel_engine_requires_cmd_parser(eb->engine) ||
316 (intel_engine_using_cmd_parser(eb->engine) &&
317 eb->args->batch_len);
320 static int eb_create(struct i915_execbuffer *eb)
322 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
323 unsigned int size = 1 + ilog2(eb->buffer_count);
326 * Without a 1:1 association between relocation handles and
327 * the execobject[] index, we instead create a hashtable.
328 * We size it dynamically based on available memory, starting
329 * first with 1:1 assocative hash and scaling back until
330 * the allocation succeeds.
332 * Later on we use a positive lut_size to indicate we are
333 * using this hashtable, and a negative value to indicate a
339 /* While we can still reduce the allocation size, don't
340 * raise a warning and allow the allocation to fail.
341 * On the last pass though, we want to try as hard
342 * as possible to perform the allocation and warn
347 flags |= __GFP_NORETRY | __GFP_NOWARN;
349 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
360 eb->lut_size = -eb->buffer_count;
367 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
368 const struct i915_vma *vma,
371 if (vma->node.size < entry->pad_to_size)
374 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
377 if (flags & EXEC_OBJECT_PINNED &&
378 vma->node.start != entry->offset)
381 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
382 vma->node.start < BATCH_OFFSET_BIAS)
385 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
386 (vma->node.start + vma->node.size + 4095) >> 32)
389 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
390 !i915_vma_is_map_and_fenceable(vma))
396 static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,
397 unsigned int exec_flags)
401 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
402 pin_flags |= PIN_GLOBAL;
405 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
406 * limit address to the first 4GBs for unflagged objects.
408 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
409 pin_flags |= PIN_ZONE_4G;
411 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
412 pin_flags |= PIN_MAPPABLE;
414 if (exec_flags & EXEC_OBJECT_PINNED)
415 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
416 else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS)
417 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
423 eb_pin_vma(struct i915_execbuffer *eb,
424 const struct drm_i915_gem_exec_object2 *entry,
427 struct i915_vma *vma = ev->vma;
431 pin_flags = vma->node.start;
433 pin_flags = entry->offset & PIN_OFFSET_MASK;
435 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
436 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
437 pin_flags |= PIN_GLOBAL;
439 /* Attempt to reuse the current location if available */
440 /* TODO: Add -EDEADLK handling here */
441 if (unlikely(i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags))) {
442 if (entry->flags & EXEC_OBJECT_PINNED)
445 /* Failing that pick any _free_ space if suitable */
446 if (unlikely(i915_vma_pin_ww(vma, &eb->ww,
449 eb_pin_flags(entry, ev->flags) |
450 PIN_USER | PIN_NOEVICT)))
454 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
455 if (unlikely(i915_vma_pin_fence(vma))) {
461 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
464 ev->flags |= __EXEC_OBJECT_HAS_PIN;
465 return !eb_vma_misplaced(entry, vma, ev->flags);
469 eb_unreserve_vma(struct eb_vma *ev)
471 if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
474 if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
475 __i915_vma_unpin_fence(ev->vma);
477 __i915_vma_unpin(ev->vma);
478 ev->flags &= ~__EXEC_OBJECT_RESERVED;
482 eb_validate_vma(struct i915_execbuffer *eb,
483 struct drm_i915_gem_exec_object2 *entry,
484 struct i915_vma *vma)
486 if (unlikely(entry->flags & eb->invalid_flags))
489 if (unlikely(entry->alignment &&
490 !is_power_of_2_u64(entry->alignment)))
494 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
495 * any non-page-aligned or non-canonical addresses.
497 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
498 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
501 /* pad_to_size was once a reserved field, so sanitize it */
502 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
503 if (unlikely(offset_in_page(entry->pad_to_size)))
506 entry->pad_to_size = 0;
509 * From drm_mm perspective address space is continuous,
510 * so from this point we're always using non-canonical
513 entry->offset = gen8_noncanonical_addr(entry->offset);
515 if (!eb->reloc_cache.has_fence) {
516 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
518 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
519 eb->reloc_cache.needs_unfenced) &&
520 i915_gem_object_is_tiled(vma->obj))
521 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
524 if (!(entry->flags & EXEC_OBJECT_PINNED))
525 entry->flags |= eb->context_flags;
531 eb_add_vma(struct i915_execbuffer *eb,
532 unsigned int i, unsigned batch_idx,
533 struct i915_vma *vma)
535 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
536 struct eb_vma *ev = &eb->vma[i];
540 ev->flags = entry->flags;
542 if (eb->lut_size > 0) {
543 ev->handle = entry->handle;
544 hlist_add_head(&ev->node,
545 &eb->buckets[hash_32(entry->handle,
549 if (entry->relocation_count)
550 list_add_tail(&ev->reloc_link, &eb->relocs);
553 * SNA is doing fancy tricks with compressing batch buffers, which leads
554 * to negative relocation deltas. Usually that works out ok since the
555 * relocate address is still positive, except when the batch is placed
556 * very low in the GTT. Ensure this doesn't happen.
558 * Note that actual hangs have only been observed on gen7, but for
559 * paranoia do it everywhere.
561 if (i == batch_idx) {
562 if (entry->relocation_count &&
563 !(ev->flags & EXEC_OBJECT_PINNED))
564 ev->flags |= __EXEC_OBJECT_NEEDS_BIAS;
565 if (eb->reloc_cache.has_fence)
566 ev->flags |= EXEC_OBJECT_NEEDS_FENCE;
572 static inline int use_cpu_reloc(const struct reloc_cache *cache,
573 const struct drm_i915_gem_object *obj)
575 if (!i915_gem_object_has_struct_page(obj))
578 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
581 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
584 return (cache->has_llc ||
586 obj->cache_level != I915_CACHE_NONE);
589 static int eb_reserve_vma(struct i915_execbuffer *eb,
593 struct drm_i915_gem_exec_object2 *entry = ev->exec;
594 struct i915_vma *vma = ev->vma;
597 if (drm_mm_node_allocated(&vma->node) &&
598 eb_vma_misplaced(entry, vma, ev->flags)) {
599 err = i915_vma_unbind(vma);
604 err = i915_vma_pin_ww(vma, &eb->ww,
605 entry->pad_to_size, entry->alignment,
606 eb_pin_flags(entry, ev->flags) | pin_flags);
610 if (entry->offset != vma->node.start) {
611 entry->offset = vma->node.start | UPDATE;
612 eb->args->flags |= __EXEC_HAS_RELOC;
615 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
616 err = i915_vma_pin_fence(vma);
623 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
626 ev->flags |= __EXEC_OBJECT_HAS_PIN;
627 GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags));
632 static int eb_reserve(struct i915_execbuffer *eb)
634 const unsigned int count = eb->buffer_count;
635 unsigned int pin_flags = PIN_USER | PIN_NONBLOCK;
636 struct list_head last;
638 unsigned int i, pass;
642 * Attempt to pin all of the buffers into the GTT.
643 * This is done in 3 phases:
645 * 1a. Unbind all objects that do not match the GTT constraints for
646 * the execbuffer (fenceable, mappable, alignment etc).
647 * 1b. Increment pin count for already bound objects.
648 * 2. Bind new objects.
649 * 3. Decrement pin count.
651 * This avoid unnecessary unbinding of later objects in order to make
652 * room for the earlier objects *unless* we need to defragment.
656 list_for_each_entry(ev, &eb->unbound, bind_link) {
657 err = eb_reserve_vma(eb, ev, pin_flags);
664 /* Resort *all* the objects into priority order */
665 INIT_LIST_HEAD(&eb->unbound);
666 INIT_LIST_HEAD(&last);
667 for (i = 0; i < count; i++) {
672 if (flags & EXEC_OBJECT_PINNED &&
673 flags & __EXEC_OBJECT_HAS_PIN)
676 eb_unreserve_vma(ev);
678 if (flags & EXEC_OBJECT_PINNED)
679 /* Pinned must have their slot */
680 list_add(&ev->bind_link, &eb->unbound);
681 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
682 /* Map require the lowest 256MiB (aperture) */
683 list_add_tail(&ev->bind_link, &eb->unbound);
684 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
685 /* Prioritise 4GiB region for restricted bo */
686 list_add(&ev->bind_link, &last);
688 list_add_tail(&ev->bind_link, &last);
690 list_splice_tail(&last, &eb->unbound);
697 /* Too fragmented, unbind everything and retry */
698 mutex_lock(&eb->context->vm->mutex);
699 err = i915_gem_evict_vm(eb->context->vm);
700 mutex_unlock(&eb->context->vm->mutex);
709 pin_flags = PIN_USER;
713 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
715 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
718 return eb->buffer_count - 1;
721 static int eb_select_context(struct i915_execbuffer *eb)
723 struct i915_gem_context *ctx;
725 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
729 eb->gem_context = ctx;
730 if (rcu_access_pointer(ctx->vm))
731 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
733 eb->context_flags = 0;
734 if (test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags))
735 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
740 static int __eb_add_lut(struct i915_execbuffer *eb,
741 u32 handle, struct i915_vma *vma)
743 struct i915_gem_context *ctx = eb->gem_context;
744 struct i915_lut_handle *lut;
747 lut = i915_lut_handle_alloc();
752 if (!atomic_fetch_inc(&vma->open_count))
753 i915_vma_reopen(vma);
754 lut->handle = handle;
757 /* Check that the context hasn't been closed in the meantime */
759 if (!mutex_lock_interruptible(&ctx->lut_mutex)) {
760 struct i915_address_space *vm = rcu_access_pointer(ctx->vm);
762 if (unlikely(vm && vma->vm != vm))
763 err = -EAGAIN; /* user racing with ctx set-vm */
764 else if (likely(!i915_gem_context_is_closed(ctx)))
765 err = radix_tree_insert(&ctx->handles_vma, handle, vma);
768 if (err == 0) { /* And nor has this handle */
769 struct drm_i915_gem_object *obj = vma->obj;
771 spin_lock(&obj->lut_lock);
772 if (idr_find(&eb->file->object_idr, handle) == obj) {
773 list_add(&lut->obj_link, &obj->lut_list);
775 radix_tree_delete(&ctx->handles_vma, handle);
778 spin_unlock(&obj->lut_lock);
780 mutex_unlock(&ctx->lut_mutex);
790 i915_lut_handle_free(lut);
794 static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
796 struct i915_address_space *vm = eb->context->vm;
799 struct drm_i915_gem_object *obj;
800 struct i915_vma *vma;
804 vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
805 if (likely(vma && vma->vm == vm))
806 vma = i915_vma_tryget(vma);
811 obj = i915_gem_object_lookup(eb->file, handle);
813 return ERR_PTR(-ENOENT);
815 vma = i915_vma_instance(obj, vm, NULL);
817 i915_gem_object_put(obj);
821 err = __eb_add_lut(eb, handle, vma);
825 i915_gem_object_put(obj);
831 static int eb_lookup_vmas(struct i915_execbuffer *eb)
833 struct drm_i915_private *i915 = eb->i915;
834 unsigned int batch = eb_batch_index(eb);
838 INIT_LIST_HEAD(&eb->relocs);
840 for (i = 0; i < eb->buffer_count; i++) {
841 struct i915_vma *vma;
843 vma = eb_lookup_vma(eb, eb->exec[i].handle);
849 err = eb_validate_vma(eb, &eb->exec[i], vma);
855 eb_add_vma(eb, i, batch, vma);
858 if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) {
860 "Attempting to use self-modifying batch buffer\n");
864 if (range_overflows_t(u64,
865 eb->batch_start_offset, eb->batch_len,
866 eb->batch->vma->size)) {
867 drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
871 if (eb->batch_len == 0)
872 eb->batch_len = eb->batch->vma->size - eb->batch_start_offset;
873 if (unlikely(eb->batch_len == 0)) { /* impossible! */
874 drm_dbg(&i915->drm, "Invalid batch length\n");
881 eb->vma[i].vma = NULL;
885 static int eb_validate_vmas(struct i915_execbuffer *eb)
890 INIT_LIST_HEAD(&eb->unbound);
892 for (i = 0; i < eb->buffer_count; i++) {
893 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
894 struct eb_vma *ev = &eb->vma[i];
895 struct i915_vma *vma = ev->vma;
897 err = i915_gem_object_lock(vma->obj, &eb->ww);
901 if (eb_pin_vma(eb, entry, ev)) {
902 if (entry->offset != vma->node.start) {
903 entry->offset = vma->node.start | UPDATE;
904 eb->args->flags |= __EXEC_HAS_RELOC;
907 eb_unreserve_vma(ev);
909 list_add_tail(&ev->bind_link, &eb->unbound);
910 if (drm_mm_node_allocated(&vma->node)) {
911 err = i915_vma_unbind(vma);
917 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
918 eb_vma_misplaced(&eb->exec[i], vma, ev->flags));
921 if (!list_empty(&eb->unbound))
922 return eb_reserve(eb);
927 static struct eb_vma *
928 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
930 if (eb->lut_size < 0) {
931 if (handle >= -eb->lut_size)
933 return &eb->vma[handle];
935 struct hlist_head *head;
938 head = &eb->buckets[hash_32(handle, eb->lut_size)];
939 hlist_for_each_entry(ev, head, node) {
940 if (ev->handle == handle)
947 static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
949 const unsigned int count = eb->buffer_count;
952 for (i = 0; i < count; i++) {
953 struct eb_vma *ev = &eb->vma[i];
954 struct i915_vma *vma = ev->vma;
959 eb_unreserve_vma(ev);
968 static void eb_destroy(const struct i915_execbuffer *eb)
970 GEM_BUG_ON(eb->reloc_cache.rq);
972 if (eb->lut_size > 0)
977 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
978 const struct i915_vma *target)
980 return gen8_canonical_addr((int)reloc->delta + target->node.start);
983 static void reloc_cache_clear(struct reloc_cache *cache)
986 cache->rq_cmd = NULL;
991 static void reloc_cache_init(struct reloc_cache *cache,
992 struct drm_i915_private *i915)
996 /* Must be a variable in the struct to allow GCC to unroll. */
997 cache->gen = INTEL_GEN(i915);
998 cache->has_llc = HAS_LLC(i915);
999 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
1000 cache->has_fence = cache->gen < 4;
1001 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
1002 cache->node.flags = 0;
1003 reloc_cache_clear(cache);
1006 static inline void *unmask_page(unsigned long p)
1008 return (void *)(uintptr_t)(p & PAGE_MASK);
1011 static inline unsigned int unmask_flags(unsigned long p)
1013 return p & ~PAGE_MASK;
1016 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
1018 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
1020 struct drm_i915_private *i915 =
1021 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
1025 static void reloc_cache_put_pool(struct i915_execbuffer *eb, struct reloc_cache *cache)
1031 * This is a bit nasty, normally we keep objects locked until the end
1032 * of execbuffer, but we already submit this, and have to unlock before
1033 * dropping the reference. Fortunately we can only hold 1 pool node at
1034 * a time, so this should be harmless.
1036 i915_gem_ww_unlock_single(cache->pool->obj);
1037 intel_gt_buffer_pool_put(cache->pool);
1041 static void reloc_gpu_flush(struct i915_execbuffer *eb, struct reloc_cache *cache)
1043 struct drm_i915_gem_object *obj = cache->rq->batch->obj;
1045 GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32));
1046 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
1048 i915_gem_object_flush_map(obj);
1049 i915_gem_object_unpin_map(obj);
1051 intel_gt_chipset_flush(cache->rq->engine->gt);
1053 i915_request_add(cache->rq);
1054 reloc_cache_put_pool(eb, cache);
1055 reloc_cache_clear(cache);
1057 eb->reloc_pool = NULL;
1060 static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
1065 reloc_gpu_flush(eb, cache);
1070 vaddr = unmask_page(cache->vaddr);
1071 if (cache->vaddr & KMAP) {
1072 struct drm_i915_gem_object *obj =
1073 (struct drm_i915_gem_object *)cache->node.mm;
1074 if (cache->vaddr & CLFLUSH_AFTER)
1077 kunmap_atomic(vaddr);
1078 i915_gem_object_finish_access(obj);
1080 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1082 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1083 io_mapping_unmap_atomic((void __iomem *)vaddr);
1085 if (drm_mm_node_allocated(&cache->node)) {
1086 ggtt->vm.clear_range(&ggtt->vm,
1089 mutex_lock(&ggtt->vm.mutex);
1090 drm_mm_remove_node(&cache->node);
1091 mutex_unlock(&ggtt->vm.mutex);
1093 i915_vma_unpin((struct i915_vma *)cache->node.mm);
1101 static void *reloc_kmap(struct drm_i915_gem_object *obj,
1102 struct reloc_cache *cache,
1103 unsigned long pageno)
1109 kunmap_atomic(unmask_page(cache->vaddr));
1111 unsigned int flushes;
1114 err = i915_gem_object_prepare_write(obj, &flushes);
1116 return ERR_PTR(err);
1118 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1119 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1121 cache->vaddr = flushes | KMAP;
1122 cache->node.mm = (void *)obj;
1127 page = i915_gem_object_get_page(obj, pageno);
1129 set_page_dirty(page);
1131 vaddr = kmap_atomic(page);
1132 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1133 cache->page = pageno;
1138 static void *reloc_iomap(struct drm_i915_gem_object *obj,
1139 struct i915_execbuffer *eb,
1142 struct reloc_cache *cache = &eb->reloc_cache;
1143 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1144 unsigned long offset;
1148 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1149 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1151 struct i915_vma *vma;
1154 if (i915_gem_object_is_tiled(obj))
1155 return ERR_PTR(-EINVAL);
1157 if (use_cpu_reloc(cache, obj))
1160 err = i915_gem_object_set_to_gtt_domain(obj, true);
1162 return ERR_PTR(err);
1164 vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0,
1166 PIN_NONBLOCK /* NOWARN */ |
1168 if (vma == ERR_PTR(-EDEADLK))
1172 memset(&cache->node, 0, sizeof(cache->node));
1173 mutex_lock(&ggtt->vm.mutex);
1174 err = drm_mm_insert_node_in_range
1175 (&ggtt->vm.mm, &cache->node,
1176 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1177 0, ggtt->mappable_end,
1179 mutex_unlock(&ggtt->vm.mutex);
1180 if (err) /* no inactive aperture space, use cpu reloc */
1183 cache->node.start = vma->node.start;
1184 cache->node.mm = (void *)vma;
1188 offset = cache->node.start;
1189 if (drm_mm_node_allocated(&cache->node)) {
1190 ggtt->vm.insert_page(&ggtt->vm,
1191 i915_gem_object_get_dma_address(obj, page),
1192 offset, I915_CACHE_NONE, 0);
1194 offset += page << PAGE_SHIFT;
1197 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1200 cache->vaddr = (unsigned long)vaddr;
1205 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1206 struct i915_execbuffer *eb,
1209 struct reloc_cache *cache = &eb->reloc_cache;
1212 if (cache->page == page) {
1213 vaddr = unmask_page(cache->vaddr);
1216 if ((cache->vaddr & KMAP) == 0)
1217 vaddr = reloc_iomap(obj, eb, page);
1219 vaddr = reloc_kmap(obj, cache, page);
1225 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1227 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1228 if (flushes & CLFLUSH_BEFORE) {
1236 * Writes to the same cacheline are serialised by the CPU
1237 * (including clflush). On the write path, we only require
1238 * that it hits memory in an orderly fashion and place
1239 * mb barriers at the start and end of the relocation phase
1240 * to ensure ordering of clflush wrt to the system.
1242 if (flushes & CLFLUSH_AFTER)
1248 static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma)
1250 struct drm_i915_gem_object *obj = vma->obj;
1253 assert_vma_held(vma);
1255 if (obj->cache_dirty & ~obj->cache_coherent)
1256 i915_gem_clflush_object(obj, 0);
1257 obj->write_domain = 0;
1259 err = i915_request_await_object(rq, vma->obj, true);
1261 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1266 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1267 struct intel_engine_cs *engine,
1268 struct i915_vma *vma,
1271 struct reloc_cache *cache = &eb->reloc_cache;
1272 struct intel_gt_buffer_pool_node *pool = eb->reloc_pool;
1273 struct i915_request *rq;
1274 struct i915_vma *batch;
1279 pool = intel_gt_get_buffer_pool(engine->gt, PAGE_SIZE,
1284 return PTR_ERR(pool);
1286 eb->reloc_pool = NULL;
1288 err = i915_gem_object_lock(pool->obj, &eb->ww);
1292 cmd = i915_gem_object_pin_map(pool->obj, pool->type);
1298 memset32(cmd, 0, pool->obj->base.size / sizeof(u32));
1300 batch = i915_vma_instance(pool->obj, vma->vm, NULL);
1301 if (IS_ERR(batch)) {
1302 err = PTR_ERR(batch);
1306 err = i915_vma_pin_ww(batch, &eb->ww, 0, 0, PIN_USER | PIN_NONBLOCK);
1310 if (engine == eb->context->engine) {
1311 rq = i915_request_create(eb->context);
1313 struct intel_context *ce = eb->reloc_context;
1316 ce = intel_context_create(engine);
1322 i915_vm_put(ce->vm);
1323 ce->vm = i915_vm_get(eb->context->vm);
1324 eb->reloc_context = ce;
1327 err = intel_context_pin_ww(ce, &eb->ww);
1331 rq = i915_request_create(ce);
1332 intel_context_unpin(ce);
1339 err = intel_gt_buffer_pool_mark_active(pool, rq);
1343 err = reloc_move_to_gpu(rq, vma);
1347 err = eb->engine->emit_bb_start(rq,
1348 batch->node.start, PAGE_SIZE,
1349 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1353 assert_vma_held(batch);
1354 err = i915_request_await_object(rq, batch->obj, false);
1356 err = i915_vma_move_to_active(batch, rq, 0);
1361 i915_vma_unpin(batch);
1364 cache->rq_cmd = cmd;
1368 /* Return with batch mapping (cmd) still pinned */
1372 i915_request_set_error_once(rq, err);
1374 i915_request_add(rq);
1376 i915_vma_unpin(batch);
1378 i915_gem_object_unpin_map(pool->obj);
1380 eb->reloc_pool = pool;
1384 static bool reloc_can_use_engine(const struct intel_engine_cs *engine)
1386 return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6);
1389 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1390 struct i915_vma *vma,
1393 struct reloc_cache *cache = &eb->reloc_cache;
1396 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1397 reloc_gpu_flush(eb, cache);
1399 if (unlikely(!cache->rq)) {
1401 struct intel_engine_cs *engine = eb->engine;
1403 if (!reloc_can_use_engine(engine)) {
1404 engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0];
1406 return ERR_PTR(-ENODEV);
1409 err = __reloc_gpu_alloc(eb, engine, vma, len);
1411 return ERR_PTR(err);
1414 cmd = cache->rq_cmd + cache->rq_size;
1415 cache->rq_size += len;
1420 static inline bool use_reloc_gpu(struct i915_vma *vma)
1422 if (DBG_FORCE_RELOC == FORCE_GPU_RELOC)
1425 if (DBG_FORCE_RELOC)
1428 return !dma_resv_test_signaled_rcu(vma->resv, true);
1431 static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset)
1436 GEM_BUG_ON(vma->pages != vma->obj->mm.pages);
1438 page = i915_gem_object_get_page(vma->obj, offset >> PAGE_SHIFT);
1439 addr = PFN_PHYS(page_to_pfn(page));
1440 GEM_BUG_ON(overflows_type(addr, u32)); /* expected dma32 */
1442 return addr + offset_in_page(offset);
1445 static int __reloc_entry_gpu(struct i915_execbuffer *eb,
1446 struct i915_vma *vma,
1450 const unsigned int gen = eb->reloc_cache.gen;
1456 len = offset & 7 ? 8 : 5;
1462 batch = reloc_gpu(eb, vma, len);
1463 if (batch == ERR_PTR(-EDEADLK))
1465 else if (IS_ERR(batch))
1468 addr = gen8_canonical_addr(vma->node.start + offset);
1471 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1472 *batch++ = lower_32_bits(addr);
1473 *batch++ = upper_32_bits(addr);
1474 *batch++ = lower_32_bits(target_addr);
1476 addr = gen8_canonical_addr(addr + 4);
1478 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1479 *batch++ = lower_32_bits(addr);
1480 *batch++ = upper_32_bits(addr);
1481 *batch++ = upper_32_bits(target_addr);
1483 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1484 *batch++ = lower_32_bits(addr);
1485 *batch++ = upper_32_bits(addr);
1486 *batch++ = lower_32_bits(target_addr);
1487 *batch++ = upper_32_bits(target_addr);
1489 } else if (gen >= 6) {
1490 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1493 *batch++ = target_addr;
1494 } else if (IS_I965G(eb->i915)) {
1495 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1497 *batch++ = vma_phys_addr(vma, offset);
1498 *batch++ = target_addr;
1499 } else if (gen >= 4) {
1500 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1503 *batch++ = target_addr;
1504 } else if (gen >= 3 &&
1505 !(IS_I915G(eb->i915) || IS_I915GM(eb->i915))) {
1506 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1508 *batch++ = target_addr;
1510 *batch++ = MI_STORE_DWORD_IMM;
1511 *batch++ = vma_phys_addr(vma, offset);
1512 *batch++ = target_addr;
1518 static int reloc_entry_gpu(struct i915_execbuffer *eb,
1519 struct i915_vma *vma,
1523 if (eb->reloc_cache.vaddr)
1526 if (!use_reloc_gpu(vma))
1529 return __reloc_entry_gpu(eb, vma, offset, target_addr);
1533 relocate_entry(struct i915_vma *vma,
1534 const struct drm_i915_gem_relocation_entry *reloc,
1535 struct i915_execbuffer *eb,
1536 const struct i915_vma *target)
1538 u64 target_addr = relocation_target(reloc, target);
1539 u64 offset = reloc->offset;
1540 int reloc_gpu = reloc_entry_gpu(eb, vma, offset, target_addr);
1546 bool wide = eb->reloc_cache.use_64bit_reloc;
1550 vaddr = reloc_vaddr(vma->obj, eb,
1551 offset >> PAGE_SHIFT);
1553 return PTR_ERR(vaddr);
1555 GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32)));
1556 clflush_write32(vaddr + offset_in_page(offset),
1557 lower_32_bits(target_addr),
1558 eb->reloc_cache.vaddr);
1561 offset += sizeof(u32);
1568 return target->node.start | UPDATE;
1572 eb_relocate_entry(struct i915_execbuffer *eb,
1574 const struct drm_i915_gem_relocation_entry *reloc)
1576 struct drm_i915_private *i915 = eb->i915;
1577 struct eb_vma *target;
1580 /* we've already hold a reference to all valid objects */
1581 target = eb_get_vma(eb, reloc->target_handle);
1582 if (unlikely(!target))
1585 /* Validate that the target is in a valid r/w GPU domain */
1586 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1587 drm_dbg(&i915->drm, "reloc with multiple write domains: "
1588 "target %d offset %d "
1589 "read %08x write %08x",
1590 reloc->target_handle,
1591 (int) reloc->offset,
1592 reloc->read_domains,
1593 reloc->write_domain);
1596 if (unlikely((reloc->write_domain | reloc->read_domains)
1597 & ~I915_GEM_GPU_DOMAINS)) {
1598 drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: "
1599 "target %d offset %d "
1600 "read %08x write %08x",
1601 reloc->target_handle,
1602 (int) reloc->offset,
1603 reloc->read_domains,
1604 reloc->write_domain);
1608 if (reloc->write_domain) {
1609 target->flags |= EXEC_OBJECT_WRITE;
1612 * Sandybridge PPGTT errata: We need a global gtt mapping
1613 * for MI and pipe_control writes because the gpu doesn't
1614 * properly redirect them through the ppgtt for non_secure
1617 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1618 IS_GEN(eb->i915, 6)) {
1619 err = i915_vma_bind(target->vma,
1620 target->vma->obj->cache_level,
1628 * If the relocation already has the right value in it, no
1629 * more work needs to be done.
1631 if (!DBG_FORCE_RELOC &&
1632 gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
1635 /* Check that the relocation address is valid... */
1636 if (unlikely(reloc->offset >
1637 ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1638 drm_dbg(&i915->drm, "Relocation beyond object bounds: "
1639 "target %d offset %d size %d.\n",
1640 reloc->target_handle,
1642 (int)ev->vma->size);
1645 if (unlikely(reloc->offset & 3)) {
1646 drm_dbg(&i915->drm, "Relocation not 4-byte aligned: "
1647 "target %d offset %d.\n",
1648 reloc->target_handle,
1649 (int)reloc->offset);
1654 * If we write into the object, we need to force the synchronisation
1655 * barrier, either with an asynchronous clflush or if we executed the
1656 * patching using the GPU (though that should be serialised by the
1657 * timeline). To be completely sure, and since we are required to
1658 * do relocations we are already stalling, disable the user's opt
1659 * out of our synchronisation.
1661 ev->flags &= ~EXEC_OBJECT_ASYNC;
1663 /* and update the user's relocation entry */
1664 return relocate_entry(ev->vma, reloc, eb, target->vma);
1667 static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev)
1669 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1670 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1671 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1672 struct drm_i915_gem_relocation_entry __user *urelocs =
1673 u64_to_user_ptr(entry->relocs_ptr);
1674 unsigned long remain = entry->relocation_count;
1676 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1680 * We must check that the entire relocation array is safe
1681 * to read. However, if the array is not writable the user loses
1682 * the updated relocation values.
1684 if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs))))
1688 struct drm_i915_gem_relocation_entry *r = stack;
1689 unsigned int count =
1690 min_t(unsigned long, remain, ARRAY_SIZE(stack));
1691 unsigned int copied;
1694 * This is the fast path and we cannot handle a pagefault
1695 * whilst holding the struct mutex lest the user pass in the
1696 * relocations contained within a mmaped bo. For in such a case
1697 * we, the page fault handler would call i915_gem_fault() and
1698 * we would try to acquire the struct mutex again. Obviously
1699 * this is bad and so lockdep complains vehemently.
1701 pagefault_disable();
1702 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1704 if (unlikely(copied)) {
1711 u64 offset = eb_relocate_entry(eb, ev, r);
1713 if (likely(offset == 0)) {
1714 } else if ((s64)offset < 0) {
1715 remain = (int)offset;
1719 * Note that reporting an error now
1720 * leaves everything in an inconsistent
1721 * state as we have *already* changed
1722 * the relocation value inside the
1723 * object. As we have not changed the
1724 * reloc.presumed_offset or will not
1725 * change the execobject.offset, on the
1726 * call we may not rewrite the value
1727 * inside the object, leaving it
1728 * dangling and causing a GPU hang. Unless
1729 * userspace dynamically rebuilds the
1730 * relocations on each execbuf rather than
1731 * presume a static tree.
1733 * We did previously check if the relocations
1734 * were writable (access_ok), an error now
1735 * would be a strange race with mprotect,
1736 * having already demonstrated that we
1737 * can read from this userspace address.
1739 offset = gen8_canonical_addr(offset & ~UPDATE);
1741 &urelocs[r - stack].presumed_offset);
1743 } while (r++, --count);
1744 urelocs += ARRAY_SIZE(stack);
1747 reloc_cache_reset(&eb->reloc_cache, eb);
1752 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
1754 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1755 struct drm_i915_gem_relocation_entry *relocs =
1756 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1760 for (i = 0; i < entry->relocation_count; i++) {
1761 u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);
1763 if ((s64)offset < 0) {
1770 reloc_cache_reset(&eb->reloc_cache, eb);
1774 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1776 const char __user *addr, *end;
1778 char __maybe_unused c;
1780 size = entry->relocation_count;
1784 if (size > N_RELOC(ULONG_MAX))
1787 addr = u64_to_user_ptr(entry->relocs_ptr);
1788 size *= sizeof(struct drm_i915_gem_relocation_entry);
1789 if (!access_ok(addr, size))
1793 for (; addr < end; addr += PAGE_SIZE) {
1794 int err = __get_user(c, addr);
1798 return __get_user(c, end - 1);
1801 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1803 struct drm_i915_gem_relocation_entry *relocs;
1804 const unsigned int count = eb->buffer_count;
1808 for (i = 0; i < count; i++) {
1809 const unsigned int nreloc = eb->exec[i].relocation_count;
1810 struct drm_i915_gem_relocation_entry __user *urelocs;
1812 unsigned long copied;
1817 err = check_relocations(&eb->exec[i]);
1821 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1822 size = nreloc * sizeof(*relocs);
1824 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1830 /* copy_from_user is limited to < 4GiB */
1834 min_t(u64, BIT_ULL(31), size - copied);
1836 if (__copy_from_user((char *)relocs + copied,
1837 (char __user *)urelocs + copied,
1842 } while (copied < size);
1845 * As we do not update the known relocation offsets after
1846 * relocating (due to the complexities in lock handling),
1847 * we need to mark them as invalid now so that we force the
1848 * relocation processing next time. Just in case the target
1849 * object is evicted and then rebound into its old
1850 * presumed_offset before the next execbuffer - if that
1851 * happened we would make the mistake of assuming that the
1852 * relocations were valid.
1854 if (!user_access_begin(urelocs, size))
1857 for (copied = 0; copied < nreloc; copied++)
1859 &urelocs[copied].presumed_offset,
1863 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1875 relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1876 if (eb->exec[i].relocation_count)
1882 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1884 const unsigned int count = eb->buffer_count;
1887 for (i = 0; i < count; i++) {
1890 err = check_relocations(&eb->exec[i]);
1898 static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb,
1899 struct i915_request *rq)
1901 bool have_copy = false;
1906 if (signal_pending(current)) {
1911 /* We may process another execbuffer during the unlock... */
1912 eb_release_vmas(eb, false);
1913 i915_gem_ww_ctx_fini(&eb->ww);
1916 /* nonblocking is always false */
1917 if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
1918 MAX_SCHEDULE_TIMEOUT) < 0) {
1919 i915_request_put(rq);
1926 i915_request_put(rq);
1931 * We take 3 passes through the slowpatch.
1933 * 1 - we try to just prefault all the user relocation entries and
1934 * then attempt to reuse the atomic pagefault disabled fast path again.
1936 * 2 - we copy the user entries to a local buffer here outside of the
1937 * local and allow ourselves to wait upon any rendering before
1940 * 3 - we already have a local copy of the relocation entries, but
1941 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1944 err = eb_prefault_relocations(eb);
1945 } else if (!have_copy) {
1946 err = eb_copy_relocations(eb);
1947 have_copy = err == 0;
1954 flush_workqueue(eb->i915->mm.userptr_wq);
1957 i915_gem_ww_ctx_init(&eb->ww, true);
1961 /* reacquire the objects */
1963 rq = eb_pin_engine(eb, false);
1970 /* We didn't throttle, should be NULL */
1973 err = eb_validate_vmas(eb);
1977 GEM_BUG_ON(!eb->batch);
1979 list_for_each_entry(ev, &eb->relocs, reloc_link) {
1981 pagefault_disable();
1982 err = eb_relocate_vma(eb, ev);
1987 err = eb_relocate_vma_slow(eb, ev);
1993 if (err == -EDEADLK)
1996 if (err && !have_copy)
2002 /* as last step, parse the command buffer */
2008 * Leave the user relocations as are, this is the painfully slow path,
2009 * and we want to avoid the complication of dropping the lock whilst
2010 * having buffers reserved in the aperture and so causing spurious
2011 * ENOSPC for random operations.
2015 if (err == -EDEADLK) {
2016 eb_release_vmas(eb, false);
2017 err = i915_gem_ww_ctx_backoff(&eb->ww);
2019 goto repeat_validate;
2027 const unsigned int count = eb->buffer_count;
2030 for (i = 0; i < count; i++) {
2031 const struct drm_i915_gem_exec_object2 *entry =
2033 struct drm_i915_gem_relocation_entry *relocs;
2035 if (!entry->relocation_count)
2038 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
2044 i915_request_put(rq);
2049 static int eb_relocate_parse(struct i915_execbuffer *eb)
2052 struct i915_request *rq = NULL;
2053 bool throttle = true;
2056 rq = eb_pin_engine(eb, throttle);
2060 if (err != -EDEADLK)
2067 bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
2069 /* Need to drop all locks now for throttling, take slowpath */
2070 err = i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, 0);
2071 if (err == -ETIME) {
2074 i915_request_put(rq);
2079 i915_request_put(rq);
2083 /* only throttle once, even if we didn't need to throttle */
2086 err = eb_validate_vmas(eb);
2092 /* The objects are in their final locations, apply the relocations. */
2093 if (eb->args->flags & __EXEC_HAS_RELOC) {
2096 list_for_each_entry(ev, &eb->relocs, reloc_link) {
2097 err = eb_relocate_vma(eb, ev);
2102 if (err == -EDEADLK)
2112 if (err == -EDEADLK) {
2113 eb_release_vmas(eb, false);
2114 err = i915_gem_ww_ctx_backoff(&eb->ww);
2122 err = eb_relocate_parse_slow(eb, rq);
2125 * If the user expects the execobject.offset and
2126 * reloc.presumed_offset to be an exact match,
2127 * as for using NO_RELOC, then we cannot update
2128 * the execobject.offset until we have completed
2131 eb->args->flags &= ~__EXEC_HAS_RELOC;
2136 static int eb_move_to_gpu(struct i915_execbuffer *eb)
2138 const unsigned int count = eb->buffer_count;
2139 unsigned int i = count;
2143 struct eb_vma *ev = &eb->vma[i];
2144 struct i915_vma *vma = ev->vma;
2145 unsigned int flags = ev->flags;
2146 struct drm_i915_gem_object *obj = vma->obj;
2148 assert_vma_held(vma);
2150 if (flags & EXEC_OBJECT_CAPTURE) {
2151 struct i915_capture_list *capture;
2153 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
2155 capture->next = eb->request->capture_list;
2157 eb->request->capture_list = capture;
2162 * If the GPU is not _reading_ through the CPU cache, we need
2163 * to make sure that any writes (both previous GPU writes from
2164 * before a change in snooping levels and normal CPU writes)
2165 * caught in that cache are flushed to main memory.
2168 * obj->cache_dirty &&
2169 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
2170 * but gcc's optimiser doesn't handle that as well and emits
2171 * two jumps instead of one. Maybe one day...
2173 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
2174 if (i915_gem_clflush_object(obj, 0))
2175 flags &= ~EXEC_OBJECT_ASYNC;
2178 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
2179 err = i915_request_await_object
2180 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
2184 err = i915_vma_move_to_active(vma, eb->request, flags);
2190 /* Unconditionally flush any chipset caches (for streaming writes). */
2191 intel_gt_chipset_flush(eb->engine->gt);
2195 i915_request_set_error_once(eb->request, err);
2199 static int i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
2201 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
2204 /* Kernel clipping was a DRI1 misfeature */
2205 if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
2206 I915_EXEC_USE_EXTENSIONS))) {
2207 if (exec->num_cliprects || exec->cliprects_ptr)
2211 if (exec->DR4 == 0xffffffff) {
2212 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
2215 if (exec->DR1 || exec->DR4)
2218 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
2224 static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
2229 if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) {
2230 drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
2234 cs = intel_ring_begin(rq, 4 * 2 + 2);
2238 *cs++ = MI_LOAD_REGISTER_IMM(4);
2239 for (i = 0; i < 4; i++) {
2240 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
2244 intel_ring_advance(rq, cs);
2249 static struct i915_vma *
2250 shadow_batch_pin(struct i915_execbuffer *eb,
2251 struct drm_i915_gem_object *obj,
2252 struct i915_address_space *vm,
2255 struct i915_vma *vma;
2258 vma = i915_vma_instance(obj, vm, NULL);
2262 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags);
2264 return ERR_PTR(err);
2269 struct eb_parse_work {
2270 struct dma_fence_work base;
2271 struct intel_engine_cs *engine;
2272 struct i915_vma *batch;
2273 struct i915_vma *shadow;
2274 struct i915_vma *trampoline;
2275 unsigned long batch_offset;
2276 unsigned long batch_length;
2279 static int __eb_parse(struct dma_fence_work *work)
2281 struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
2283 return intel_engine_cmd_parser(pw->engine,
2291 static void __eb_parse_release(struct dma_fence_work *work)
2293 struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
2296 i915_active_release(&pw->trampoline->active);
2297 i915_active_release(&pw->shadow->active);
2298 i915_active_release(&pw->batch->active);
2301 static const struct dma_fence_work_ops eb_parse_ops = {
2304 .release = __eb_parse_release,
2308 __parser_mark_active(struct i915_vma *vma,
2309 struct intel_timeline *tl,
2310 struct dma_fence *fence)
2312 struct intel_gt_buffer_pool_node *node = vma->private;
2314 return i915_active_ref(&node->active, tl->fence_context, fence);
2318 parser_mark_active(struct eb_parse_work *pw, struct intel_timeline *tl)
2322 mutex_lock(&tl->mutex);
2324 err = __parser_mark_active(pw->shadow, tl, &pw->base.dma);
2328 if (pw->trampoline) {
2329 err = __parser_mark_active(pw->trampoline, tl, &pw->base.dma);
2335 mutex_unlock(&tl->mutex);
2339 static int eb_parse_pipeline(struct i915_execbuffer *eb,
2340 struct i915_vma *shadow,
2341 struct i915_vma *trampoline)
2343 struct eb_parse_work *pw;
2346 GEM_BUG_ON(overflows_type(eb->batch_start_offset, pw->batch_offset));
2347 GEM_BUG_ON(overflows_type(eb->batch_len, pw->batch_length));
2349 pw = kzalloc(sizeof(*pw), GFP_KERNEL);
2353 err = i915_active_acquire(&eb->batch->vma->active);
2357 err = i915_active_acquire(&shadow->active);
2362 err = i915_active_acquire(&trampoline->active);
2367 dma_fence_work_init(&pw->base, &eb_parse_ops);
2369 pw->engine = eb->engine;
2370 pw->batch = eb->batch->vma;
2371 pw->batch_offset = eb->batch_start_offset;
2372 pw->batch_length = eb->batch_len;
2373 pw->shadow = shadow;
2374 pw->trampoline = trampoline;
2376 /* Mark active refs early for this worker, in case we get interrupted */
2377 err = parser_mark_active(pw, eb->context->timeline);
2381 err = dma_resv_reserve_shared(pw->batch->resv, 1);
2385 /* Wait for all writes (and relocs) into the batch to complete */
2386 err = i915_sw_fence_await_reservation(&pw->base.chain,
2387 pw->batch->resv, NULL, false,
2392 /* Keep the batch alive and unwritten as we parse */
2393 dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma);
2395 /* Force execution to wait for completion of the parser */
2396 dma_resv_add_excl_fence(shadow->resv, &pw->base.dma);
2398 dma_fence_work_commit_imm(&pw->base);
2402 i915_sw_fence_set_error_once(&pw->base.chain, err);
2403 dma_fence_work_commit_imm(&pw->base);
2407 i915_active_release(&shadow->active);
2409 i915_active_release(&eb->batch->vma->active);
2415 static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma)
2418 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2419 * batch" bit. Hence we need to pin secure batches into the global gtt.
2420 * hsw should have this fixed, but bdw mucks it up again. */
2421 if (eb->batch_flags & I915_DISPATCH_SECURE)
2422 return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, 0);
2427 static int eb_parse(struct i915_execbuffer *eb)
2429 struct drm_i915_private *i915 = eb->i915;
2430 struct intel_gt_buffer_pool_node *pool = eb->batch_pool;
2431 struct i915_vma *shadow, *trampoline, *batch;
2435 if (!eb_use_cmdparser(eb)) {
2436 batch = eb_dispatch_secure(eb, eb->batch->vma);
2438 return PTR_ERR(batch);
2443 len = eb->batch_len;
2444 if (!CMDPARSER_USES_GGTT(eb->i915)) {
2446 * ppGTT backed shadow buffers must be mapped RO, to prevent
2447 * post-scan tampering
2449 if (!eb->context->vm->has_read_only) {
2451 "Cannot prevent post-scan tampering without RO capable vm\n");
2455 len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
2457 if (unlikely(len < eb->batch_len)) /* last paranoid check of overflow */
2461 pool = intel_gt_get_buffer_pool(eb->engine->gt, len,
2464 return PTR_ERR(pool);
2465 eb->batch_pool = pool;
2468 err = i915_gem_object_lock(pool->obj, &eb->ww);
2472 shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER);
2473 if (IS_ERR(shadow)) {
2474 err = PTR_ERR(shadow);
2477 i915_gem_object_set_readonly(shadow->obj);
2478 shadow->private = pool;
2481 if (CMDPARSER_USES_GGTT(eb->i915)) {
2482 trampoline = shadow;
2484 shadow = shadow_batch_pin(eb, pool->obj,
2485 &eb->engine->gt->ggtt->vm,
2487 if (IS_ERR(shadow)) {
2488 err = PTR_ERR(shadow);
2489 shadow = trampoline;
2492 shadow->private = pool;
2494 eb->batch_flags |= I915_DISPATCH_SECURE;
2497 batch = eb_dispatch_secure(eb, shadow);
2498 if (IS_ERR(batch)) {
2499 err = PTR_ERR(batch);
2500 goto err_trampoline;
2503 err = eb_parse_pipeline(eb, shadow, trampoline);
2505 goto err_unpin_batch;
2507 eb->batch = &eb->vma[eb->buffer_count++];
2508 eb->batch->vma = i915_vma_get(shadow);
2509 eb->batch->flags = __EXEC_OBJECT_HAS_PIN;
2511 eb->trampoline = trampoline;
2512 eb->batch_start_offset = 0;
2516 eb->batch = &eb->vma[eb->buffer_count++];
2517 eb->batch->flags = __EXEC_OBJECT_HAS_PIN;
2518 eb->batch->vma = i915_vma_get(batch);
2524 i915_vma_unpin(batch);
2527 i915_vma_unpin(trampoline);
2529 i915_vma_unpin(shadow);
2534 static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
2538 if (intel_context_nopreempt(eb->context))
2539 __set_bit(I915_FENCE_FLAG_NOPREEMPT, &eb->request->fence.flags);
2541 err = eb_move_to_gpu(eb);
2545 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2546 err = i915_reset_gen7_sol_offsets(eb->request);
2552 * After we completed waiting for other engines (using HW semaphores)
2553 * then we can signal that this request/batch is ready to run. This
2554 * allows us to determine if the batch is still waiting on the GPU
2555 * or actually running by checking the breadcrumb.
2557 if (eb->engine->emit_init_breadcrumb) {
2558 err = eb->engine->emit_init_breadcrumb(eb->request);
2563 err = eb->engine->emit_bb_start(eb->request,
2565 eb->batch_start_offset,
2571 if (eb->trampoline) {
2572 GEM_BUG_ON(eb->batch_start_offset);
2573 err = eb->engine->emit_bb_start(eb->request,
2574 eb->trampoline->node.start +
2584 static int num_vcs_engines(const struct drm_i915_private *i915)
2586 return hweight_long(VDBOX_MASK(&i915->gt));
2590 * Find one BSD ring to dispatch the corresponding BSD command.
2591 * The engine index is returned.
2594 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2595 struct drm_file *file)
2597 struct drm_i915_file_private *file_priv = file->driver_priv;
2599 /* Check whether the file_priv has already selected one ring. */
2600 if ((int)file_priv->bsd_engine < 0)
2601 file_priv->bsd_engine =
2602 get_random_int() % num_vcs_engines(dev_priv);
2604 return file_priv->bsd_engine;
2607 static const enum intel_engine_id user_ring_map[] = {
2608 [I915_EXEC_DEFAULT] = RCS0,
2609 [I915_EXEC_RENDER] = RCS0,
2610 [I915_EXEC_BLT] = BCS0,
2611 [I915_EXEC_BSD] = VCS0,
2612 [I915_EXEC_VEBOX] = VECS0
2615 static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce)
2617 struct intel_ring *ring = ce->ring;
2618 struct intel_timeline *tl = ce->timeline;
2619 struct i915_request *rq;
2622 * Completely unscientific finger-in-the-air estimates for suitable
2623 * maximum user request size (to avoid blocking) and then backoff.
2625 if (intel_ring_update_space(ring) >= PAGE_SIZE)
2629 * Find a request that after waiting upon, there will be at least half
2630 * the ring available. The hysteresis allows us to compete for the
2631 * shared ring and should mean that we sleep less often prior to
2632 * claiming our resources, but not so long that the ring completely
2633 * drains before we can submit our next request.
2635 list_for_each_entry(rq, &tl->requests, link) {
2636 if (rq->ring != ring)
2639 if (__intel_ring_space(rq->postfix,
2640 ring->emit, ring->size) > ring->size / 2)
2643 if (&rq->link == &tl->requests)
2644 return NULL; /* weird, we will check again later for real */
2646 return i915_request_get(rq);
2649 static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
2651 struct intel_context *ce = eb->context;
2652 struct intel_timeline *tl;
2653 struct i915_request *rq = NULL;
2656 GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
2658 if (unlikely(intel_context_is_banned(ce)))
2659 return ERR_PTR(-EIO);
2662 * Pinning the contexts may generate requests in order to acquire
2663 * GGTT space, so do this first before we reserve a seqno for
2666 err = intel_context_pin_ww(ce, &eb->ww);
2668 return ERR_PTR(err);
2671 * Take a local wakeref for preparing to dispatch the execbuf as
2672 * we expect to access the hardware fairly frequently in the
2673 * process, and require the engine to be kept awake between accesses.
2674 * Upon dispatch, we acquire another prolonged wakeref that we hold
2675 * until the timeline is idle, which in turn releases the wakeref
2676 * taken on the engine, and the parent device.
2678 tl = intel_context_timeline_lock(ce);
2680 intel_context_unpin(ce);
2681 return ERR_CAST(tl);
2684 intel_context_enter(ce);
2686 rq = eb_throttle(eb, ce);
2687 intel_context_timeline_unlock(tl);
2689 eb->args->flags |= __EXEC_ENGINE_PINNED;
2693 static void eb_unpin_engine(struct i915_execbuffer *eb)
2695 struct intel_context *ce = eb->context;
2696 struct intel_timeline *tl = ce->timeline;
2698 if (!(eb->args->flags & __EXEC_ENGINE_PINNED))
2701 eb->args->flags &= ~__EXEC_ENGINE_PINNED;
2703 mutex_lock(&tl->mutex);
2704 intel_context_exit(ce);
2705 mutex_unlock(&tl->mutex);
2707 intel_context_unpin(ce);
2711 eb_select_legacy_ring(struct i915_execbuffer *eb)
2713 struct drm_i915_private *i915 = eb->i915;
2714 struct drm_i915_gem_execbuffer2 *args = eb->args;
2715 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2717 if (user_ring_id != I915_EXEC_BSD &&
2718 (args->flags & I915_EXEC_BSD_MASK)) {
2720 "execbuf with non bsd ring but with invalid "
2721 "bsd dispatch flags: %d\n", (int)(args->flags));
2725 if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) {
2726 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2728 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2729 bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
2730 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2731 bsd_idx <= I915_EXEC_BSD_RING2) {
2732 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2736 "execbuf with unknown bsd ring: %u\n",
2741 return _VCS(bsd_idx);
2744 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2745 drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n",
2750 return user_ring_map[user_ring_id];
2754 eb_select_engine(struct i915_execbuffer *eb)
2756 struct intel_context *ce;
2760 if (i915_gem_context_user_engines(eb->gem_context))
2761 idx = eb->args->flags & I915_EXEC_RING_MASK;
2763 idx = eb_select_legacy_ring(eb);
2765 ce = i915_gem_context_get_engine(eb->gem_context, idx);
2769 intel_gt_pm_get(ce->engine->gt);
2771 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
2772 err = intel_context_alloc_state(ce);
2778 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2779 * EIO if the GPU is already wedged.
2781 err = intel_gt_terminally_wedged(ce->engine->gt);
2786 eb->engine = ce->engine;
2789 * Make sure engine pool stays alive even if we call intel_context_put
2790 * during ww handling. The pool is destroyed when last pm reference
2791 * is dropped, which breaks our -EDEADLK handling.
2796 intel_gt_pm_put(ce->engine->gt);
2797 intel_context_put(ce);
2802 eb_put_engine(struct i915_execbuffer *eb)
2804 intel_gt_pm_put(eb->engine->gt);
2805 intel_context_put(eb->context);
2809 __free_fence_array(struct eb_fence *fences, unsigned int n)
2812 drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
2813 dma_fence_put(fences[n].dma_fence);
2814 kfree(fences[n].chain_fence);
2820 add_timeline_fence_array(struct i915_execbuffer *eb,
2821 const struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences)
2823 struct drm_i915_gem_exec_fence __user *user_fences;
2824 u64 __user *user_values;
2829 nfences = timeline_fences->fence_count;
2833 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2834 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2835 if (nfences > min_t(unsigned long,
2836 ULONG_MAX / sizeof(*user_fences),
2837 SIZE_MAX / sizeof(*f)) - eb->num_fences)
2840 user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
2841 if (!access_ok(user_fences, nfences * sizeof(*user_fences)))
2844 user_values = u64_to_user_ptr(timeline_fences->values_ptr);
2845 if (!access_ok(user_values, nfences * sizeof(*user_values)))
2848 f = krealloc(eb->fences,
2849 (eb->num_fences + nfences) * sizeof(*f),
2850 __GFP_NOWARN | GFP_KERNEL);
2855 f += eb->num_fences;
2857 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2858 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2861 struct drm_i915_gem_exec_fence user_fence;
2862 struct drm_syncobj *syncobj;
2863 struct dma_fence *fence = NULL;
2866 if (__copy_from_user(&user_fence,
2868 sizeof(user_fence)))
2871 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2874 if (__get_user(point, user_values++))
2877 syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2879 DRM_DEBUG("Invalid syncobj handle provided\n");
2883 fence = drm_syncobj_fence_get(syncobj);
2885 if (!fence && user_fence.flags &&
2886 !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2887 DRM_DEBUG("Syncobj handle has no fence\n");
2888 drm_syncobj_put(syncobj);
2893 err = dma_fence_chain_find_seqno(&fence, point);
2895 if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2896 DRM_DEBUG("Syncobj handle missing requested point %llu\n", point);
2897 dma_fence_put(fence);
2898 drm_syncobj_put(syncobj);
2903 * A point might have been signaled already and
2904 * garbage collected from the timeline. In this case
2905 * just ignore the point and carry on.
2907 if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2908 drm_syncobj_put(syncobj);
2913 * For timeline syncobjs we need to preallocate chains for
2916 if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
2918 * Waiting and signaling the same point (when point !=
2919 * 0) would break the timeline.
2921 if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2922 DRM_DEBUG("Trying to wait & signal the same timeline point.\n");
2923 dma_fence_put(fence);
2924 drm_syncobj_put(syncobj);
2929 kmalloc(sizeof(*f->chain_fence),
2931 if (!f->chain_fence) {
2932 drm_syncobj_put(syncobj);
2933 dma_fence_put(fence);
2937 f->chain_fence = NULL;
2940 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2941 f->dma_fence = fence;
2950 static int add_fence_array(struct i915_execbuffer *eb)
2952 struct drm_i915_gem_execbuffer2 *args = eb->args;
2953 struct drm_i915_gem_exec_fence __user *user;
2954 unsigned long num_fences = args->num_cliprects;
2957 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2963 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2964 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2965 if (num_fences > min_t(unsigned long,
2966 ULONG_MAX / sizeof(*user),
2967 SIZE_MAX / sizeof(*f) - eb->num_fences))
2970 user = u64_to_user_ptr(args->cliprects_ptr);
2971 if (!access_ok(user, num_fences * sizeof(*user)))
2974 f = krealloc(eb->fences,
2975 (eb->num_fences + num_fences) * sizeof(*f),
2976 __GFP_NOWARN | GFP_KERNEL);
2981 f += eb->num_fences;
2982 while (num_fences--) {
2983 struct drm_i915_gem_exec_fence user_fence;
2984 struct drm_syncobj *syncobj;
2985 struct dma_fence *fence = NULL;
2987 if (__copy_from_user(&user_fence, user++, sizeof(user_fence)))
2990 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2993 syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2995 DRM_DEBUG("Invalid syncobj handle provided\n");
2999 if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
3000 fence = drm_syncobj_fence_get(syncobj);
3002 DRM_DEBUG("Syncobj handle has no fence\n");
3003 drm_syncobj_put(syncobj);
3008 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
3009 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
3011 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
3012 f->dma_fence = fence;
3014 f->chain_fence = NULL;
3022 static void put_fence_array(struct eb_fence *fences, int num_fences)
3025 __free_fence_array(fences, num_fences);
3029 await_fence_array(struct i915_execbuffer *eb)
3034 for (n = 0; n < eb->num_fences; n++) {
3035 struct drm_syncobj *syncobj;
3038 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
3040 if (!eb->fences[n].dma_fence)
3043 err = i915_request_await_dma_fence(eb->request,
3044 eb->fences[n].dma_fence);
3052 static void signal_fence_array(const struct i915_execbuffer *eb)
3054 struct dma_fence * const fence = &eb->request->fence;
3057 for (n = 0; n < eb->num_fences; n++) {
3058 struct drm_syncobj *syncobj;
3061 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
3062 if (!(flags & I915_EXEC_FENCE_SIGNAL))
3065 if (eb->fences[n].chain_fence) {
3066 drm_syncobj_add_point(syncobj,
3067 eb->fences[n].chain_fence,
3069 eb->fences[n].value);
3071 * The chain's ownership is transferred to the
3074 eb->fences[n].chain_fence = NULL;
3076 drm_syncobj_replace_fence(syncobj, fence);
3082 parse_timeline_fences(struct i915_user_extension __user *ext, void *data)
3084 struct i915_execbuffer *eb = data;
3085 struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
3087 if (copy_from_user(&timeline_fences, ext, sizeof(timeline_fences)))
3090 return add_timeline_fence_array(eb, &timeline_fences);
3093 static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
3095 struct i915_request *rq, *rn;
3097 list_for_each_entry_safe(rq, rn, &tl->requests, link)
3098 if (rq == end || !i915_request_retire(rq))
3102 static int eb_request_add(struct i915_execbuffer *eb, int err)
3104 struct i915_request *rq = eb->request;
3105 struct intel_timeline * const tl = i915_request_timeline(rq);
3106 struct i915_sched_attr attr = {};
3107 struct i915_request *prev;
3109 lockdep_assert_held(&tl->mutex);
3110 lockdep_unpin_lock(&tl->mutex, rq->cookie);
3112 trace_i915_request_add(rq);
3114 prev = __i915_request_commit(rq);
3116 /* Check that the context wasn't destroyed before submission */
3117 if (likely(!intel_context_is_closed(eb->context))) {
3118 attr = eb->gem_context->sched;
3120 /* Serialise with context_close via the add_to_timeline */
3121 i915_request_set_error_once(rq, -ENOENT);
3122 __i915_request_skip(rq);
3123 err = -ENOENT; /* override any transient errors */
3126 __i915_request_queue(rq, &attr);
3128 /* Try to clean up the client's timeline after submitting the request */
3130 retire_requests(tl, prev);
3132 mutex_unlock(&tl->mutex);
3137 static const i915_user_extension_fn execbuf_extensions[] = {
3138 [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
3142 parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
3143 struct i915_execbuffer *eb)
3145 if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
3148 /* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
3149 * have another flag also using it at the same time.
3151 if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
3154 if (args->num_cliprects != 0)
3157 return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
3159 ARRAY_SIZE(execbuf_extensions),
3164 i915_gem_do_execbuffer(struct drm_device *dev,
3165 struct drm_file *file,
3166 struct drm_i915_gem_execbuffer2 *args,
3167 struct drm_i915_gem_exec_object2 *exec)
3169 struct drm_i915_private *i915 = to_i915(dev);
3170 struct i915_execbuffer eb;
3171 struct dma_fence *in_fence = NULL;
3172 struct sync_file *out_fence = NULL;
3173 struct i915_vma *batch;
3174 int out_fence_fd = -1;
3177 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
3178 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
3179 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
3184 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
3185 args->flags |= __EXEC_HAS_RELOC;
3188 eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
3189 eb.vma[0].vma = NULL;
3190 eb.reloc_pool = eb.batch_pool = NULL;
3191 eb.reloc_context = NULL;
3193 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
3194 reloc_cache_init(&eb.reloc_cache, eb.i915);
3196 eb.buffer_count = args->buffer_count;
3197 eb.batch_start_offset = args->batch_start_offset;
3198 eb.batch_len = args->batch_len;
3199 eb.trampoline = NULL;
3205 if (args->flags & I915_EXEC_SECURE) {
3206 if (INTEL_GEN(i915) >= 11)
3209 /* Return -EPERM to trigger fallback code on old binaries. */
3210 if (!HAS_SECURE_BATCHES(i915))
3213 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
3216 eb.batch_flags |= I915_DISPATCH_SECURE;
3218 if (args->flags & I915_EXEC_IS_PINNED)
3219 eb.batch_flags |= I915_DISPATCH_PINNED;
3221 err = parse_execbuf2_extensions(args, &eb);
3225 err = add_fence_array(&eb);
3229 #define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT)
3230 if (args->flags & IN_FENCES) {
3231 if ((args->flags & IN_FENCES) == IN_FENCES)
3234 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
3242 if (args->flags & I915_EXEC_FENCE_OUT) {
3243 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3244 if (out_fence_fd < 0) {
3250 err = eb_create(&eb);
3254 GEM_BUG_ON(!eb.lut_size);
3256 err = eb_select_context(&eb);
3260 err = eb_select_engine(&eb);
3264 err = eb_lookup_vmas(&eb);
3266 eb_release_vmas(&eb, true);
3270 i915_gem_ww_ctx_init(&eb.ww, true);
3272 err = eb_relocate_parse(&eb);
3275 * If the user expects the execobject.offset and
3276 * reloc.presumed_offset to be an exact match,
3277 * as for using NO_RELOC, then we cannot update
3278 * the execobject.offset until we have completed
3281 args->flags &= ~__EXEC_HAS_RELOC;
3285 ww_acquire_done(&eb.ww.ctx);
3287 batch = eb.batch->vma;
3289 /* All GPU relocation batches must be submitted prior to the user rq */
3290 GEM_BUG_ON(eb.reloc_cache.rq);
3292 /* Allocate a request for this batch buffer nice and early. */
3293 eb.request = i915_request_create(eb.context);
3294 if (IS_ERR(eb.request)) {
3295 err = PTR_ERR(eb.request);
3300 if (args->flags & I915_EXEC_FENCE_SUBMIT)
3301 err = i915_request_await_execution(eb.request,
3303 eb.engine->bond_execute);
3305 err = i915_request_await_dma_fence(eb.request,
3312 err = await_fence_array(&eb);
3317 if (out_fence_fd != -1) {
3318 out_fence = sync_file_create(&eb.request->fence);
3326 * Whilst this request exists, batch_obj will be on the
3327 * active_list, and so will hold the active reference. Only when this
3328 * request is retired will the the batch_obj be moved onto the
3329 * inactive_list and lose its active reference. Hence we do not need
3330 * to explicitly hold another reference here.
3332 eb.request->batch = batch;
3334 intel_gt_buffer_pool_mark_active(eb.batch_pool, eb.request);
3336 trace_i915_request_queue(eb.request, eb.batch_flags);
3337 err = eb_submit(&eb, batch);
3339 i915_request_get(eb.request);
3340 err = eb_request_add(&eb, err);
3343 signal_fence_array(&eb);
3347 fd_install(out_fence_fd, out_fence->file);
3348 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
3349 args->rsvd2 |= (u64)out_fence_fd << 32;
3352 fput(out_fence->file);
3355 i915_request_put(eb.request);
3358 eb_release_vmas(&eb, true);
3360 i915_vma_unpin(eb.trampoline);
3361 WARN_ON(err == -EDEADLK);
3362 i915_gem_ww_ctx_fini(&eb.ww);
3365 intel_gt_buffer_pool_put(eb.batch_pool);
3367 intel_gt_buffer_pool_put(eb.reloc_pool);
3368 if (eb.reloc_context)
3369 intel_context_put(eb.reloc_context);
3373 i915_gem_context_put(eb.gem_context);
3377 if (out_fence_fd != -1)
3378 put_unused_fd(out_fence_fd);
3380 dma_fence_put(in_fence);
3382 put_fence_array(eb.fences, eb.num_fences);
3386 static size_t eb_element_size(void)
3388 return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma);
3391 static bool check_buffer_count(size_t count)
3393 const size_t sz = eb_element_size();
3396 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
3397 * array size (see eb_create()). Otherwise, we can accept an array as
3398 * large as can be addressed (though use large arrays at your peril)!
3401 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
3405 * Legacy execbuffer just creates an exec2 list from the original exec object
3406 * list array and passes it to the real function.
3409 i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
3410 struct drm_file *file)
3412 struct drm_i915_private *i915 = to_i915(dev);
3413 struct drm_i915_gem_execbuffer *args = data;
3414 struct drm_i915_gem_execbuffer2 exec2;
3415 struct drm_i915_gem_exec_object *exec_list = NULL;
3416 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3417 const size_t count = args->buffer_count;
3421 if (!check_buffer_count(count)) {
3422 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3426 exec2.buffers_ptr = args->buffers_ptr;
3427 exec2.buffer_count = args->buffer_count;
3428 exec2.batch_start_offset = args->batch_start_offset;
3429 exec2.batch_len = args->batch_len;
3430 exec2.DR1 = args->DR1;
3431 exec2.DR4 = args->DR4;
3432 exec2.num_cliprects = args->num_cliprects;
3433 exec2.cliprects_ptr = args->cliprects_ptr;
3434 exec2.flags = I915_EXEC_RENDER;
3435 i915_execbuffer2_set_context_id(exec2, 0);
3437 err = i915_gem_check_execbuffer(&exec2);
3441 /* Copy in the exec list from userland */
3442 exec_list = kvmalloc_array(count, sizeof(*exec_list),
3443 __GFP_NOWARN | GFP_KERNEL);
3445 /* Allocate extra slots for use by the command parser */
3446 exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3447 __GFP_NOWARN | GFP_KERNEL);
3448 if (exec_list == NULL || exec2_list == NULL) {
3450 "Failed to allocate exec list for %d buffers\n",
3451 args->buffer_count);
3456 err = copy_from_user(exec_list,
3457 u64_to_user_ptr(args->buffers_ptr),
3458 sizeof(*exec_list) * count);
3460 drm_dbg(&i915->drm, "copy %d exec entries failed %d\n",
3461 args->buffer_count, err);
3467 for (i = 0; i < args->buffer_count; i++) {
3468 exec2_list[i].handle = exec_list[i].handle;
3469 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3470 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3471 exec2_list[i].alignment = exec_list[i].alignment;
3472 exec2_list[i].offset = exec_list[i].offset;
3473 if (INTEL_GEN(to_i915(dev)) < 4)
3474 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3476 exec2_list[i].flags = 0;
3479 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list);
3480 if (exec2.flags & __EXEC_HAS_RELOC) {
3481 struct drm_i915_gem_exec_object __user *user_exec_list =
3482 u64_to_user_ptr(args->buffers_ptr);
3484 /* Copy the new buffer offsets back to the user's exec list. */
3485 for (i = 0; i < args->buffer_count; i++) {
3486 if (!(exec2_list[i].offset & UPDATE))
3489 exec2_list[i].offset =
3490 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3491 exec2_list[i].offset &= PIN_OFFSET_MASK;
3492 if (__copy_to_user(&user_exec_list[i].offset,
3493 &exec2_list[i].offset,
3494 sizeof(user_exec_list[i].offset)))
3505 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
3506 struct drm_file *file)
3508 struct drm_i915_private *i915 = to_i915(dev);
3509 struct drm_i915_gem_execbuffer2 *args = data;
3510 struct drm_i915_gem_exec_object2 *exec2_list;
3511 const size_t count = args->buffer_count;
3514 if (!check_buffer_count(count)) {
3515 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3519 err = i915_gem_check_execbuffer(args);
3523 /* Allocate extra slots for use by the command parser */
3524 exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3525 __GFP_NOWARN | GFP_KERNEL);
3526 if (exec2_list == NULL) {
3527 drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n",
3531 if (copy_from_user(exec2_list,
3532 u64_to_user_ptr(args->buffers_ptr),
3533 sizeof(*exec2_list) * count)) {
3534 drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count);
3539 err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
3542 * Now that we have begun execution of the batchbuffer, we ignore
3543 * any new error after this point. Also given that we have already
3544 * updated the associated relocations, we try to write out the current
3545 * object locations irrespective of any error.
3547 if (args->flags & __EXEC_HAS_RELOC) {
3548 struct drm_i915_gem_exec_object2 __user *user_exec_list =
3549 u64_to_user_ptr(args->buffers_ptr);
3552 /* Copy the new buffer offsets back to the user's exec list. */
3554 * Note: count * sizeof(*user_exec_list) does not overflow,
3555 * because we checked 'count' in check_buffer_count().
3557 * And this range already got effectively checked earlier
3558 * when we did the "copy_from_user()" above.
3560 if (!user_write_access_begin(user_exec_list,
3561 count * sizeof(*user_exec_list)))
3564 for (i = 0; i < args->buffer_count; i++) {
3565 if (!(exec2_list[i].offset & UPDATE))
3568 exec2_list[i].offset =
3569 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3570 unsafe_put_user(exec2_list[i].offset,
3571 &user_exec_list[i].offset,
3575 user_write_access_end();
3579 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
3584 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3585 #include "selftests/i915_gem_execbuffer.c"