2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008,2010 Intel Corporation
7 #include <linux/intel-iommu.h>
8 #include <linux/dma-resv.h>
9 #include <linux/sync_file.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_syncobj.h>
14 #include "display/intel_frontbuffer.h"
16 #include "gem/i915_gem_ioctls.h"
17 #include "gt/intel_context.h"
18 #include "gt/intel_gt.h"
19 #include "gt/intel_gt_buffer_pool.h"
20 #include "gt/intel_gt_pm.h"
21 #include "gt/intel_ring.h"
24 #include "i915_gem_clflush.h"
25 #include "i915_gem_context.h"
26 #include "i915_gem_ioctls.h"
27 #include "i915_sw_fence_work.h"
28 #include "i915_trace.h"
29 #include "i915_user_extensions.h"
35 /** This vma's place in the execbuf reservation list */
36 struct drm_i915_gem_exec_object2 *exec;
37 struct list_head bind_link;
38 struct list_head reloc_link;
40 struct hlist_node node;
48 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
51 #define __EXEC_OBJECT_HAS_PIN BIT(31)
52 #define __EXEC_OBJECT_HAS_FENCE BIT(30)
53 #define __EXEC_OBJECT_NEEDS_MAP BIT(29)
54 #define __EXEC_OBJECT_NEEDS_BIAS BIT(28)
55 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */
56 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
58 #define __EXEC_HAS_RELOC BIT(31)
59 #define __EXEC_ENGINE_PINNED BIT(30)
60 #define __EXEC_INTERNAL_FLAGS (~0u << 30)
61 #define UPDATE PIN_OFFSET_FIXED
63 #define BATCH_OFFSET_BIAS (256*1024)
65 #define __I915_EXEC_ILLEGAL_FLAGS \
66 (__I915_EXEC_UNKNOWN_FLAGS | \
67 I915_EXEC_CONSTANTS_MASK | \
68 I915_EXEC_RESOURCE_STREAMER)
70 /* Catch emission of unexpected errors for CI! */
71 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
74 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
80 * DOC: User command execution
82 * Userspace submits commands to be executed on the GPU as an instruction
83 * stream within a GEM object we call a batchbuffer. This instructions may
84 * refer to other GEM objects containing auxiliary state such as kernels,
85 * samplers, render targets and even secondary batchbuffers. Userspace does
86 * not know where in the GPU memory these objects reside and so before the
87 * batchbuffer is passed to the GPU for execution, those addresses in the
88 * batchbuffer and auxiliary objects are updated. This is known as relocation,
89 * or patching. To try and avoid having to relocate each object on the next
90 * execution, userspace is told the location of those objects in this pass,
91 * but this remains just a hint as the kernel may choose a new location for
92 * any object in the future.
94 * At the level of talking to the hardware, submitting a batchbuffer for the
95 * GPU to execute is to add content to a buffer from which the HW
96 * command streamer is reading.
98 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
99 * Execlists, this command is not placed on the same buffer as the
102 * 2. Add a command to invalidate caches to the buffer.
104 * 3. Add a batchbuffer start command to the buffer; the start command is
105 * essentially a token together with the GPU address of the batchbuffer
108 * 4. Add a pipeline flush to the buffer.
110 * 5. Add a memory write command to the buffer to record when the GPU
111 * is done executing the batchbuffer. The memory write writes the
112 * global sequence number of the request, ``i915_request::global_seqno``;
113 * the i915 driver uses the current value in the register to determine
114 * if the GPU has completed the batchbuffer.
116 * 6. Add a user interrupt command to the buffer. This command instructs
117 * the GPU to issue an interrupt when the command, pipeline flush and
118 * memory write are completed.
120 * 7. Inform the hardware of the additional commands added to the buffer
121 * (by updating the tail pointer).
123 * Processing an execbuf ioctl is conceptually split up into a few phases.
125 * 1. Validation - Ensure all the pointers, handles and flags are valid.
126 * 2. Reservation - Assign GPU address space for every object
127 * 3. Relocation - Update any addresses to point to the final locations
128 * 4. Serialisation - Order the request with respect to its dependencies
129 * 5. Construction - Construct a request to execute the batchbuffer
130 * 6. Submission (at some point in the future execution)
132 * Reserving resources for the execbuf is the most complicated phase. We
133 * neither want to have to migrate the object in the address space, nor do
134 * we want to have to update any relocations pointing to this object. Ideally,
135 * we want to leave the object where it is and for all the existing relocations
136 * to match. If the object is given a new address, or if userspace thinks the
137 * object is elsewhere, we have to parse all the relocation entries and update
138 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
139 * all the target addresses in all of its objects match the value in the
140 * relocation entries and that they all match the presumed offsets given by the
141 * list of execbuffer objects. Using this knowledge, we know that if we haven't
142 * moved any buffers, all the relocation entries are valid and we can skip
143 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
144 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
146 * The addresses written in the objects must match the corresponding
147 * reloc.presumed_offset which in turn must match the corresponding
150 * Any render targets written to in the batch must be flagged with
153 * To avoid stalling, execobject.offset should match the current
154 * address of that object within the active context.
156 * The reservation is done is multiple phases. First we try and keep any
157 * object already bound in its current location - so as long as meets the
158 * constraints imposed by the new execbuffer. Any object left unbound after the
159 * first pass is then fitted into any available idle space. If an object does
160 * not fit, all objects are removed from the reservation and the process rerun
161 * after sorting the objects into a priority order (more difficult to fit
162 * objects are tried first). Failing that, the entire VM is cleared and we try
163 * to fit the execbuf once last time before concluding that it simply will not
166 * A small complication to all of this is that we allow userspace not only to
167 * specify an alignment and a size for the object in the address space, but
168 * we also allow userspace to specify the exact offset. This objects are
169 * simpler to place (the location is known a priori) all we have to do is make
170 * sure the space is available.
172 * Once all the objects are in place, patching up the buried pointers to point
173 * to the final locations is a fairly simple job of walking over the relocation
174 * entry arrays, looking up the right address and rewriting the value into
175 * the object. Simple! ... The relocation entries are stored in user memory
176 * and so to access them we have to copy them into a local buffer. That copy
177 * has to avoid taking any pagefaults as they may lead back to a GEM object
178 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
179 * the relocation into multiple passes. First we try to do everything within an
180 * atomic context (avoid the pagefaults) which requires that we never wait. If
181 * we detect that we may wait, or if we need to fault, then we have to fallback
182 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
183 * bells yet?) Dropping the mutex means that we lose all the state we have
184 * built up so far for the execbuf and we must reset any global data. However,
185 * we do leave the objects pinned in their final locations - which is a
186 * potential issue for concurrent execbufs. Once we have left the mutex, we can
187 * allocate and copy all the relocation entries into a large array at our
188 * leisure, reacquire the mutex, reclaim all the objects and other state and
189 * then proceed to update any incorrect addresses with the objects.
191 * As we process the relocation entries, we maintain a record of whether the
192 * object is being written to. Using NORELOC, we expect userspace to provide
193 * this information instead. We also check whether we can skip the relocation
194 * by comparing the expected value inside the relocation entry with the target's
195 * final address. If they differ, we have to map the current object and rewrite
196 * the 4 or 8 byte pointer within.
198 * Serialising an execbuf is quite simple according to the rules of the GEM
199 * ABI. Execution within each context is ordered by the order of submission.
200 * Writes to any GEM object are in order of submission and are exclusive. Reads
201 * from a GEM object are unordered with respect to other reads, but ordered by
202 * writes. A write submitted after a read cannot occur before the read, and
203 * similarly any read submitted after a write cannot occur before the write.
204 * Writes are ordered between engines such that only one write occurs at any
205 * time (completing any reads beforehand) - using semaphores where available
206 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
207 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
208 * reads before starting, and any read (either using set-domain or pread) must
209 * flush all GPU writes before starting. (Note we only employ a barrier before,
210 * we currently rely on userspace not concurrently starting a new execution
211 * whilst reading or writing to an object. This may be an advantage or not
212 * depending on how much you trust userspace not to shoot themselves in the
213 * foot.) Serialisation may just result in the request being inserted into
214 * a DAG awaiting its turn, but most simple is to wait on the CPU until
215 * all dependencies are resolved.
217 * After all of that, is just a matter of closing the request and handing it to
218 * the hardware (well, leaving it in a queue to be executed). However, we also
219 * offer the ability for batchbuffers to be run with elevated privileges so
220 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
221 * Before any batch is given extra privileges we first must check that it
222 * contains no nefarious instructions, we check that each instruction is from
223 * our whitelist and all registers are also from an allowed list. We first
224 * copy the user's batchbuffer to a shadow (so that the user doesn't have
225 * access to it, either by the CPU or GPU as we scan it) and then parse each
226 * instruction. If everything is ok, we set a flag telling the hardware to run
227 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
231 struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
232 struct dma_fence *dma_fence;
234 struct dma_fence_chain *chain_fence;
237 struct i915_execbuffer {
238 struct drm_i915_private *i915; /** i915 backpointer */
239 struct drm_file *file; /** per-file lookup tables and limits */
240 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
241 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
244 struct intel_engine_cs *engine; /** engine to queue the request to */
245 struct intel_context *context; /* logical state for the request */
246 struct i915_gem_context *gem_context; /** caller's context */
248 struct i915_request *request; /** our request to build */
249 struct eb_vma *batch; /** identity of the batch obj/vma */
250 struct i915_vma *trampoline; /** trampoline used for chaining */
252 /** actual size of execobj[] as we may extend it for the cmdparser */
253 unsigned int buffer_count;
255 /** list of vma not yet bound during reservation phase */
256 struct list_head unbound;
258 /** list of vma that have execobj.relocation_count */
259 struct list_head relocs;
261 struct i915_gem_ww_ctx ww;
264 * Track the most recently used object for relocations, as we
265 * frequently have to perform multiple relocations within the same
269 struct drm_mm_node node; /** temporary GTT binding */
270 unsigned long vaddr; /** Current kmap address */
271 unsigned long page; /** Currently mapped page index */
272 unsigned int gen; /** Cached value of INTEL_GEN */
273 bool use_64bit_reloc : 1;
276 bool needs_unfenced : 1;
278 struct i915_request *rq;
280 unsigned int rq_size;
281 struct intel_gt_buffer_pool_node *pool;
284 struct intel_gt_buffer_pool_node *reloc_pool; /** relocation pool for -EDEADLK handling */
285 struct intel_context *reloc_context;
287 u64 invalid_flags; /** Set of execobj.flags that are invalid */
288 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
290 u64 batch_len; /** Length of batch within object */
291 u32 batch_start_offset; /** Location within object of batch */
292 u32 batch_flags; /** Flags composed for emit_bb_start() */
293 struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */
296 * Indicate either the size of the hastable used to resolve
297 * relocation handles, or if negative that we are using a direct
298 * index into the execobj[].
301 struct hlist_head *buckets; /** ht for relocation handles */
303 struct eb_fence *fences;
304 unsigned long num_fences;
307 static int eb_parse(struct i915_execbuffer *eb);
308 static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb,
310 static void eb_unpin_engine(struct i915_execbuffer *eb);
312 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
314 return intel_engine_requires_cmd_parser(eb->engine) ||
315 (intel_engine_using_cmd_parser(eb->engine) &&
316 eb->args->batch_len);
319 static int eb_create(struct i915_execbuffer *eb)
321 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
322 unsigned int size = 1 + ilog2(eb->buffer_count);
325 * Without a 1:1 association between relocation handles and
326 * the execobject[] index, we instead create a hashtable.
327 * We size it dynamically based on available memory, starting
328 * first with 1:1 assocative hash and scaling back until
329 * the allocation succeeds.
331 * Later on we use a positive lut_size to indicate we are
332 * using this hashtable, and a negative value to indicate a
338 /* While we can still reduce the allocation size, don't
339 * raise a warning and allow the allocation to fail.
340 * On the last pass though, we want to try as hard
341 * as possible to perform the allocation and warn
346 flags |= __GFP_NORETRY | __GFP_NOWARN;
348 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
359 eb->lut_size = -eb->buffer_count;
366 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
367 const struct i915_vma *vma,
370 if (vma->node.size < entry->pad_to_size)
373 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
376 if (flags & EXEC_OBJECT_PINNED &&
377 vma->node.start != entry->offset)
380 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
381 vma->node.start < BATCH_OFFSET_BIAS)
384 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
385 (vma->node.start + vma->node.size - 1) >> 32)
388 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
389 !i915_vma_is_map_and_fenceable(vma))
395 static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,
396 unsigned int exec_flags)
400 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
401 pin_flags |= PIN_GLOBAL;
404 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
405 * limit address to the first 4GBs for unflagged objects.
407 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
408 pin_flags |= PIN_ZONE_4G;
410 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
411 pin_flags |= PIN_MAPPABLE;
413 if (exec_flags & EXEC_OBJECT_PINNED)
414 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
415 else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS)
416 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
422 eb_pin_vma(struct i915_execbuffer *eb,
423 const struct drm_i915_gem_exec_object2 *entry,
426 struct i915_vma *vma = ev->vma;
430 pin_flags = vma->node.start;
432 pin_flags = entry->offset & PIN_OFFSET_MASK;
434 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
435 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
436 pin_flags |= PIN_GLOBAL;
438 /* Attempt to reuse the current location if available */
439 /* TODO: Add -EDEADLK handling here */
440 if (unlikely(i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags))) {
441 if (entry->flags & EXEC_OBJECT_PINNED)
444 /* Failing that pick any _free_ space if suitable */
445 if (unlikely(i915_vma_pin_ww(vma, &eb->ww,
448 eb_pin_flags(entry, ev->flags) |
449 PIN_USER | PIN_NOEVICT)))
453 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
454 if (unlikely(i915_vma_pin_fence(vma))) {
460 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
463 ev->flags |= __EXEC_OBJECT_HAS_PIN;
464 return !eb_vma_misplaced(entry, vma, ev->flags);
468 eb_unreserve_vma(struct eb_vma *ev)
470 if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
473 if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
474 __i915_vma_unpin_fence(ev->vma);
476 __i915_vma_unpin(ev->vma);
477 ev->flags &= ~__EXEC_OBJECT_RESERVED;
481 eb_validate_vma(struct i915_execbuffer *eb,
482 struct drm_i915_gem_exec_object2 *entry,
483 struct i915_vma *vma)
485 if (unlikely(entry->flags & eb->invalid_flags))
488 if (unlikely(entry->alignment &&
489 !is_power_of_2_u64(entry->alignment)))
493 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
494 * any non-page-aligned or non-canonical addresses.
496 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
497 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
500 /* pad_to_size was once a reserved field, so sanitize it */
501 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
502 if (unlikely(offset_in_page(entry->pad_to_size)))
505 entry->pad_to_size = 0;
508 * From drm_mm perspective address space is continuous,
509 * so from this point we're always using non-canonical
512 entry->offset = gen8_noncanonical_addr(entry->offset);
514 if (!eb->reloc_cache.has_fence) {
515 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
517 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
518 eb->reloc_cache.needs_unfenced) &&
519 i915_gem_object_is_tiled(vma->obj))
520 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
523 if (!(entry->flags & EXEC_OBJECT_PINNED))
524 entry->flags |= eb->context_flags;
530 eb_add_vma(struct i915_execbuffer *eb,
531 unsigned int i, unsigned batch_idx,
532 struct i915_vma *vma)
534 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
535 struct eb_vma *ev = &eb->vma[i];
537 GEM_BUG_ON(i915_vma_is_closed(vma));
541 ev->flags = entry->flags;
543 if (eb->lut_size > 0) {
544 ev->handle = entry->handle;
545 hlist_add_head(&ev->node,
546 &eb->buckets[hash_32(entry->handle,
550 if (entry->relocation_count)
551 list_add_tail(&ev->reloc_link, &eb->relocs);
554 * SNA is doing fancy tricks with compressing batch buffers, which leads
555 * to negative relocation deltas. Usually that works out ok since the
556 * relocate address is still positive, except when the batch is placed
557 * very low in the GTT. Ensure this doesn't happen.
559 * Note that actual hangs have only been observed on gen7, but for
560 * paranoia do it everywhere.
562 if (i == batch_idx) {
563 if (entry->relocation_count &&
564 !(ev->flags & EXEC_OBJECT_PINNED))
565 ev->flags |= __EXEC_OBJECT_NEEDS_BIAS;
566 if (eb->reloc_cache.has_fence)
567 ev->flags |= EXEC_OBJECT_NEEDS_FENCE;
573 static inline int use_cpu_reloc(const struct reloc_cache *cache,
574 const struct drm_i915_gem_object *obj)
576 if (!i915_gem_object_has_struct_page(obj))
579 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
582 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
585 return (cache->has_llc ||
587 obj->cache_level != I915_CACHE_NONE);
590 static int eb_reserve_vma(struct i915_execbuffer *eb,
594 struct drm_i915_gem_exec_object2 *entry = ev->exec;
595 struct i915_vma *vma = ev->vma;
598 if (drm_mm_node_allocated(&vma->node) &&
599 eb_vma_misplaced(entry, vma, ev->flags)) {
600 err = i915_vma_unbind(vma);
605 err = i915_vma_pin_ww(vma, &eb->ww,
606 entry->pad_to_size, entry->alignment,
607 eb_pin_flags(entry, ev->flags) | pin_flags);
611 if (entry->offset != vma->node.start) {
612 entry->offset = vma->node.start | UPDATE;
613 eb->args->flags |= __EXEC_HAS_RELOC;
616 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
617 err = i915_vma_pin_fence(vma);
624 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
627 ev->flags |= __EXEC_OBJECT_HAS_PIN;
628 GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags));
633 static int eb_reserve(struct i915_execbuffer *eb)
635 const unsigned int count = eb->buffer_count;
636 unsigned int pin_flags = PIN_USER | PIN_NONBLOCK;
637 struct list_head last;
639 unsigned int i, pass;
643 * Attempt to pin all of the buffers into the GTT.
644 * This is done in 3 phases:
646 * 1a. Unbind all objects that do not match the GTT constraints for
647 * the execbuffer (fenceable, mappable, alignment etc).
648 * 1b. Increment pin count for already bound objects.
649 * 2. Bind new objects.
650 * 3. Decrement pin count.
652 * This avoid unnecessary unbinding of later objects in order to make
653 * room for the earlier objects *unless* we need to defragment.
657 list_for_each_entry(ev, &eb->unbound, bind_link) {
658 err = eb_reserve_vma(eb, ev, pin_flags);
665 /* Resort *all* the objects into priority order */
666 INIT_LIST_HEAD(&eb->unbound);
667 INIT_LIST_HEAD(&last);
668 for (i = 0; i < count; i++) {
673 if (flags & EXEC_OBJECT_PINNED &&
674 flags & __EXEC_OBJECT_HAS_PIN)
677 eb_unreserve_vma(ev);
679 if (flags & EXEC_OBJECT_PINNED)
680 /* Pinned must have their slot */
681 list_add(&ev->bind_link, &eb->unbound);
682 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
683 /* Map require the lowest 256MiB (aperture) */
684 list_add_tail(&ev->bind_link, &eb->unbound);
685 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
686 /* Prioritise 4GiB region for restricted bo */
687 list_add(&ev->bind_link, &last);
689 list_add_tail(&ev->bind_link, &last);
691 list_splice_tail(&last, &eb->unbound);
698 /* Too fragmented, unbind everything and retry */
699 mutex_lock(&eb->context->vm->mutex);
700 err = i915_gem_evict_vm(eb->context->vm);
701 mutex_unlock(&eb->context->vm->mutex);
710 pin_flags = PIN_USER;
714 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
716 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
719 return eb->buffer_count - 1;
722 static int eb_select_context(struct i915_execbuffer *eb)
724 struct i915_gem_context *ctx;
726 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
730 eb->gem_context = ctx;
731 if (rcu_access_pointer(ctx->vm))
732 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
734 eb->context_flags = 0;
735 if (test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags))
736 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
741 static int __eb_add_lut(struct i915_execbuffer *eb,
742 u32 handle, struct i915_vma *vma)
744 struct i915_gem_context *ctx = eb->gem_context;
745 struct i915_lut_handle *lut;
748 lut = i915_lut_handle_alloc();
753 if (!atomic_fetch_inc(&vma->open_count))
754 i915_vma_reopen(vma);
755 lut->handle = handle;
758 /* Check that the context hasn't been closed in the meantime */
760 if (!mutex_lock_interruptible(&ctx->lut_mutex)) {
761 struct i915_address_space *vm = rcu_access_pointer(ctx->vm);
763 if (unlikely(vm && vma->vm != vm))
764 err = -EAGAIN; /* user racing with ctx set-vm */
765 else if (likely(!i915_gem_context_is_closed(ctx)))
766 err = radix_tree_insert(&ctx->handles_vma, handle, vma);
769 if (err == 0) { /* And nor has this handle */
770 struct drm_i915_gem_object *obj = vma->obj;
772 spin_lock(&obj->lut_lock);
773 if (idr_find(&eb->file->object_idr, handle) == obj) {
774 list_add(&lut->obj_link, &obj->lut_list);
776 radix_tree_delete(&ctx->handles_vma, handle);
779 spin_unlock(&obj->lut_lock);
781 mutex_unlock(&ctx->lut_mutex);
791 i915_lut_handle_free(lut);
795 static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
797 struct i915_address_space *vm = eb->context->vm;
800 struct drm_i915_gem_object *obj;
801 struct i915_vma *vma;
805 vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
806 if (likely(vma && vma->vm == vm))
807 vma = i915_vma_tryget(vma);
812 obj = i915_gem_object_lookup(eb->file, handle);
814 return ERR_PTR(-ENOENT);
816 vma = i915_vma_instance(obj, vm, NULL);
818 i915_gem_object_put(obj);
822 err = __eb_add_lut(eb, handle, vma);
826 i915_gem_object_put(obj);
832 static int eb_lookup_vmas(struct i915_execbuffer *eb)
834 struct drm_i915_private *i915 = eb->i915;
835 unsigned int batch = eb_batch_index(eb);
839 INIT_LIST_HEAD(&eb->relocs);
841 for (i = 0; i < eb->buffer_count; i++) {
842 struct i915_vma *vma;
844 vma = eb_lookup_vma(eb, eb->exec[i].handle);
850 err = eb_validate_vma(eb, &eb->exec[i], vma);
856 eb_add_vma(eb, i, batch, vma);
859 if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) {
861 "Attempting to use self-modifying batch buffer\n");
865 if (range_overflows_t(u64,
866 eb->batch_start_offset, eb->batch_len,
867 eb->batch->vma->size)) {
868 drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
872 if (eb->batch_len == 0)
873 eb->batch_len = eb->batch->vma->size - eb->batch_start_offset;
874 if (unlikely(eb->batch_len == 0)) { /* impossible! */
875 drm_dbg(&i915->drm, "Invalid batch length\n");
882 eb->vma[i].vma = NULL;
886 static int eb_validate_vmas(struct i915_execbuffer *eb)
891 INIT_LIST_HEAD(&eb->unbound);
893 for (i = 0; i < eb->buffer_count; i++) {
894 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
895 struct eb_vma *ev = &eb->vma[i];
896 struct i915_vma *vma = ev->vma;
898 err = i915_gem_object_lock(vma->obj, &eb->ww);
902 if (eb_pin_vma(eb, entry, ev)) {
903 if (entry->offset != vma->node.start) {
904 entry->offset = vma->node.start | UPDATE;
905 eb->args->flags |= __EXEC_HAS_RELOC;
908 eb_unreserve_vma(ev);
910 list_add_tail(&ev->bind_link, &eb->unbound);
911 if (drm_mm_node_allocated(&vma->node)) {
912 err = i915_vma_unbind(vma);
918 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
919 eb_vma_misplaced(&eb->exec[i], vma, ev->flags));
922 if (!list_empty(&eb->unbound))
923 return eb_reserve(eb);
928 static struct eb_vma *
929 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
931 if (eb->lut_size < 0) {
932 if (handle >= -eb->lut_size)
934 return &eb->vma[handle];
936 struct hlist_head *head;
939 head = &eb->buckets[hash_32(handle, eb->lut_size)];
940 hlist_for_each_entry(ev, head, node) {
941 if (ev->handle == handle)
948 static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
950 const unsigned int count = eb->buffer_count;
953 for (i = 0; i < count; i++) {
954 struct eb_vma *ev = &eb->vma[i];
955 struct i915_vma *vma = ev->vma;
960 eb_unreserve_vma(ev);
969 static void eb_destroy(const struct i915_execbuffer *eb)
971 GEM_BUG_ON(eb->reloc_cache.rq);
973 if (eb->lut_size > 0)
978 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
979 const struct i915_vma *target)
981 return gen8_canonical_addr((int)reloc->delta + target->node.start);
984 static void reloc_cache_clear(struct reloc_cache *cache)
987 cache->rq_cmd = NULL;
992 static void reloc_cache_init(struct reloc_cache *cache,
993 struct drm_i915_private *i915)
997 /* Must be a variable in the struct to allow GCC to unroll. */
998 cache->gen = INTEL_GEN(i915);
999 cache->has_llc = HAS_LLC(i915);
1000 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
1001 cache->has_fence = cache->gen < 4;
1002 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
1003 cache->node.flags = 0;
1004 reloc_cache_clear(cache);
1007 static inline void *unmask_page(unsigned long p)
1009 return (void *)(uintptr_t)(p & PAGE_MASK);
1012 static inline unsigned int unmask_flags(unsigned long p)
1014 return p & ~PAGE_MASK;
1017 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
1019 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
1021 struct drm_i915_private *i915 =
1022 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
1026 static void reloc_cache_put_pool(struct i915_execbuffer *eb, struct reloc_cache *cache)
1032 * This is a bit nasty, normally we keep objects locked until the end
1033 * of execbuffer, but we already submit this, and have to unlock before
1034 * dropping the reference. Fortunately we can only hold 1 pool node at
1035 * a time, so this should be harmless.
1037 i915_gem_ww_unlock_single(cache->pool->obj);
1038 intel_gt_buffer_pool_put(cache->pool);
1042 static void reloc_gpu_flush(struct i915_execbuffer *eb, struct reloc_cache *cache)
1044 struct drm_i915_gem_object *obj = cache->rq->batch->obj;
1046 GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32));
1047 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
1049 __i915_gem_object_flush_map(obj, 0, sizeof(u32) * (cache->rq_size + 1));
1050 i915_gem_object_unpin_map(obj);
1052 intel_gt_chipset_flush(cache->rq->engine->gt);
1054 i915_request_add(cache->rq);
1055 reloc_cache_put_pool(eb, cache);
1056 reloc_cache_clear(cache);
1058 eb->reloc_pool = NULL;
1061 static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
1066 reloc_gpu_flush(eb, cache);
1071 vaddr = unmask_page(cache->vaddr);
1072 if (cache->vaddr & KMAP) {
1073 struct drm_i915_gem_object *obj =
1074 (struct drm_i915_gem_object *)cache->node.mm;
1075 if (cache->vaddr & CLFLUSH_AFTER)
1078 kunmap_atomic(vaddr);
1079 i915_gem_object_finish_access(obj);
1081 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1083 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1084 io_mapping_unmap_atomic((void __iomem *)vaddr);
1086 if (drm_mm_node_allocated(&cache->node)) {
1087 ggtt->vm.clear_range(&ggtt->vm,
1090 mutex_lock(&ggtt->vm.mutex);
1091 drm_mm_remove_node(&cache->node);
1092 mutex_unlock(&ggtt->vm.mutex);
1094 i915_vma_unpin((struct i915_vma *)cache->node.mm);
1102 static void *reloc_kmap(struct drm_i915_gem_object *obj,
1103 struct reloc_cache *cache,
1104 unsigned long pageno)
1110 kunmap_atomic(unmask_page(cache->vaddr));
1112 unsigned int flushes;
1115 err = i915_gem_object_prepare_write(obj, &flushes);
1117 return ERR_PTR(err);
1119 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1120 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1122 cache->vaddr = flushes | KMAP;
1123 cache->node.mm = (void *)obj;
1128 page = i915_gem_object_get_page(obj, pageno);
1130 set_page_dirty(page);
1132 vaddr = kmap_atomic(page);
1133 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1134 cache->page = pageno;
1139 static void *reloc_iomap(struct drm_i915_gem_object *obj,
1140 struct i915_execbuffer *eb,
1143 struct reloc_cache *cache = &eb->reloc_cache;
1144 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1145 unsigned long offset;
1149 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1150 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1152 struct i915_vma *vma;
1155 if (i915_gem_object_is_tiled(obj))
1156 return ERR_PTR(-EINVAL);
1158 if (use_cpu_reloc(cache, obj))
1161 err = i915_gem_object_set_to_gtt_domain(obj, true);
1163 return ERR_PTR(err);
1165 vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0,
1167 PIN_NONBLOCK /* NOWARN */ |
1169 if (vma == ERR_PTR(-EDEADLK))
1173 memset(&cache->node, 0, sizeof(cache->node));
1174 mutex_lock(&ggtt->vm.mutex);
1175 err = drm_mm_insert_node_in_range
1176 (&ggtt->vm.mm, &cache->node,
1177 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1178 0, ggtt->mappable_end,
1180 mutex_unlock(&ggtt->vm.mutex);
1181 if (err) /* no inactive aperture space, use cpu reloc */
1184 cache->node.start = vma->node.start;
1185 cache->node.mm = (void *)vma;
1189 offset = cache->node.start;
1190 if (drm_mm_node_allocated(&cache->node)) {
1191 ggtt->vm.insert_page(&ggtt->vm,
1192 i915_gem_object_get_dma_address(obj, page),
1193 offset, I915_CACHE_NONE, 0);
1195 offset += page << PAGE_SHIFT;
1198 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1201 cache->vaddr = (unsigned long)vaddr;
1206 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1207 struct i915_execbuffer *eb,
1210 struct reloc_cache *cache = &eb->reloc_cache;
1213 if (cache->page == page) {
1214 vaddr = unmask_page(cache->vaddr);
1217 if ((cache->vaddr & KMAP) == 0)
1218 vaddr = reloc_iomap(obj, eb, page);
1220 vaddr = reloc_kmap(obj, cache, page);
1226 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1228 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1229 if (flushes & CLFLUSH_BEFORE) {
1237 * Writes to the same cacheline are serialised by the CPU
1238 * (including clflush). On the write path, we only require
1239 * that it hits memory in an orderly fashion and place
1240 * mb barriers at the start and end of the relocation phase
1241 * to ensure ordering of clflush wrt to the system.
1243 if (flushes & CLFLUSH_AFTER)
1249 static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma)
1251 struct drm_i915_gem_object *obj = vma->obj;
1254 assert_vma_held(vma);
1256 if (obj->cache_dirty & ~obj->cache_coherent)
1257 i915_gem_clflush_object(obj, 0);
1258 obj->write_domain = 0;
1260 err = i915_request_await_object(rq, vma->obj, true);
1262 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1267 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1268 struct intel_engine_cs *engine,
1269 struct i915_vma *vma,
1272 struct reloc_cache *cache = &eb->reloc_cache;
1273 struct intel_gt_buffer_pool_node *pool = eb->reloc_pool;
1274 struct i915_request *rq;
1275 struct i915_vma *batch;
1280 pool = intel_gt_get_buffer_pool(engine->gt, PAGE_SIZE);
1282 return PTR_ERR(pool);
1284 eb->reloc_pool = NULL;
1286 err = i915_gem_object_lock(pool->obj, &eb->ww);
1290 cmd = i915_gem_object_pin_map(pool->obj,
1299 batch = i915_vma_instance(pool->obj, vma->vm, NULL);
1300 if (IS_ERR(batch)) {
1301 err = PTR_ERR(batch);
1305 err = i915_vma_pin_ww(batch, &eb->ww, 0, 0, PIN_USER | PIN_NONBLOCK);
1309 if (engine == eb->context->engine) {
1310 rq = i915_request_create(eb->context);
1312 struct intel_context *ce = eb->reloc_context;
1315 ce = intel_context_create(engine);
1321 i915_vm_put(ce->vm);
1322 ce->vm = i915_vm_get(eb->context->vm);
1323 eb->reloc_context = ce;
1326 err = intel_context_pin_ww(ce, &eb->ww);
1330 rq = i915_request_create(ce);
1331 intel_context_unpin(ce);
1338 err = intel_gt_buffer_pool_mark_active(pool, rq);
1342 err = reloc_move_to_gpu(rq, vma);
1346 err = eb->engine->emit_bb_start(rq,
1347 batch->node.start, PAGE_SIZE,
1348 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1352 assert_vma_held(batch);
1353 err = i915_request_await_object(rq, batch->obj, false);
1355 err = i915_vma_move_to_active(batch, rq, 0);
1360 i915_vma_unpin(batch);
1363 cache->rq_cmd = cmd;
1367 /* Return with batch mapping (cmd) still pinned */
1371 i915_request_set_error_once(rq, err);
1373 i915_request_add(rq);
1375 i915_vma_unpin(batch);
1377 i915_gem_object_unpin_map(pool->obj);
1379 eb->reloc_pool = pool;
1383 static bool reloc_can_use_engine(const struct intel_engine_cs *engine)
1385 return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6);
1388 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1389 struct i915_vma *vma,
1392 struct reloc_cache *cache = &eb->reloc_cache;
1395 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1396 reloc_gpu_flush(eb, cache);
1398 if (unlikely(!cache->rq)) {
1400 struct intel_engine_cs *engine = eb->engine;
1402 if (!reloc_can_use_engine(engine)) {
1403 engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0];
1405 return ERR_PTR(-ENODEV);
1408 err = __reloc_gpu_alloc(eb, engine, vma, len);
1410 return ERR_PTR(err);
1413 cmd = cache->rq_cmd + cache->rq_size;
1414 cache->rq_size += len;
1419 static inline bool use_reloc_gpu(struct i915_vma *vma)
1421 if (DBG_FORCE_RELOC == FORCE_GPU_RELOC)
1424 if (DBG_FORCE_RELOC)
1427 return !dma_resv_test_signaled_rcu(vma->resv, true);
1430 static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset)
1435 GEM_BUG_ON(vma->pages != vma->obj->mm.pages);
1437 page = i915_gem_object_get_page(vma->obj, offset >> PAGE_SHIFT);
1438 addr = PFN_PHYS(page_to_pfn(page));
1439 GEM_BUG_ON(overflows_type(addr, u32)); /* expected dma32 */
1441 return addr + offset_in_page(offset);
1444 static int __reloc_entry_gpu(struct i915_execbuffer *eb,
1445 struct i915_vma *vma,
1449 const unsigned int gen = eb->reloc_cache.gen;
1455 len = offset & 7 ? 8 : 5;
1461 batch = reloc_gpu(eb, vma, len);
1462 if (batch == ERR_PTR(-EDEADLK))
1464 else if (IS_ERR(batch))
1467 addr = gen8_canonical_addr(vma->node.start + offset);
1470 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1471 *batch++ = lower_32_bits(addr);
1472 *batch++ = upper_32_bits(addr);
1473 *batch++ = lower_32_bits(target_addr);
1475 addr = gen8_canonical_addr(addr + 4);
1477 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1478 *batch++ = lower_32_bits(addr);
1479 *batch++ = upper_32_bits(addr);
1480 *batch++ = upper_32_bits(target_addr);
1482 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1483 *batch++ = lower_32_bits(addr);
1484 *batch++ = upper_32_bits(addr);
1485 *batch++ = lower_32_bits(target_addr);
1486 *batch++ = upper_32_bits(target_addr);
1488 } else if (gen >= 6) {
1489 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1492 *batch++ = target_addr;
1493 } else if (IS_I965G(eb->i915)) {
1494 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1496 *batch++ = vma_phys_addr(vma, offset);
1497 *batch++ = target_addr;
1498 } else if (gen >= 4) {
1499 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1502 *batch++ = target_addr;
1503 } else if (gen >= 3 &&
1504 !(IS_I915G(eb->i915) || IS_I915GM(eb->i915))) {
1505 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1507 *batch++ = target_addr;
1509 *batch++ = MI_STORE_DWORD_IMM;
1510 *batch++ = vma_phys_addr(vma, offset);
1511 *batch++ = target_addr;
1517 static int reloc_entry_gpu(struct i915_execbuffer *eb,
1518 struct i915_vma *vma,
1522 if (eb->reloc_cache.vaddr)
1525 if (!use_reloc_gpu(vma))
1528 return __reloc_entry_gpu(eb, vma, offset, target_addr);
1532 relocate_entry(struct i915_vma *vma,
1533 const struct drm_i915_gem_relocation_entry *reloc,
1534 struct i915_execbuffer *eb,
1535 const struct i915_vma *target)
1537 u64 target_addr = relocation_target(reloc, target);
1538 u64 offset = reloc->offset;
1539 int reloc_gpu = reloc_entry_gpu(eb, vma, offset, target_addr);
1545 bool wide = eb->reloc_cache.use_64bit_reloc;
1549 vaddr = reloc_vaddr(vma->obj, eb,
1550 offset >> PAGE_SHIFT);
1552 return PTR_ERR(vaddr);
1554 GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32)));
1555 clflush_write32(vaddr + offset_in_page(offset),
1556 lower_32_bits(target_addr),
1557 eb->reloc_cache.vaddr);
1560 offset += sizeof(u32);
1567 return target->node.start | UPDATE;
1571 eb_relocate_entry(struct i915_execbuffer *eb,
1573 const struct drm_i915_gem_relocation_entry *reloc)
1575 struct drm_i915_private *i915 = eb->i915;
1576 struct eb_vma *target;
1579 /* we've already hold a reference to all valid objects */
1580 target = eb_get_vma(eb, reloc->target_handle);
1581 if (unlikely(!target))
1584 /* Validate that the target is in a valid r/w GPU domain */
1585 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1586 drm_dbg(&i915->drm, "reloc with multiple write domains: "
1587 "target %d offset %d "
1588 "read %08x write %08x",
1589 reloc->target_handle,
1590 (int) reloc->offset,
1591 reloc->read_domains,
1592 reloc->write_domain);
1595 if (unlikely((reloc->write_domain | reloc->read_domains)
1596 & ~I915_GEM_GPU_DOMAINS)) {
1597 drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: "
1598 "target %d offset %d "
1599 "read %08x write %08x",
1600 reloc->target_handle,
1601 (int) reloc->offset,
1602 reloc->read_domains,
1603 reloc->write_domain);
1607 if (reloc->write_domain) {
1608 target->flags |= EXEC_OBJECT_WRITE;
1611 * Sandybridge PPGTT errata: We need a global gtt mapping
1612 * for MI and pipe_control writes because the gpu doesn't
1613 * properly redirect them through the ppgtt for non_secure
1616 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1617 IS_GEN(eb->i915, 6)) {
1618 err = i915_vma_bind(target->vma,
1619 target->vma->obj->cache_level,
1627 * If the relocation already has the right value in it, no
1628 * more work needs to be done.
1630 if (!DBG_FORCE_RELOC &&
1631 gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
1634 /* Check that the relocation address is valid... */
1635 if (unlikely(reloc->offset >
1636 ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1637 drm_dbg(&i915->drm, "Relocation beyond object bounds: "
1638 "target %d offset %d size %d.\n",
1639 reloc->target_handle,
1641 (int)ev->vma->size);
1644 if (unlikely(reloc->offset & 3)) {
1645 drm_dbg(&i915->drm, "Relocation not 4-byte aligned: "
1646 "target %d offset %d.\n",
1647 reloc->target_handle,
1648 (int)reloc->offset);
1653 * If we write into the object, we need to force the synchronisation
1654 * barrier, either with an asynchronous clflush or if we executed the
1655 * patching using the GPU (though that should be serialised by the
1656 * timeline). To be completely sure, and since we are required to
1657 * do relocations we are already stalling, disable the user's opt
1658 * out of our synchronisation.
1660 ev->flags &= ~EXEC_OBJECT_ASYNC;
1662 /* and update the user's relocation entry */
1663 return relocate_entry(ev->vma, reloc, eb, target->vma);
1666 static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev)
1668 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1669 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1670 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1671 struct drm_i915_gem_relocation_entry __user *urelocs =
1672 u64_to_user_ptr(entry->relocs_ptr);
1673 unsigned long remain = entry->relocation_count;
1675 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1679 * We must check that the entire relocation array is safe
1680 * to read. However, if the array is not writable the user loses
1681 * the updated relocation values.
1683 if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs))))
1687 struct drm_i915_gem_relocation_entry *r = stack;
1688 unsigned int count =
1689 min_t(unsigned long, remain, ARRAY_SIZE(stack));
1690 unsigned int copied;
1693 * This is the fast path and we cannot handle a pagefault
1694 * whilst holding the struct mutex lest the user pass in the
1695 * relocations contained within a mmaped bo. For in such a case
1696 * we, the page fault handler would call i915_gem_fault() and
1697 * we would try to acquire the struct mutex again. Obviously
1698 * this is bad and so lockdep complains vehemently.
1700 pagefault_disable();
1701 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1703 if (unlikely(copied)) {
1710 u64 offset = eb_relocate_entry(eb, ev, r);
1712 if (likely(offset == 0)) {
1713 } else if ((s64)offset < 0) {
1714 remain = (int)offset;
1718 * Note that reporting an error now
1719 * leaves everything in an inconsistent
1720 * state as we have *already* changed
1721 * the relocation value inside the
1722 * object. As we have not changed the
1723 * reloc.presumed_offset or will not
1724 * change the execobject.offset, on the
1725 * call we may not rewrite the value
1726 * inside the object, leaving it
1727 * dangling and causing a GPU hang. Unless
1728 * userspace dynamically rebuilds the
1729 * relocations on each execbuf rather than
1730 * presume a static tree.
1732 * We did previously check if the relocations
1733 * were writable (access_ok), an error now
1734 * would be a strange race with mprotect,
1735 * having already demonstrated that we
1736 * can read from this userspace address.
1738 offset = gen8_canonical_addr(offset & ~UPDATE);
1740 &urelocs[r - stack].presumed_offset);
1742 } while (r++, --count);
1743 urelocs += ARRAY_SIZE(stack);
1746 reloc_cache_reset(&eb->reloc_cache, eb);
1751 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
1753 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1754 struct drm_i915_gem_relocation_entry *relocs =
1755 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1759 for (i = 0; i < entry->relocation_count; i++) {
1760 u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);
1762 if ((s64)offset < 0) {
1769 reloc_cache_reset(&eb->reloc_cache, eb);
1773 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1775 const char __user *addr, *end;
1777 char __maybe_unused c;
1779 size = entry->relocation_count;
1783 if (size > N_RELOC(ULONG_MAX))
1786 addr = u64_to_user_ptr(entry->relocs_ptr);
1787 size *= sizeof(struct drm_i915_gem_relocation_entry);
1788 if (!access_ok(addr, size))
1792 for (; addr < end; addr += PAGE_SIZE) {
1793 int err = __get_user(c, addr);
1797 return __get_user(c, end - 1);
1800 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1802 struct drm_i915_gem_relocation_entry *relocs;
1803 const unsigned int count = eb->buffer_count;
1807 for (i = 0; i < count; i++) {
1808 const unsigned int nreloc = eb->exec[i].relocation_count;
1809 struct drm_i915_gem_relocation_entry __user *urelocs;
1811 unsigned long copied;
1816 err = check_relocations(&eb->exec[i]);
1820 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1821 size = nreloc * sizeof(*relocs);
1823 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1829 /* copy_from_user is limited to < 4GiB */
1833 min_t(u64, BIT_ULL(31), size - copied);
1835 if (__copy_from_user((char *)relocs + copied,
1836 (char __user *)urelocs + copied,
1841 } while (copied < size);
1844 * As we do not update the known relocation offsets after
1845 * relocating (due to the complexities in lock handling),
1846 * we need to mark them as invalid now so that we force the
1847 * relocation processing next time. Just in case the target
1848 * object is evicted and then rebound into its old
1849 * presumed_offset before the next execbuffer - if that
1850 * happened we would make the mistake of assuming that the
1851 * relocations were valid.
1853 if (!user_access_begin(urelocs, size))
1856 for (copied = 0; copied < nreloc; copied++)
1858 &urelocs[copied].presumed_offset,
1862 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1874 relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1875 if (eb->exec[i].relocation_count)
1881 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1883 const unsigned int count = eb->buffer_count;
1886 for (i = 0; i < count; i++) {
1889 err = check_relocations(&eb->exec[i]);
1897 static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb,
1898 struct i915_request *rq)
1900 bool have_copy = false;
1905 if (signal_pending(current)) {
1910 /* We may process another execbuffer during the unlock... */
1911 eb_release_vmas(eb, false);
1912 i915_gem_ww_ctx_fini(&eb->ww);
1915 /* nonblocking is always false */
1916 if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
1917 MAX_SCHEDULE_TIMEOUT) < 0) {
1918 i915_request_put(rq);
1925 i915_request_put(rq);
1930 * We take 3 passes through the slowpatch.
1932 * 1 - we try to just prefault all the user relocation entries and
1933 * then attempt to reuse the atomic pagefault disabled fast path again.
1935 * 2 - we copy the user entries to a local buffer here outside of the
1936 * local and allow ourselves to wait upon any rendering before
1939 * 3 - we already have a local copy of the relocation entries, but
1940 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1943 err = eb_prefault_relocations(eb);
1944 } else if (!have_copy) {
1945 err = eb_copy_relocations(eb);
1946 have_copy = err == 0;
1953 flush_workqueue(eb->i915->mm.userptr_wq);
1956 i915_gem_ww_ctx_init(&eb->ww, true);
1960 /* reacquire the objects */
1962 rq = eb_pin_engine(eb, false);
1969 /* We didn't throttle, should be NULL */
1972 err = eb_validate_vmas(eb);
1976 GEM_BUG_ON(!eb->batch);
1978 list_for_each_entry(ev, &eb->relocs, reloc_link) {
1980 pagefault_disable();
1981 err = eb_relocate_vma(eb, ev);
1986 err = eb_relocate_vma_slow(eb, ev);
1992 if (err == -EDEADLK)
1995 if (err && !have_copy)
2001 /* as last step, parse the command buffer */
2007 * Leave the user relocations as are, this is the painfully slow path,
2008 * and we want to avoid the complication of dropping the lock whilst
2009 * having buffers reserved in the aperture and so causing spurious
2010 * ENOSPC for random operations.
2014 if (err == -EDEADLK) {
2015 eb_release_vmas(eb, false);
2016 err = i915_gem_ww_ctx_backoff(&eb->ww);
2018 goto repeat_validate;
2026 const unsigned int count = eb->buffer_count;
2029 for (i = 0; i < count; i++) {
2030 const struct drm_i915_gem_exec_object2 *entry =
2032 struct drm_i915_gem_relocation_entry *relocs;
2034 if (!entry->relocation_count)
2037 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
2043 i915_request_put(rq);
2048 static int eb_relocate_parse(struct i915_execbuffer *eb)
2051 struct i915_request *rq = NULL;
2052 bool throttle = true;
2055 rq = eb_pin_engine(eb, throttle);
2059 if (err != -EDEADLK)
2066 bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
2068 /* Need to drop all locks now for throttling, take slowpath */
2069 err = i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, 0);
2070 if (err == -ETIME) {
2073 i915_request_put(rq);
2078 i915_request_put(rq);
2082 /* only throttle once, even if we didn't need to throttle */
2085 err = eb_validate_vmas(eb);
2091 /* The objects are in their final locations, apply the relocations. */
2092 if (eb->args->flags & __EXEC_HAS_RELOC) {
2095 list_for_each_entry(ev, &eb->relocs, reloc_link) {
2096 err = eb_relocate_vma(eb, ev);
2101 if (err == -EDEADLK)
2111 if (err == -EDEADLK) {
2112 eb_release_vmas(eb, false);
2113 err = i915_gem_ww_ctx_backoff(&eb->ww);
2121 err = eb_relocate_parse_slow(eb, rq);
2124 * If the user expects the execobject.offset and
2125 * reloc.presumed_offset to be an exact match,
2126 * as for using NO_RELOC, then we cannot update
2127 * the execobject.offset until we have completed
2130 eb->args->flags &= ~__EXEC_HAS_RELOC;
2135 static int eb_move_to_gpu(struct i915_execbuffer *eb)
2137 const unsigned int count = eb->buffer_count;
2138 unsigned int i = count;
2142 struct eb_vma *ev = &eb->vma[i];
2143 struct i915_vma *vma = ev->vma;
2144 unsigned int flags = ev->flags;
2145 struct drm_i915_gem_object *obj = vma->obj;
2147 assert_vma_held(vma);
2149 if (flags & EXEC_OBJECT_CAPTURE) {
2150 struct i915_capture_list *capture;
2152 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
2154 capture->next = eb->request->capture_list;
2156 eb->request->capture_list = capture;
2161 * If the GPU is not _reading_ through the CPU cache, we need
2162 * to make sure that any writes (both previous GPU writes from
2163 * before a change in snooping levels and normal CPU writes)
2164 * caught in that cache are flushed to main memory.
2167 * obj->cache_dirty &&
2168 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
2169 * but gcc's optimiser doesn't handle that as well and emits
2170 * two jumps instead of one. Maybe one day...
2172 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
2173 if (i915_gem_clflush_object(obj, 0))
2174 flags &= ~EXEC_OBJECT_ASYNC;
2177 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
2178 err = i915_request_await_object
2179 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
2183 err = i915_vma_move_to_active(vma, eb->request, flags);
2189 /* Unconditionally flush any chipset caches (for streaming writes). */
2190 intel_gt_chipset_flush(eb->engine->gt);
2194 i915_request_set_error_once(eb->request, err);
2198 static int i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
2200 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
2203 /* Kernel clipping was a DRI1 misfeature */
2204 if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
2205 I915_EXEC_USE_EXTENSIONS))) {
2206 if (exec->num_cliprects || exec->cliprects_ptr)
2210 if (exec->DR4 == 0xffffffff) {
2211 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
2214 if (exec->DR1 || exec->DR4)
2217 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
2223 static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
2228 if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) {
2229 drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
2233 cs = intel_ring_begin(rq, 4 * 2 + 2);
2237 *cs++ = MI_LOAD_REGISTER_IMM(4);
2238 for (i = 0; i < 4; i++) {
2239 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
2243 intel_ring_advance(rq, cs);
2248 static struct i915_vma *
2249 shadow_batch_pin(struct i915_execbuffer *eb,
2250 struct drm_i915_gem_object *obj,
2251 struct i915_address_space *vm,
2254 struct i915_vma *vma;
2257 vma = i915_vma_instance(obj, vm, NULL);
2261 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags);
2263 return ERR_PTR(err);
2268 struct eb_parse_work {
2269 struct dma_fence_work base;
2270 struct intel_engine_cs *engine;
2271 struct i915_vma *batch;
2272 struct i915_vma *shadow;
2273 struct i915_vma *trampoline;
2274 unsigned long batch_offset;
2275 unsigned long batch_length;
2278 static int __eb_parse(struct dma_fence_work *work)
2280 struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
2282 return intel_engine_cmd_parser(pw->engine,
2290 static void __eb_parse_release(struct dma_fence_work *work)
2292 struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
2295 i915_active_release(&pw->trampoline->active);
2296 i915_active_release(&pw->shadow->active);
2297 i915_active_release(&pw->batch->active);
2300 static const struct dma_fence_work_ops eb_parse_ops = {
2303 .release = __eb_parse_release,
2307 __parser_mark_active(struct i915_vma *vma,
2308 struct intel_timeline *tl,
2309 struct dma_fence *fence)
2311 struct intel_gt_buffer_pool_node *node = vma->private;
2313 return i915_active_ref(&node->active, tl->fence_context, fence);
2317 parser_mark_active(struct eb_parse_work *pw, struct intel_timeline *tl)
2321 mutex_lock(&tl->mutex);
2323 err = __parser_mark_active(pw->shadow, tl, &pw->base.dma);
2327 if (pw->trampoline) {
2328 err = __parser_mark_active(pw->trampoline, tl, &pw->base.dma);
2334 mutex_unlock(&tl->mutex);
2338 static int eb_parse_pipeline(struct i915_execbuffer *eb,
2339 struct i915_vma *shadow,
2340 struct i915_vma *trampoline)
2342 struct eb_parse_work *pw;
2345 GEM_BUG_ON(overflows_type(eb->batch_start_offset, pw->batch_offset));
2346 GEM_BUG_ON(overflows_type(eb->batch_len, pw->batch_length));
2348 pw = kzalloc(sizeof(*pw), GFP_KERNEL);
2352 err = i915_active_acquire(&eb->batch->vma->active);
2356 err = i915_active_acquire(&shadow->active);
2361 err = i915_active_acquire(&trampoline->active);
2366 dma_fence_work_init(&pw->base, &eb_parse_ops);
2368 pw->engine = eb->engine;
2369 pw->batch = eb->batch->vma;
2370 pw->batch_offset = eb->batch_start_offset;
2371 pw->batch_length = eb->batch_len;
2372 pw->shadow = shadow;
2373 pw->trampoline = trampoline;
2375 /* Mark active refs early for this worker, in case we get interrupted */
2376 err = parser_mark_active(pw, eb->context->timeline);
2380 err = dma_resv_reserve_shared(pw->batch->resv, 1);
2384 /* Wait for all writes (and relocs) into the batch to complete */
2385 err = i915_sw_fence_await_reservation(&pw->base.chain,
2386 pw->batch->resv, NULL, false,
2391 /* Keep the batch alive and unwritten as we parse */
2392 dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma);
2394 /* Force execution to wait for completion of the parser */
2395 dma_resv_add_excl_fence(shadow->resv, &pw->base.dma);
2397 dma_fence_work_commit_imm(&pw->base);
2401 i915_sw_fence_set_error_once(&pw->base.chain, err);
2402 dma_fence_work_commit_imm(&pw->base);
2406 i915_active_release(&shadow->active);
2408 i915_active_release(&eb->batch->vma->active);
2414 static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma)
2417 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2418 * batch" bit. Hence we need to pin secure batches into the global gtt.
2419 * hsw should have this fixed, but bdw mucks it up again. */
2420 if (eb->batch_flags & I915_DISPATCH_SECURE)
2421 return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, 0);
2426 static int eb_parse(struct i915_execbuffer *eb)
2428 struct drm_i915_private *i915 = eb->i915;
2429 struct intel_gt_buffer_pool_node *pool = eb->batch_pool;
2430 struct i915_vma *shadow, *trampoline, *batch;
2434 if (!eb_use_cmdparser(eb)) {
2435 batch = eb_dispatch_secure(eb, eb->batch->vma);
2437 return PTR_ERR(batch);
2442 len = eb->batch_len;
2443 if (!CMDPARSER_USES_GGTT(eb->i915)) {
2445 * ppGTT backed shadow buffers must be mapped RO, to prevent
2446 * post-scan tampering
2448 if (!eb->context->vm->has_read_only) {
2450 "Cannot prevent post-scan tampering without RO capable vm\n");
2454 len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
2456 if (unlikely(len < eb->batch_len)) /* last paranoid check of overflow */
2460 pool = intel_gt_get_buffer_pool(eb->engine->gt, len);
2462 return PTR_ERR(pool);
2463 eb->batch_pool = pool;
2466 err = i915_gem_object_lock(pool->obj, &eb->ww);
2470 shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER);
2471 if (IS_ERR(shadow)) {
2472 err = PTR_ERR(shadow);
2475 i915_gem_object_set_readonly(shadow->obj);
2476 shadow->private = pool;
2479 if (CMDPARSER_USES_GGTT(eb->i915)) {
2480 trampoline = shadow;
2482 shadow = shadow_batch_pin(eb, pool->obj,
2483 &eb->engine->gt->ggtt->vm,
2485 if (IS_ERR(shadow)) {
2486 err = PTR_ERR(shadow);
2487 shadow = trampoline;
2490 shadow->private = pool;
2492 eb->batch_flags |= I915_DISPATCH_SECURE;
2495 batch = eb_dispatch_secure(eb, shadow);
2496 if (IS_ERR(batch)) {
2497 err = PTR_ERR(batch);
2498 goto err_trampoline;
2501 err = eb_parse_pipeline(eb, shadow, trampoline);
2503 goto err_unpin_batch;
2505 eb->batch = &eb->vma[eb->buffer_count++];
2506 eb->batch->vma = i915_vma_get(shadow);
2507 eb->batch->flags = __EXEC_OBJECT_HAS_PIN;
2509 eb->trampoline = trampoline;
2510 eb->batch_start_offset = 0;
2514 eb->batch = &eb->vma[eb->buffer_count++];
2515 eb->batch->flags = __EXEC_OBJECT_HAS_PIN;
2516 eb->batch->vma = i915_vma_get(batch);
2522 i915_vma_unpin(batch);
2525 i915_vma_unpin(trampoline);
2527 i915_vma_unpin(shadow);
2532 static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
2536 err = eb_move_to_gpu(eb);
2540 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2541 err = i915_reset_gen7_sol_offsets(eb->request);
2547 * After we completed waiting for other engines (using HW semaphores)
2548 * then we can signal that this request/batch is ready to run. This
2549 * allows us to determine if the batch is still waiting on the GPU
2550 * or actually running by checking the breadcrumb.
2552 if (eb->engine->emit_init_breadcrumb) {
2553 err = eb->engine->emit_init_breadcrumb(eb->request);
2558 err = eb->engine->emit_bb_start(eb->request,
2560 eb->batch_start_offset,
2566 if (eb->trampoline) {
2567 GEM_BUG_ON(eb->batch_start_offset);
2568 err = eb->engine->emit_bb_start(eb->request,
2569 eb->trampoline->node.start +
2576 if (intel_context_nopreempt(eb->context))
2577 __set_bit(I915_FENCE_FLAG_NOPREEMPT, &eb->request->fence.flags);
2582 static int num_vcs_engines(const struct drm_i915_private *i915)
2584 return hweight64(VDBOX_MASK(&i915->gt));
2588 * Find one BSD ring to dispatch the corresponding BSD command.
2589 * The engine index is returned.
2592 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2593 struct drm_file *file)
2595 struct drm_i915_file_private *file_priv = file->driver_priv;
2597 /* Check whether the file_priv has already selected one ring. */
2598 if ((int)file_priv->bsd_engine < 0)
2599 file_priv->bsd_engine =
2600 get_random_int() % num_vcs_engines(dev_priv);
2602 return file_priv->bsd_engine;
2605 static const enum intel_engine_id user_ring_map[] = {
2606 [I915_EXEC_DEFAULT] = RCS0,
2607 [I915_EXEC_RENDER] = RCS0,
2608 [I915_EXEC_BLT] = BCS0,
2609 [I915_EXEC_BSD] = VCS0,
2610 [I915_EXEC_VEBOX] = VECS0
2613 static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce)
2615 struct intel_ring *ring = ce->ring;
2616 struct intel_timeline *tl = ce->timeline;
2617 struct i915_request *rq;
2620 * Completely unscientific finger-in-the-air estimates for suitable
2621 * maximum user request size (to avoid blocking) and then backoff.
2623 if (intel_ring_update_space(ring) >= PAGE_SIZE)
2627 * Find a request that after waiting upon, there will be at least half
2628 * the ring available. The hysteresis allows us to compete for the
2629 * shared ring and should mean that we sleep less often prior to
2630 * claiming our resources, but not so long that the ring completely
2631 * drains before we can submit our next request.
2633 list_for_each_entry(rq, &tl->requests, link) {
2634 if (rq->ring != ring)
2637 if (__intel_ring_space(rq->postfix,
2638 ring->emit, ring->size) > ring->size / 2)
2641 if (&rq->link == &tl->requests)
2642 return NULL; /* weird, we will check again later for real */
2644 return i915_request_get(rq);
2647 static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
2649 struct intel_context *ce = eb->context;
2650 struct intel_timeline *tl;
2651 struct i915_request *rq = NULL;
2654 GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
2656 if (unlikely(intel_context_is_banned(ce)))
2657 return ERR_PTR(-EIO);
2660 * Pinning the contexts may generate requests in order to acquire
2661 * GGTT space, so do this first before we reserve a seqno for
2664 err = intel_context_pin_ww(ce, &eb->ww);
2666 return ERR_PTR(err);
2669 * Take a local wakeref for preparing to dispatch the execbuf as
2670 * we expect to access the hardware fairly frequently in the
2671 * process, and require the engine to be kept awake between accesses.
2672 * Upon dispatch, we acquire another prolonged wakeref that we hold
2673 * until the timeline is idle, which in turn releases the wakeref
2674 * taken on the engine, and the parent device.
2676 tl = intel_context_timeline_lock(ce);
2678 intel_context_unpin(ce);
2679 return ERR_CAST(tl);
2682 intel_context_enter(ce);
2684 rq = eb_throttle(eb, ce);
2685 intel_context_timeline_unlock(tl);
2687 eb->args->flags |= __EXEC_ENGINE_PINNED;
2691 static void eb_unpin_engine(struct i915_execbuffer *eb)
2693 struct intel_context *ce = eb->context;
2694 struct intel_timeline *tl = ce->timeline;
2696 if (!(eb->args->flags & __EXEC_ENGINE_PINNED))
2699 eb->args->flags &= ~__EXEC_ENGINE_PINNED;
2701 mutex_lock(&tl->mutex);
2702 intel_context_exit(ce);
2703 mutex_unlock(&tl->mutex);
2705 intel_context_unpin(ce);
2709 eb_select_legacy_ring(struct i915_execbuffer *eb)
2711 struct drm_i915_private *i915 = eb->i915;
2712 struct drm_i915_gem_execbuffer2 *args = eb->args;
2713 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2715 if (user_ring_id != I915_EXEC_BSD &&
2716 (args->flags & I915_EXEC_BSD_MASK)) {
2718 "execbuf with non bsd ring but with invalid "
2719 "bsd dispatch flags: %d\n", (int)(args->flags));
2723 if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) {
2724 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2726 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2727 bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
2728 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2729 bsd_idx <= I915_EXEC_BSD_RING2) {
2730 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2734 "execbuf with unknown bsd ring: %u\n",
2739 return _VCS(bsd_idx);
2742 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2743 drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n",
2748 return user_ring_map[user_ring_id];
2752 eb_select_engine(struct i915_execbuffer *eb)
2754 struct intel_context *ce;
2758 if (i915_gem_context_user_engines(eb->gem_context))
2759 idx = eb->args->flags & I915_EXEC_RING_MASK;
2761 idx = eb_select_legacy_ring(eb);
2763 ce = i915_gem_context_get_engine(eb->gem_context, idx);
2767 intel_gt_pm_get(ce->engine->gt);
2769 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
2770 err = intel_context_alloc_state(ce);
2776 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2777 * EIO if the GPU is already wedged.
2779 err = intel_gt_terminally_wedged(ce->engine->gt);
2784 eb->engine = ce->engine;
2787 * Make sure engine pool stays alive even if we call intel_context_put
2788 * during ww handling. The pool is destroyed when last pm reference
2789 * is dropped, which breaks our -EDEADLK handling.
2794 intel_gt_pm_put(ce->engine->gt);
2795 intel_context_put(ce);
2800 eb_put_engine(struct i915_execbuffer *eb)
2802 intel_gt_pm_put(eb->engine->gt);
2803 intel_context_put(eb->context);
2807 __free_fence_array(struct eb_fence *fences, unsigned int n)
2810 drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
2811 dma_fence_put(fences[n].dma_fence);
2812 kfree(fences[n].chain_fence);
2818 add_timeline_fence_array(struct i915_execbuffer *eb,
2819 const struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences)
2821 struct drm_i915_gem_exec_fence __user *user_fences;
2822 u64 __user *user_values;
2827 nfences = timeline_fences->fence_count;
2831 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2832 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2833 if (nfences > min_t(unsigned long,
2834 ULONG_MAX / sizeof(*user_fences),
2835 SIZE_MAX / sizeof(*f)) - eb->num_fences)
2838 user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
2839 if (!access_ok(user_fences, nfences * sizeof(*user_fences)))
2842 user_values = u64_to_user_ptr(timeline_fences->values_ptr);
2843 if (!access_ok(user_values, nfences * sizeof(*user_values)))
2846 f = krealloc(eb->fences,
2847 (eb->num_fences + nfences) * sizeof(*f),
2848 __GFP_NOWARN | GFP_KERNEL);
2853 f += eb->num_fences;
2855 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2856 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2859 struct drm_i915_gem_exec_fence user_fence;
2860 struct drm_syncobj *syncobj;
2861 struct dma_fence *fence = NULL;
2864 if (__copy_from_user(&user_fence,
2866 sizeof(user_fence)))
2869 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2872 if (__get_user(point, user_values++))
2875 syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2877 DRM_DEBUG("Invalid syncobj handle provided\n");
2881 fence = drm_syncobj_fence_get(syncobj);
2883 if (!fence && user_fence.flags &&
2884 !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2885 DRM_DEBUG("Syncobj handle has no fence\n");
2886 drm_syncobj_put(syncobj);
2891 err = dma_fence_chain_find_seqno(&fence, point);
2893 if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2894 DRM_DEBUG("Syncobj handle missing requested point %llu\n", point);
2895 dma_fence_put(fence);
2896 drm_syncobj_put(syncobj);
2901 * A point might have been signaled already and
2902 * garbage collected from the timeline. In this case
2903 * just ignore the point and carry on.
2905 if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2906 drm_syncobj_put(syncobj);
2911 * For timeline syncobjs we need to preallocate chains for
2914 if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
2916 * Waiting and signaling the same point (when point !=
2917 * 0) would break the timeline.
2919 if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2920 DRM_DEBUG("Trying to wait & signal the same timeline point.\n");
2921 dma_fence_put(fence);
2922 drm_syncobj_put(syncobj);
2927 kmalloc(sizeof(*f->chain_fence),
2929 if (!f->chain_fence) {
2930 drm_syncobj_put(syncobj);
2931 dma_fence_put(fence);
2935 f->chain_fence = NULL;
2938 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2939 f->dma_fence = fence;
2948 static int add_fence_array(struct i915_execbuffer *eb)
2950 struct drm_i915_gem_execbuffer2 *args = eb->args;
2951 struct drm_i915_gem_exec_fence __user *user;
2952 unsigned long num_fences = args->num_cliprects;
2955 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2961 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2962 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2963 if (num_fences > min_t(unsigned long,
2964 ULONG_MAX / sizeof(*user),
2965 SIZE_MAX / sizeof(*f) - eb->num_fences))
2968 user = u64_to_user_ptr(args->cliprects_ptr);
2969 if (!access_ok(user, num_fences * sizeof(*user)))
2972 f = krealloc(eb->fences,
2973 (eb->num_fences + num_fences) * sizeof(*f),
2974 __GFP_NOWARN | GFP_KERNEL);
2979 f += eb->num_fences;
2980 while (num_fences--) {
2981 struct drm_i915_gem_exec_fence user_fence;
2982 struct drm_syncobj *syncobj;
2983 struct dma_fence *fence = NULL;
2985 if (__copy_from_user(&user_fence, user++, sizeof(user_fence)))
2988 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2991 syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2993 DRM_DEBUG("Invalid syncobj handle provided\n");
2997 if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2998 fence = drm_syncobj_fence_get(syncobj);
3000 DRM_DEBUG("Syncobj handle has no fence\n");
3001 drm_syncobj_put(syncobj);
3006 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
3007 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
3009 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
3010 f->dma_fence = fence;
3012 f->chain_fence = NULL;
3020 static void put_fence_array(struct eb_fence *fences, int num_fences)
3023 __free_fence_array(fences, num_fences);
3027 await_fence_array(struct i915_execbuffer *eb)
3032 for (n = 0; n < eb->num_fences; n++) {
3033 struct drm_syncobj *syncobj;
3036 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
3038 if (!eb->fences[n].dma_fence)
3041 err = i915_request_await_dma_fence(eb->request,
3042 eb->fences[n].dma_fence);
3050 static void signal_fence_array(const struct i915_execbuffer *eb)
3052 struct dma_fence * const fence = &eb->request->fence;
3055 for (n = 0; n < eb->num_fences; n++) {
3056 struct drm_syncobj *syncobj;
3059 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
3060 if (!(flags & I915_EXEC_FENCE_SIGNAL))
3063 if (eb->fences[n].chain_fence) {
3064 drm_syncobj_add_point(syncobj,
3065 eb->fences[n].chain_fence,
3067 eb->fences[n].value);
3069 * The chain's ownership is transferred to the
3072 eb->fences[n].chain_fence = NULL;
3074 drm_syncobj_replace_fence(syncobj, fence);
3080 parse_timeline_fences(struct i915_user_extension __user *ext, void *data)
3082 struct i915_execbuffer *eb = data;
3083 struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
3085 if (copy_from_user(&timeline_fences, ext, sizeof(timeline_fences)))
3088 return add_timeline_fence_array(eb, &timeline_fences);
3091 static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
3093 struct i915_request *rq, *rn;
3095 list_for_each_entry_safe(rq, rn, &tl->requests, link)
3096 if (rq == end || !i915_request_retire(rq))
3100 static void eb_request_add(struct i915_execbuffer *eb)
3102 struct i915_request *rq = eb->request;
3103 struct intel_timeline * const tl = i915_request_timeline(rq);
3104 struct i915_sched_attr attr = {};
3105 struct i915_request *prev;
3107 lockdep_assert_held(&tl->mutex);
3108 lockdep_unpin_lock(&tl->mutex, rq->cookie);
3110 trace_i915_request_add(rq);
3112 prev = __i915_request_commit(rq);
3114 /* Check that the context wasn't destroyed before submission */
3115 if (likely(!intel_context_is_closed(eb->context))) {
3116 attr = eb->gem_context->sched;
3118 /* Serialise with context_close via the add_to_timeline */
3119 i915_request_set_error_once(rq, -ENOENT);
3120 __i915_request_skip(rq);
3123 __i915_request_queue(rq, &attr);
3125 /* Try to clean up the client's timeline after submitting the request */
3127 retire_requests(tl, prev);
3129 mutex_unlock(&tl->mutex);
3132 static const i915_user_extension_fn execbuf_extensions[] = {
3133 [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
3137 parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
3138 struct i915_execbuffer *eb)
3140 if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
3143 /* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
3144 * have another flag also using it at the same time.
3146 if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
3149 if (args->num_cliprects != 0)
3152 return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
3154 ARRAY_SIZE(execbuf_extensions),
3159 i915_gem_do_execbuffer(struct drm_device *dev,
3160 struct drm_file *file,
3161 struct drm_i915_gem_execbuffer2 *args,
3162 struct drm_i915_gem_exec_object2 *exec)
3164 struct drm_i915_private *i915 = to_i915(dev);
3165 struct i915_execbuffer eb;
3166 struct dma_fence *in_fence = NULL;
3167 struct sync_file *out_fence = NULL;
3168 struct i915_vma *batch;
3169 int out_fence_fd = -1;
3172 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
3173 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
3174 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
3179 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
3180 args->flags |= __EXEC_HAS_RELOC;
3183 eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
3184 eb.vma[0].vma = NULL;
3185 eb.reloc_pool = eb.batch_pool = NULL;
3186 eb.reloc_context = NULL;
3188 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
3189 reloc_cache_init(&eb.reloc_cache, eb.i915);
3191 eb.buffer_count = args->buffer_count;
3192 eb.batch_start_offset = args->batch_start_offset;
3193 eb.batch_len = args->batch_len;
3194 eb.trampoline = NULL;
3200 if (args->flags & I915_EXEC_SECURE) {
3201 if (INTEL_GEN(i915) >= 11)
3204 /* Return -EPERM to trigger fallback code on old binaries. */
3205 if (!HAS_SECURE_BATCHES(i915))
3208 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
3211 eb.batch_flags |= I915_DISPATCH_SECURE;
3213 if (args->flags & I915_EXEC_IS_PINNED)
3214 eb.batch_flags |= I915_DISPATCH_PINNED;
3216 err = parse_execbuf2_extensions(args, &eb);
3220 err = add_fence_array(&eb);
3224 #define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT)
3225 if (args->flags & IN_FENCES) {
3226 if ((args->flags & IN_FENCES) == IN_FENCES)
3229 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
3237 if (args->flags & I915_EXEC_FENCE_OUT) {
3238 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3239 if (out_fence_fd < 0) {
3245 err = eb_create(&eb);
3249 GEM_BUG_ON(!eb.lut_size);
3251 err = eb_select_context(&eb);
3255 err = eb_select_engine(&eb);
3259 err = eb_lookup_vmas(&eb);
3261 eb_release_vmas(&eb, true);
3265 i915_gem_ww_ctx_init(&eb.ww, true);
3267 err = eb_relocate_parse(&eb);
3270 * If the user expects the execobject.offset and
3271 * reloc.presumed_offset to be an exact match,
3272 * as for using NO_RELOC, then we cannot update
3273 * the execobject.offset until we have completed
3276 args->flags &= ~__EXEC_HAS_RELOC;
3280 ww_acquire_done(&eb.ww.ctx);
3282 batch = eb.batch->vma;
3284 /* All GPU relocation batches must be submitted prior to the user rq */
3285 GEM_BUG_ON(eb.reloc_cache.rq);
3287 /* Allocate a request for this batch buffer nice and early. */
3288 eb.request = i915_request_create(eb.context);
3289 if (IS_ERR(eb.request)) {
3290 err = PTR_ERR(eb.request);
3295 if (args->flags & I915_EXEC_FENCE_SUBMIT)
3296 err = i915_request_await_execution(eb.request,
3298 eb.engine->bond_execute);
3300 err = i915_request_await_dma_fence(eb.request,
3307 err = await_fence_array(&eb);
3312 if (out_fence_fd != -1) {
3313 out_fence = sync_file_create(&eb.request->fence);
3321 * Whilst this request exists, batch_obj will be on the
3322 * active_list, and so will hold the active reference. Only when this
3323 * request is retired will the the batch_obj be moved onto the
3324 * inactive_list and lose its active reference. Hence we do not need
3325 * to explicitly hold another reference here.
3327 eb.request->batch = batch;
3329 intel_gt_buffer_pool_mark_active(eb.batch_pool, eb.request);
3331 trace_i915_request_queue(eb.request, eb.batch_flags);
3332 err = eb_submit(&eb, batch);
3334 i915_request_get(eb.request);
3335 eb_request_add(&eb);
3338 signal_fence_array(&eb);
3342 fd_install(out_fence_fd, out_fence->file);
3343 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
3344 args->rsvd2 |= (u64)out_fence_fd << 32;
3347 fput(out_fence->file);
3350 i915_request_put(eb.request);
3353 eb_release_vmas(&eb, true);
3355 i915_vma_unpin(eb.trampoline);
3356 WARN_ON(err == -EDEADLK);
3357 i915_gem_ww_ctx_fini(&eb.ww);
3360 intel_gt_buffer_pool_put(eb.batch_pool);
3362 intel_gt_buffer_pool_put(eb.reloc_pool);
3363 if (eb.reloc_context)
3364 intel_context_put(eb.reloc_context);
3368 i915_gem_context_put(eb.gem_context);
3372 if (out_fence_fd != -1)
3373 put_unused_fd(out_fence_fd);
3375 dma_fence_put(in_fence);
3377 put_fence_array(eb.fences, eb.num_fences);
3381 static size_t eb_element_size(void)
3383 return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma);
3386 static bool check_buffer_count(size_t count)
3388 const size_t sz = eb_element_size();
3391 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
3392 * array size (see eb_create()). Otherwise, we can accept an array as
3393 * large as can be addressed (though use large arrays at your peril)!
3396 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
3400 * Legacy execbuffer just creates an exec2 list from the original exec object
3401 * list array and passes it to the real function.
3404 i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
3405 struct drm_file *file)
3407 struct drm_i915_private *i915 = to_i915(dev);
3408 struct drm_i915_gem_execbuffer *args = data;
3409 struct drm_i915_gem_execbuffer2 exec2;
3410 struct drm_i915_gem_exec_object *exec_list = NULL;
3411 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3412 const size_t count = args->buffer_count;
3416 if (!check_buffer_count(count)) {
3417 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3421 exec2.buffers_ptr = args->buffers_ptr;
3422 exec2.buffer_count = args->buffer_count;
3423 exec2.batch_start_offset = args->batch_start_offset;
3424 exec2.batch_len = args->batch_len;
3425 exec2.DR1 = args->DR1;
3426 exec2.DR4 = args->DR4;
3427 exec2.num_cliprects = args->num_cliprects;
3428 exec2.cliprects_ptr = args->cliprects_ptr;
3429 exec2.flags = I915_EXEC_RENDER;
3430 i915_execbuffer2_set_context_id(exec2, 0);
3432 err = i915_gem_check_execbuffer(&exec2);
3436 /* Copy in the exec list from userland */
3437 exec_list = kvmalloc_array(count, sizeof(*exec_list),
3438 __GFP_NOWARN | GFP_KERNEL);
3440 /* Allocate extra slots for use by the command parser */
3441 exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3442 __GFP_NOWARN | GFP_KERNEL);
3443 if (exec_list == NULL || exec2_list == NULL) {
3445 "Failed to allocate exec list for %d buffers\n",
3446 args->buffer_count);
3451 err = copy_from_user(exec_list,
3452 u64_to_user_ptr(args->buffers_ptr),
3453 sizeof(*exec_list) * count);
3455 drm_dbg(&i915->drm, "copy %d exec entries failed %d\n",
3456 args->buffer_count, err);
3462 for (i = 0; i < args->buffer_count; i++) {
3463 exec2_list[i].handle = exec_list[i].handle;
3464 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3465 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3466 exec2_list[i].alignment = exec_list[i].alignment;
3467 exec2_list[i].offset = exec_list[i].offset;
3468 if (INTEL_GEN(to_i915(dev)) < 4)
3469 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3471 exec2_list[i].flags = 0;
3474 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list);
3475 if (exec2.flags & __EXEC_HAS_RELOC) {
3476 struct drm_i915_gem_exec_object __user *user_exec_list =
3477 u64_to_user_ptr(args->buffers_ptr);
3479 /* Copy the new buffer offsets back to the user's exec list. */
3480 for (i = 0; i < args->buffer_count; i++) {
3481 if (!(exec2_list[i].offset & UPDATE))
3484 exec2_list[i].offset =
3485 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3486 exec2_list[i].offset &= PIN_OFFSET_MASK;
3487 if (__copy_to_user(&user_exec_list[i].offset,
3488 &exec2_list[i].offset,
3489 sizeof(user_exec_list[i].offset)))
3500 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
3501 struct drm_file *file)
3503 struct drm_i915_private *i915 = to_i915(dev);
3504 struct drm_i915_gem_execbuffer2 *args = data;
3505 struct drm_i915_gem_exec_object2 *exec2_list;
3506 const size_t count = args->buffer_count;
3509 if (!check_buffer_count(count)) {
3510 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3514 err = i915_gem_check_execbuffer(args);
3518 /* Allocate extra slots for use by the command parser */
3519 exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3520 __GFP_NOWARN | GFP_KERNEL);
3521 if (exec2_list == NULL) {
3522 drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n",
3526 if (copy_from_user(exec2_list,
3527 u64_to_user_ptr(args->buffers_ptr),
3528 sizeof(*exec2_list) * count)) {
3529 drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count);
3534 err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
3537 * Now that we have begun execution of the batchbuffer, we ignore
3538 * any new error after this point. Also given that we have already
3539 * updated the associated relocations, we try to write out the current
3540 * object locations irrespective of any error.
3542 if (args->flags & __EXEC_HAS_RELOC) {
3543 struct drm_i915_gem_exec_object2 __user *user_exec_list =
3544 u64_to_user_ptr(args->buffers_ptr);
3547 /* Copy the new buffer offsets back to the user's exec list. */
3549 * Note: count * sizeof(*user_exec_list) does not overflow,
3550 * because we checked 'count' in check_buffer_count().
3552 * And this range already got effectively checked earlier
3553 * when we did the "copy_from_user()" above.
3555 if (!user_write_access_begin(user_exec_list,
3556 count * sizeof(*user_exec_list)))
3559 for (i = 0; i < args->buffer_count; i++) {
3560 if (!(exec2_list[i].offset & UPDATE))
3563 exec2_list[i].offset =
3564 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3565 unsafe_put_user(exec2_list[i].offset,
3566 &user_exec_list[i].offset,
3570 user_write_access_end();
3574 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
3579 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3580 #include "selftests/i915_gem_execbuffer.c"