2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008,2010 Intel Corporation
7 #include <linux/intel-iommu.h>
8 #include <linux/dma-resv.h>
9 #include <linux/sync_file.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_syncobj.h>
14 #include "display/intel_frontbuffer.h"
16 #include "gem/i915_gem_ioctls.h"
17 #include "gt/intel_context.h"
18 #include "gt/intel_gpu_commands.h"
19 #include "gt/intel_gt.h"
20 #include "gt/intel_gt_buffer_pool.h"
21 #include "gt/intel_gt_pm.h"
22 #include "gt/intel_ring.h"
24 #include "pxp/intel_pxp.h"
27 #include "i915_gem_clflush.h"
28 #include "i915_gem_context.h"
29 #include "i915_gem_ioctls.h"
30 #include "i915_trace.h"
31 #include "i915_user_extensions.h"
32 #include "i915_vma_snapshot.h"
38 /** This vma's place in the execbuf reservation list */
39 struct drm_i915_gem_exec_object2 *exec;
40 struct list_head bind_link;
41 struct list_head reloc_link;
43 struct hlist_node node;
51 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
54 /* __EXEC_OBJECT_NO_RESERVE is BIT(31), defined in i915_vma.h */
55 #define __EXEC_OBJECT_HAS_PIN BIT(30)
56 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
57 #define __EXEC_OBJECT_USERPTR_INIT BIT(28)
58 #define __EXEC_OBJECT_NEEDS_MAP BIT(27)
59 #define __EXEC_OBJECT_NEEDS_BIAS BIT(26)
60 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 26) /* all of the above + */
61 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
63 #define __EXEC_HAS_RELOC BIT(31)
64 #define __EXEC_ENGINE_PINNED BIT(30)
65 #define __EXEC_USERPTR_USED BIT(29)
66 #define __EXEC_INTERNAL_FLAGS (~0u << 29)
67 #define UPDATE PIN_OFFSET_FIXED
69 #define BATCH_OFFSET_BIAS (256*1024)
71 #define __I915_EXEC_ILLEGAL_FLAGS \
72 (__I915_EXEC_UNKNOWN_FLAGS | \
73 I915_EXEC_CONSTANTS_MASK | \
74 I915_EXEC_RESOURCE_STREAMER)
76 /* Catch emission of unexpected errors for CI! */
77 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
80 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
86 * DOC: User command execution
88 * Userspace submits commands to be executed on the GPU as an instruction
89 * stream within a GEM object we call a batchbuffer. This instructions may
90 * refer to other GEM objects containing auxiliary state such as kernels,
91 * samplers, render targets and even secondary batchbuffers. Userspace does
92 * not know where in the GPU memory these objects reside and so before the
93 * batchbuffer is passed to the GPU for execution, those addresses in the
94 * batchbuffer and auxiliary objects are updated. This is known as relocation,
95 * or patching. To try and avoid having to relocate each object on the next
96 * execution, userspace is told the location of those objects in this pass,
97 * but this remains just a hint as the kernel may choose a new location for
98 * any object in the future.
100 * At the level of talking to the hardware, submitting a batchbuffer for the
101 * GPU to execute is to add content to a buffer from which the HW
102 * command streamer is reading.
104 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
105 * Execlists, this command is not placed on the same buffer as the
108 * 2. Add a command to invalidate caches to the buffer.
110 * 3. Add a batchbuffer start command to the buffer; the start command is
111 * essentially a token together with the GPU address of the batchbuffer
114 * 4. Add a pipeline flush to the buffer.
116 * 5. Add a memory write command to the buffer to record when the GPU
117 * is done executing the batchbuffer. The memory write writes the
118 * global sequence number of the request, ``i915_request::global_seqno``;
119 * the i915 driver uses the current value in the register to determine
120 * if the GPU has completed the batchbuffer.
122 * 6. Add a user interrupt command to the buffer. This command instructs
123 * the GPU to issue an interrupt when the command, pipeline flush and
124 * memory write are completed.
126 * 7. Inform the hardware of the additional commands added to the buffer
127 * (by updating the tail pointer).
129 * Processing an execbuf ioctl is conceptually split up into a few phases.
131 * 1. Validation - Ensure all the pointers, handles and flags are valid.
132 * 2. Reservation - Assign GPU address space for every object
133 * 3. Relocation - Update any addresses to point to the final locations
134 * 4. Serialisation - Order the request with respect to its dependencies
135 * 5. Construction - Construct a request to execute the batchbuffer
136 * 6. Submission (at some point in the future execution)
138 * Reserving resources for the execbuf is the most complicated phase. We
139 * neither want to have to migrate the object in the address space, nor do
140 * we want to have to update any relocations pointing to this object. Ideally,
141 * we want to leave the object where it is and for all the existing relocations
142 * to match. If the object is given a new address, or if userspace thinks the
143 * object is elsewhere, we have to parse all the relocation entries and update
144 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
145 * all the target addresses in all of its objects match the value in the
146 * relocation entries and that they all match the presumed offsets given by the
147 * list of execbuffer objects. Using this knowledge, we know that if we haven't
148 * moved any buffers, all the relocation entries are valid and we can skip
149 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
150 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
152 * The addresses written in the objects must match the corresponding
153 * reloc.presumed_offset which in turn must match the corresponding
156 * Any render targets written to in the batch must be flagged with
159 * To avoid stalling, execobject.offset should match the current
160 * address of that object within the active context.
162 * The reservation is done is multiple phases. First we try and keep any
163 * object already bound in its current location - so as long as meets the
164 * constraints imposed by the new execbuffer. Any object left unbound after the
165 * first pass is then fitted into any available idle space. If an object does
166 * not fit, all objects are removed from the reservation and the process rerun
167 * after sorting the objects into a priority order (more difficult to fit
168 * objects are tried first). Failing that, the entire VM is cleared and we try
169 * to fit the execbuf once last time before concluding that it simply will not
172 * A small complication to all of this is that we allow userspace not only to
173 * specify an alignment and a size for the object in the address space, but
174 * we also allow userspace to specify the exact offset. This objects are
175 * simpler to place (the location is known a priori) all we have to do is make
176 * sure the space is available.
178 * Once all the objects are in place, patching up the buried pointers to point
179 * to the final locations is a fairly simple job of walking over the relocation
180 * entry arrays, looking up the right address and rewriting the value into
181 * the object. Simple! ... The relocation entries are stored in user memory
182 * and so to access them we have to copy them into a local buffer. That copy
183 * has to avoid taking any pagefaults as they may lead back to a GEM object
184 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
185 * the relocation into multiple passes. First we try to do everything within an
186 * atomic context (avoid the pagefaults) which requires that we never wait. If
187 * we detect that we may wait, or if we need to fault, then we have to fallback
188 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
189 * bells yet?) Dropping the mutex means that we lose all the state we have
190 * built up so far for the execbuf and we must reset any global data. However,
191 * we do leave the objects pinned in their final locations - which is a
192 * potential issue for concurrent execbufs. Once we have left the mutex, we can
193 * allocate and copy all the relocation entries into a large array at our
194 * leisure, reacquire the mutex, reclaim all the objects and other state and
195 * then proceed to update any incorrect addresses with the objects.
197 * As we process the relocation entries, we maintain a record of whether the
198 * object is being written to. Using NORELOC, we expect userspace to provide
199 * this information instead. We also check whether we can skip the relocation
200 * by comparing the expected value inside the relocation entry with the target's
201 * final address. If they differ, we have to map the current object and rewrite
202 * the 4 or 8 byte pointer within.
204 * Serialising an execbuf is quite simple according to the rules of the GEM
205 * ABI. Execution within each context is ordered by the order of submission.
206 * Writes to any GEM object are in order of submission and are exclusive. Reads
207 * from a GEM object are unordered with respect to other reads, but ordered by
208 * writes. A write submitted after a read cannot occur before the read, and
209 * similarly any read submitted after a write cannot occur before the write.
210 * Writes are ordered between engines such that only one write occurs at any
211 * time (completing any reads beforehand) - using semaphores where available
212 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
213 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
214 * reads before starting, and any read (either using set-domain or pread) must
215 * flush all GPU writes before starting. (Note we only employ a barrier before,
216 * we currently rely on userspace not concurrently starting a new execution
217 * whilst reading or writing to an object. This may be an advantage or not
218 * depending on how much you trust userspace not to shoot themselves in the
219 * foot.) Serialisation may just result in the request being inserted into
220 * a DAG awaiting its turn, but most simple is to wait on the CPU until
221 * all dependencies are resolved.
223 * After all of that, is just a matter of closing the request and handing it to
224 * the hardware (well, leaving it in a queue to be executed). However, we also
225 * offer the ability for batchbuffers to be run with elevated privileges so
226 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
227 * Before any batch is given extra privileges we first must check that it
228 * contains no nefarious instructions, we check that each instruction is from
229 * our whitelist and all registers are also from an allowed list. We first
230 * copy the user's batchbuffer to a shadow (so that the user doesn't have
231 * access to it, either by the CPU or GPU as we scan it) and then parse each
232 * instruction. If everything is ok, we set a flag telling the hardware to run
233 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
237 struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
238 struct dma_fence *dma_fence;
240 struct dma_fence_chain *chain_fence;
243 struct i915_execbuffer {
244 struct drm_i915_private *i915; /** i915 backpointer */
245 struct drm_file *file; /** per-file lookup tables and limits */
246 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
247 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
250 struct intel_gt *gt; /* gt for the execbuf */
251 struct intel_context *context; /* logical state for the request */
252 struct i915_gem_context *gem_context; /** caller's context */
254 /** our requests to build */
255 struct i915_request *requests[MAX_ENGINE_INSTANCE + 1];
256 /** identity of the batch obj/vma */
257 struct eb_vma *batches[MAX_ENGINE_INSTANCE + 1];
258 struct i915_vma *trampoline; /** trampoline used for chaining */
260 /** used for excl fence in dma_resv objects when > 1 BB submitted */
261 struct dma_fence *composite_fence;
263 /** actual size of execobj[] as we may extend it for the cmdparser */
264 unsigned int buffer_count;
266 /* number of batches in execbuf IOCTL */
267 unsigned int num_batches;
269 /** list of vma not yet bound during reservation phase */
270 struct list_head unbound;
272 /** list of vma that have execobj.relocation_count */
273 struct list_head relocs;
275 struct i915_gem_ww_ctx ww;
278 * Track the most recently used object for relocations, as we
279 * frequently have to perform multiple relocations within the same
283 struct drm_mm_node node; /** temporary GTT binding */
284 unsigned long vaddr; /** Current kmap address */
285 unsigned long page; /** Currently mapped page index */
286 unsigned int graphics_ver; /** Cached value of GRAPHICS_VER */
287 bool use_64bit_reloc : 1;
290 bool needs_unfenced : 1;
293 u64 invalid_flags; /** Set of execobj.flags that are invalid */
295 /** Length of batch within object */
296 u64 batch_len[MAX_ENGINE_INSTANCE + 1];
297 u32 batch_start_offset; /** Location within object of batch */
298 u32 batch_flags; /** Flags composed for emit_bb_start() */
299 struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */
302 * Indicate either the size of the hastable used to resolve
303 * relocation handles, or if negative that we are using a direct
304 * index into the execobj[].
307 struct hlist_head *buckets; /** ht for relocation handles */
309 struct eb_fence *fences;
310 unsigned long num_fences;
311 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
312 struct i915_capture_list *capture_lists[MAX_ENGINE_INSTANCE + 1];
316 static int eb_parse(struct i915_execbuffer *eb);
317 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle);
318 static void eb_unpin_engine(struct i915_execbuffer *eb);
319 static void eb_capture_release(struct i915_execbuffer *eb);
321 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
323 return intel_engine_requires_cmd_parser(eb->context->engine) ||
324 (intel_engine_using_cmd_parser(eb->context->engine) &&
325 eb->args->batch_len);
328 static int eb_create(struct i915_execbuffer *eb)
330 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
331 unsigned int size = 1 + ilog2(eb->buffer_count);
334 * Without a 1:1 association between relocation handles and
335 * the execobject[] index, we instead create a hashtable.
336 * We size it dynamically based on available memory, starting
337 * first with 1:1 assocative hash and scaling back until
338 * the allocation succeeds.
340 * Later on we use a positive lut_size to indicate we are
341 * using this hashtable, and a negative value to indicate a
347 /* While we can still reduce the allocation size, don't
348 * raise a warning and allow the allocation to fail.
349 * On the last pass though, we want to try as hard
350 * as possible to perform the allocation and warn
355 flags |= __GFP_NORETRY | __GFP_NOWARN;
357 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
368 eb->lut_size = -eb->buffer_count;
375 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
376 const struct i915_vma *vma,
379 if (vma->node.size < entry->pad_to_size)
382 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
385 if (flags & EXEC_OBJECT_PINNED &&
386 vma->node.start != entry->offset)
389 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
390 vma->node.start < BATCH_OFFSET_BIAS)
393 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
394 (vma->node.start + vma->node.size + 4095) >> 32)
397 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
398 !i915_vma_is_map_and_fenceable(vma))
404 static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,
405 unsigned int exec_flags)
409 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
410 pin_flags |= PIN_GLOBAL;
413 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
414 * limit address to the first 4GBs for unflagged objects.
416 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
417 pin_flags |= PIN_ZONE_4G;
419 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
420 pin_flags |= PIN_MAPPABLE;
422 if (exec_flags & EXEC_OBJECT_PINNED)
423 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
424 else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS)
425 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
431 eb_pin_vma(struct i915_execbuffer *eb,
432 const struct drm_i915_gem_exec_object2 *entry,
435 struct i915_vma *vma = ev->vma;
440 pin_flags = vma->node.start;
442 pin_flags = entry->offset & PIN_OFFSET_MASK;
444 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
445 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
446 pin_flags |= PIN_GLOBAL;
448 /* Attempt to reuse the current location if available */
449 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags);
454 if (entry->flags & EXEC_OBJECT_PINNED)
457 /* Failing that pick any _free_ space if suitable */
458 err = i915_vma_pin_ww(vma, &eb->ww,
461 eb_pin_flags(entry, ev->flags) |
462 PIN_USER | PIN_NOEVICT);
467 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
468 err = i915_vma_pin_fence(vma);
475 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
478 ev->flags |= __EXEC_OBJECT_HAS_PIN;
479 if (eb_vma_misplaced(entry, vma, ev->flags))
486 eb_unreserve_vma(struct eb_vma *ev)
488 if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
491 if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
492 __i915_vma_unpin_fence(ev->vma);
494 __i915_vma_unpin(ev->vma);
495 ev->flags &= ~__EXEC_OBJECT_RESERVED;
499 eb_validate_vma(struct i915_execbuffer *eb,
500 struct drm_i915_gem_exec_object2 *entry,
501 struct i915_vma *vma)
503 /* Relocations are disallowed for all platforms after TGL-LP. This
504 * also covers all platforms with local memory.
506 if (entry->relocation_count &&
507 GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
510 if (unlikely(entry->flags & eb->invalid_flags))
513 if (unlikely(entry->alignment &&
514 !is_power_of_2_u64(entry->alignment)))
518 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
519 * any non-page-aligned or non-canonical addresses.
521 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
522 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
525 /* pad_to_size was once a reserved field, so sanitize it */
526 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
527 if (unlikely(offset_in_page(entry->pad_to_size)))
530 entry->pad_to_size = 0;
533 * From drm_mm perspective address space is continuous,
534 * so from this point we're always using non-canonical
537 entry->offset = gen8_noncanonical_addr(entry->offset);
539 if (!eb->reloc_cache.has_fence) {
540 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
542 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
543 eb->reloc_cache.needs_unfenced) &&
544 i915_gem_object_is_tiled(vma->obj))
545 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
552 is_batch_buffer(struct i915_execbuffer *eb, unsigned int buffer_idx)
554 return eb->args->flags & I915_EXEC_BATCH_FIRST ?
555 buffer_idx < eb->num_batches :
556 buffer_idx >= eb->args->buffer_count - eb->num_batches;
560 eb_add_vma(struct i915_execbuffer *eb,
561 unsigned int *current_batch,
563 struct i915_vma *vma)
565 struct drm_i915_private *i915 = eb->i915;
566 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
567 struct eb_vma *ev = &eb->vma[i];
571 ev->flags = entry->flags;
573 if (eb->lut_size > 0) {
574 ev->handle = entry->handle;
575 hlist_add_head(&ev->node,
576 &eb->buckets[hash_32(entry->handle,
580 if (entry->relocation_count)
581 list_add_tail(&ev->reloc_link, &eb->relocs);
584 * SNA is doing fancy tricks with compressing batch buffers, which leads
585 * to negative relocation deltas. Usually that works out ok since the
586 * relocate address is still positive, except when the batch is placed
587 * very low in the GTT. Ensure this doesn't happen.
589 * Note that actual hangs have only been observed on gen7, but for
590 * paranoia do it everywhere.
592 if (is_batch_buffer(eb, i)) {
593 if (entry->relocation_count &&
594 !(ev->flags & EXEC_OBJECT_PINNED))
595 ev->flags |= __EXEC_OBJECT_NEEDS_BIAS;
596 if (eb->reloc_cache.has_fence)
597 ev->flags |= EXEC_OBJECT_NEEDS_FENCE;
599 eb->batches[*current_batch] = ev;
601 if (unlikely(ev->flags & EXEC_OBJECT_WRITE)) {
603 "Attempting to use self-modifying batch buffer\n");
607 if (range_overflows_t(u64,
608 eb->batch_start_offset,
611 drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
615 if (eb->args->batch_len == 0)
616 eb->batch_len[*current_batch] = ev->vma->size -
617 eb->batch_start_offset;
619 eb->batch_len[*current_batch] = eb->args->batch_len;
620 if (unlikely(eb->batch_len[*current_batch] == 0)) { /* impossible! */
621 drm_dbg(&i915->drm, "Invalid batch length\n");
631 static inline int use_cpu_reloc(const struct reloc_cache *cache,
632 const struct drm_i915_gem_object *obj)
634 if (!i915_gem_object_has_struct_page(obj))
637 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
640 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
643 return (cache->has_llc ||
645 obj->cache_level != I915_CACHE_NONE);
648 static int eb_reserve_vma(struct i915_execbuffer *eb,
652 struct drm_i915_gem_exec_object2 *entry = ev->exec;
653 struct i915_vma *vma = ev->vma;
656 if (drm_mm_node_allocated(&vma->node) &&
657 eb_vma_misplaced(entry, vma, ev->flags)) {
658 err = i915_vma_unbind(vma);
663 err = i915_vma_pin_ww(vma, &eb->ww,
664 entry->pad_to_size, entry->alignment,
665 eb_pin_flags(entry, ev->flags) | pin_flags);
669 if (entry->offset != vma->node.start) {
670 entry->offset = vma->node.start | UPDATE;
671 eb->args->flags |= __EXEC_HAS_RELOC;
674 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
675 err = i915_vma_pin_fence(vma);
682 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
685 ev->flags |= __EXEC_OBJECT_HAS_PIN;
686 GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags));
691 static int eb_reserve(struct i915_execbuffer *eb)
693 const unsigned int count = eb->buffer_count;
694 unsigned int pin_flags = PIN_USER | PIN_NONBLOCK;
695 struct list_head last;
697 unsigned int i, pass;
701 * Attempt to pin all of the buffers into the GTT.
702 * This is done in 3 phases:
704 * 1a. Unbind all objects that do not match the GTT constraints for
705 * the execbuffer (fenceable, mappable, alignment etc).
706 * 1b. Increment pin count for already bound objects.
707 * 2. Bind new objects.
708 * 3. Decrement pin count.
710 * This avoid unnecessary unbinding of later objects in order to make
711 * room for the earlier objects *unless* we need to defragment.
715 list_for_each_entry(ev, &eb->unbound, bind_link) {
716 err = eb_reserve_vma(eb, ev, pin_flags);
723 /* Resort *all* the objects into priority order */
724 INIT_LIST_HEAD(&eb->unbound);
725 INIT_LIST_HEAD(&last);
726 for (i = 0; i < count; i++) {
731 if (flags & EXEC_OBJECT_PINNED &&
732 flags & __EXEC_OBJECT_HAS_PIN)
735 eb_unreserve_vma(ev);
737 if (flags & EXEC_OBJECT_PINNED)
738 /* Pinned must have their slot */
739 list_add(&ev->bind_link, &eb->unbound);
740 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
741 /* Map require the lowest 256MiB (aperture) */
742 list_add_tail(&ev->bind_link, &eb->unbound);
743 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
744 /* Prioritise 4GiB region for restricted bo */
745 list_add(&ev->bind_link, &last);
747 list_add_tail(&ev->bind_link, &last);
749 list_splice_tail(&last, &eb->unbound);
756 /* Too fragmented, unbind everything and retry */
757 mutex_lock(&eb->context->vm->mutex);
758 err = i915_gem_evict_vm(eb->context->vm);
759 mutex_unlock(&eb->context->vm->mutex);
768 pin_flags = PIN_USER;
772 static int eb_select_context(struct i915_execbuffer *eb)
774 struct i915_gem_context *ctx;
776 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
777 if (unlikely(IS_ERR(ctx)))
780 eb->gem_context = ctx;
781 if (i915_gem_context_has_full_ppgtt(ctx))
782 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
787 static int __eb_add_lut(struct i915_execbuffer *eb,
788 u32 handle, struct i915_vma *vma)
790 struct i915_gem_context *ctx = eb->gem_context;
791 struct i915_lut_handle *lut;
794 lut = i915_lut_handle_alloc();
799 if (!atomic_fetch_inc(&vma->open_count))
800 i915_vma_reopen(vma);
801 lut->handle = handle;
804 /* Check that the context hasn't been closed in the meantime */
806 if (!mutex_lock_interruptible(&ctx->lut_mutex)) {
807 if (likely(!i915_gem_context_is_closed(ctx)))
808 err = radix_tree_insert(&ctx->handles_vma, handle, vma);
811 if (err == 0) { /* And nor has this handle */
812 struct drm_i915_gem_object *obj = vma->obj;
814 spin_lock(&obj->lut_lock);
815 if (idr_find(&eb->file->object_idr, handle) == obj) {
816 list_add(&lut->obj_link, &obj->lut_list);
818 radix_tree_delete(&ctx->handles_vma, handle);
821 spin_unlock(&obj->lut_lock);
823 mutex_unlock(&ctx->lut_mutex);
833 i915_lut_handle_free(lut);
837 static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
839 struct i915_address_space *vm = eb->context->vm;
842 struct drm_i915_gem_object *obj;
843 struct i915_vma *vma;
847 vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
848 if (likely(vma && vma->vm == vm))
849 vma = i915_vma_tryget(vma);
854 obj = i915_gem_object_lookup(eb->file, handle);
856 return ERR_PTR(-ENOENT);
859 * If the user has opted-in for protected-object tracking, make
860 * sure the object encryption can be used.
861 * We only need to do this when the object is first used with
862 * this context, because the context itself will be banned when
863 * the protected objects become invalid.
865 if (i915_gem_context_uses_protected_content(eb->gem_context) &&
866 i915_gem_object_is_protected(obj)) {
867 err = intel_pxp_key_check(&vm->gt->pxp, obj, true);
869 i915_gem_object_put(obj);
874 vma = i915_vma_instance(obj, vm, NULL);
876 i915_gem_object_put(obj);
880 err = __eb_add_lut(eb, handle, vma);
884 i915_gem_object_put(obj);
890 static int eb_lookup_vmas(struct i915_execbuffer *eb)
892 unsigned int i, current_batch = 0;
895 INIT_LIST_HEAD(&eb->relocs);
897 for (i = 0; i < eb->buffer_count; i++) {
898 struct i915_vma *vma;
900 vma = eb_lookup_vma(eb, eb->exec[i].handle);
906 err = eb_validate_vma(eb, &eb->exec[i], vma);
912 err = eb_add_vma(eb, ¤t_batch, i, vma);
916 if (i915_gem_object_is_userptr(vma->obj)) {
917 err = i915_gem_object_userptr_submit_init(vma->obj);
919 if (i + 1 < eb->buffer_count) {
921 * Execbuffer code expects last vma entry to be NULL,
922 * since we already initialized this entry,
923 * set the next value to NULL or we mess up
926 eb->vma[i + 1].vma = NULL;
932 eb->vma[i].flags |= __EXEC_OBJECT_USERPTR_INIT;
933 eb->args->flags |= __EXEC_USERPTR_USED;
940 eb->vma[i].vma = NULL;
944 static int eb_lock_vmas(struct i915_execbuffer *eb)
949 for (i = 0; i < eb->buffer_count; i++) {
950 struct eb_vma *ev = &eb->vma[i];
951 struct i915_vma *vma = ev->vma;
953 err = i915_gem_object_lock(vma->obj, &eb->ww);
961 static int eb_validate_vmas(struct i915_execbuffer *eb)
966 INIT_LIST_HEAD(&eb->unbound);
968 err = eb_lock_vmas(eb);
972 for (i = 0; i < eb->buffer_count; i++) {
973 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
974 struct eb_vma *ev = &eb->vma[i];
975 struct i915_vma *vma = ev->vma;
977 err = eb_pin_vma(eb, entry, ev);
982 if (entry->offset != vma->node.start) {
983 entry->offset = vma->node.start | UPDATE;
984 eb->args->flags |= __EXEC_HAS_RELOC;
987 eb_unreserve_vma(ev);
989 list_add_tail(&ev->bind_link, &eb->unbound);
990 if (drm_mm_node_allocated(&vma->node)) {
991 err = i915_vma_unbind(vma);
997 if (!(ev->flags & EXEC_OBJECT_WRITE)) {
998 err = dma_resv_reserve_shared(vma->obj->base.resv, 1);
1003 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
1004 eb_vma_misplaced(&eb->exec[i], vma, ev->flags));
1007 if (!list_empty(&eb->unbound))
1008 return eb_reserve(eb);
1013 static struct eb_vma *
1014 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
1016 if (eb->lut_size < 0) {
1017 if (handle >= -eb->lut_size)
1019 return &eb->vma[handle];
1021 struct hlist_head *head;
1024 head = &eb->buckets[hash_32(handle, eb->lut_size)];
1025 hlist_for_each_entry(ev, head, node) {
1026 if (ev->handle == handle)
1033 static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
1035 const unsigned int count = eb->buffer_count;
1038 for (i = 0; i < count; i++) {
1039 struct eb_vma *ev = &eb->vma[i];
1040 struct i915_vma *vma = ev->vma;
1045 eb_unreserve_vma(ev);
1051 eb_capture_release(eb);
1052 eb_unpin_engine(eb);
1055 static void eb_destroy(const struct i915_execbuffer *eb)
1057 if (eb->lut_size > 0)
1062 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
1063 const struct i915_vma *target)
1065 return gen8_canonical_addr((int)reloc->delta + target->node.start);
1068 static void reloc_cache_init(struct reloc_cache *cache,
1069 struct drm_i915_private *i915)
1073 /* Must be a variable in the struct to allow GCC to unroll. */
1074 cache->graphics_ver = GRAPHICS_VER(i915);
1075 cache->has_llc = HAS_LLC(i915);
1076 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
1077 cache->has_fence = cache->graphics_ver < 4;
1078 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
1079 cache->node.flags = 0;
1082 static inline void *unmask_page(unsigned long p)
1084 return (void *)(uintptr_t)(p & PAGE_MASK);
1087 static inline unsigned int unmask_flags(unsigned long p)
1089 return p & ~PAGE_MASK;
1092 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
1094 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
1096 struct drm_i915_private *i915 =
1097 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
1101 static void reloc_cache_unmap(struct reloc_cache *cache)
1108 vaddr = unmask_page(cache->vaddr);
1109 if (cache->vaddr & KMAP)
1110 kunmap_atomic(vaddr);
1112 io_mapping_unmap_atomic((void __iomem *)vaddr);
1115 static void reloc_cache_remap(struct reloc_cache *cache,
1116 struct drm_i915_gem_object *obj)
1123 if (cache->vaddr & KMAP) {
1124 struct page *page = i915_gem_object_get_page(obj, cache->page);
1126 vaddr = kmap_atomic(page);
1127 cache->vaddr = unmask_flags(cache->vaddr) |
1128 (unsigned long)vaddr;
1130 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1131 unsigned long offset;
1133 offset = cache->node.start;
1134 if (!drm_mm_node_allocated(&cache->node))
1135 offset += cache->page << PAGE_SHIFT;
1137 cache->vaddr = (unsigned long)
1138 io_mapping_map_atomic_wc(&ggtt->iomap, offset);
1142 static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
1149 vaddr = unmask_page(cache->vaddr);
1150 if (cache->vaddr & KMAP) {
1151 struct drm_i915_gem_object *obj =
1152 (struct drm_i915_gem_object *)cache->node.mm;
1153 if (cache->vaddr & CLFLUSH_AFTER)
1156 kunmap_atomic(vaddr);
1157 i915_gem_object_finish_access(obj);
1159 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1161 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1162 io_mapping_unmap_atomic((void __iomem *)vaddr);
1164 if (drm_mm_node_allocated(&cache->node)) {
1165 ggtt->vm.clear_range(&ggtt->vm,
1168 mutex_lock(&ggtt->vm.mutex);
1169 drm_mm_remove_node(&cache->node);
1170 mutex_unlock(&ggtt->vm.mutex);
1172 i915_vma_unpin((struct i915_vma *)cache->node.mm);
1180 static void *reloc_kmap(struct drm_i915_gem_object *obj,
1181 struct reloc_cache *cache,
1182 unsigned long pageno)
1188 kunmap_atomic(unmask_page(cache->vaddr));
1190 unsigned int flushes;
1193 err = i915_gem_object_prepare_write(obj, &flushes);
1195 return ERR_PTR(err);
1197 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1198 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1200 cache->vaddr = flushes | KMAP;
1201 cache->node.mm = (void *)obj;
1206 page = i915_gem_object_get_page(obj, pageno);
1208 set_page_dirty(page);
1210 vaddr = kmap_atomic(page);
1211 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1212 cache->page = pageno;
1217 static void *reloc_iomap(struct drm_i915_gem_object *obj,
1218 struct i915_execbuffer *eb,
1221 struct reloc_cache *cache = &eb->reloc_cache;
1222 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1223 unsigned long offset;
1227 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1228 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1230 struct i915_vma *vma;
1233 if (i915_gem_object_is_tiled(obj))
1234 return ERR_PTR(-EINVAL);
1236 if (use_cpu_reloc(cache, obj))
1239 err = i915_gem_object_set_to_gtt_domain(obj, true);
1241 return ERR_PTR(err);
1243 vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0,
1245 PIN_NONBLOCK /* NOWARN */ |
1247 if (vma == ERR_PTR(-EDEADLK))
1251 memset(&cache->node, 0, sizeof(cache->node));
1252 mutex_lock(&ggtt->vm.mutex);
1253 err = drm_mm_insert_node_in_range
1254 (&ggtt->vm.mm, &cache->node,
1255 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1256 0, ggtt->mappable_end,
1258 mutex_unlock(&ggtt->vm.mutex);
1259 if (err) /* no inactive aperture space, use cpu reloc */
1262 cache->node.start = vma->node.start;
1263 cache->node.mm = (void *)vma;
1267 offset = cache->node.start;
1268 if (drm_mm_node_allocated(&cache->node)) {
1269 ggtt->vm.insert_page(&ggtt->vm,
1270 i915_gem_object_get_dma_address(obj, page),
1271 offset, I915_CACHE_NONE, 0);
1273 offset += page << PAGE_SHIFT;
1276 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1279 cache->vaddr = (unsigned long)vaddr;
1284 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1285 struct i915_execbuffer *eb,
1288 struct reloc_cache *cache = &eb->reloc_cache;
1291 if (cache->page == page) {
1292 vaddr = unmask_page(cache->vaddr);
1295 if ((cache->vaddr & KMAP) == 0)
1296 vaddr = reloc_iomap(obj, eb, page);
1298 vaddr = reloc_kmap(obj, cache, page);
1304 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1306 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1307 if (flushes & CLFLUSH_BEFORE) {
1315 * Writes to the same cacheline are serialised by the CPU
1316 * (including clflush). On the write path, we only require
1317 * that it hits memory in an orderly fashion and place
1318 * mb barriers at the start and end of the relocation phase
1319 * to ensure ordering of clflush wrt to the system.
1321 if (flushes & CLFLUSH_AFTER)
1328 relocate_entry(struct i915_vma *vma,
1329 const struct drm_i915_gem_relocation_entry *reloc,
1330 struct i915_execbuffer *eb,
1331 const struct i915_vma *target)
1333 u64 target_addr = relocation_target(reloc, target);
1334 u64 offset = reloc->offset;
1335 bool wide = eb->reloc_cache.use_64bit_reloc;
1339 vaddr = reloc_vaddr(vma->obj, eb,
1340 offset >> PAGE_SHIFT);
1342 return PTR_ERR(vaddr);
1344 GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32)));
1345 clflush_write32(vaddr + offset_in_page(offset),
1346 lower_32_bits(target_addr),
1347 eb->reloc_cache.vaddr);
1350 offset += sizeof(u32);
1356 return target->node.start | UPDATE;
1360 eb_relocate_entry(struct i915_execbuffer *eb,
1362 const struct drm_i915_gem_relocation_entry *reloc)
1364 struct drm_i915_private *i915 = eb->i915;
1365 struct eb_vma *target;
1368 /* we've already hold a reference to all valid objects */
1369 target = eb_get_vma(eb, reloc->target_handle);
1370 if (unlikely(!target))
1373 /* Validate that the target is in a valid r/w GPU domain */
1374 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1375 drm_dbg(&i915->drm, "reloc with multiple write domains: "
1376 "target %d offset %d "
1377 "read %08x write %08x",
1378 reloc->target_handle,
1379 (int) reloc->offset,
1380 reloc->read_domains,
1381 reloc->write_domain);
1384 if (unlikely((reloc->write_domain | reloc->read_domains)
1385 & ~I915_GEM_GPU_DOMAINS)) {
1386 drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: "
1387 "target %d offset %d "
1388 "read %08x write %08x",
1389 reloc->target_handle,
1390 (int) reloc->offset,
1391 reloc->read_domains,
1392 reloc->write_domain);
1396 if (reloc->write_domain) {
1397 target->flags |= EXEC_OBJECT_WRITE;
1400 * Sandybridge PPGTT errata: We need a global gtt mapping
1401 * for MI and pipe_control writes because the gpu doesn't
1402 * properly redirect them through the ppgtt for non_secure
1405 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1406 GRAPHICS_VER(eb->i915) == 6 &&
1407 !i915_vma_is_bound(target->vma, I915_VMA_GLOBAL_BIND)) {
1408 struct i915_vma *vma = target->vma;
1410 reloc_cache_unmap(&eb->reloc_cache);
1411 mutex_lock(&vma->vm->mutex);
1412 err = i915_vma_bind(target->vma,
1413 target->vma->obj->cache_level,
1415 mutex_unlock(&vma->vm->mutex);
1416 reloc_cache_remap(&eb->reloc_cache, ev->vma->obj);
1423 * If the relocation already has the right value in it, no
1424 * more work needs to be done.
1426 if (!DBG_FORCE_RELOC &&
1427 gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
1430 /* Check that the relocation address is valid... */
1431 if (unlikely(reloc->offset >
1432 ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1433 drm_dbg(&i915->drm, "Relocation beyond object bounds: "
1434 "target %d offset %d size %d.\n",
1435 reloc->target_handle,
1437 (int)ev->vma->size);
1440 if (unlikely(reloc->offset & 3)) {
1441 drm_dbg(&i915->drm, "Relocation not 4-byte aligned: "
1442 "target %d offset %d.\n",
1443 reloc->target_handle,
1444 (int)reloc->offset);
1449 * If we write into the object, we need to force the synchronisation
1450 * barrier, either with an asynchronous clflush or if we executed the
1451 * patching using the GPU (though that should be serialised by the
1452 * timeline). To be completely sure, and since we are required to
1453 * do relocations we are already stalling, disable the user's opt
1454 * out of our synchronisation.
1456 ev->flags &= ~EXEC_OBJECT_ASYNC;
1458 /* and update the user's relocation entry */
1459 return relocate_entry(ev->vma, reloc, eb, target->vma);
1462 static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev)
1464 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1465 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1466 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1467 struct drm_i915_gem_relocation_entry __user *urelocs =
1468 u64_to_user_ptr(entry->relocs_ptr);
1469 unsigned long remain = entry->relocation_count;
1471 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1475 * We must check that the entire relocation array is safe
1476 * to read. However, if the array is not writable the user loses
1477 * the updated relocation values.
1479 if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs))))
1483 struct drm_i915_gem_relocation_entry *r = stack;
1484 unsigned int count =
1485 min_t(unsigned long, remain, ARRAY_SIZE(stack));
1486 unsigned int copied;
1489 * This is the fast path and we cannot handle a pagefault
1490 * whilst holding the struct mutex lest the user pass in the
1491 * relocations contained within a mmaped bo. For in such a case
1492 * we, the page fault handler would call i915_gem_fault() and
1493 * we would try to acquire the struct mutex again. Obviously
1494 * this is bad and so lockdep complains vehemently.
1496 pagefault_disable();
1497 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1499 if (unlikely(copied)) {
1506 u64 offset = eb_relocate_entry(eb, ev, r);
1508 if (likely(offset == 0)) {
1509 } else if ((s64)offset < 0) {
1510 remain = (int)offset;
1514 * Note that reporting an error now
1515 * leaves everything in an inconsistent
1516 * state as we have *already* changed
1517 * the relocation value inside the
1518 * object. As we have not changed the
1519 * reloc.presumed_offset or will not
1520 * change the execobject.offset, on the
1521 * call we may not rewrite the value
1522 * inside the object, leaving it
1523 * dangling and causing a GPU hang. Unless
1524 * userspace dynamically rebuilds the
1525 * relocations on each execbuf rather than
1526 * presume a static tree.
1528 * We did previously check if the relocations
1529 * were writable (access_ok), an error now
1530 * would be a strange race with mprotect,
1531 * having already demonstrated that we
1532 * can read from this userspace address.
1534 offset = gen8_canonical_addr(offset & ~UPDATE);
1536 &urelocs[r - stack].presumed_offset);
1538 } while (r++, --count);
1539 urelocs += ARRAY_SIZE(stack);
1542 reloc_cache_reset(&eb->reloc_cache, eb);
1547 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
1549 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1550 struct drm_i915_gem_relocation_entry *relocs =
1551 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1555 for (i = 0; i < entry->relocation_count; i++) {
1556 u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);
1558 if ((s64)offset < 0) {
1565 reloc_cache_reset(&eb->reloc_cache, eb);
1569 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1571 const char __user *addr, *end;
1573 char __maybe_unused c;
1575 size = entry->relocation_count;
1579 if (size > N_RELOC(ULONG_MAX))
1582 addr = u64_to_user_ptr(entry->relocs_ptr);
1583 size *= sizeof(struct drm_i915_gem_relocation_entry);
1584 if (!access_ok(addr, size))
1588 for (; addr < end; addr += PAGE_SIZE) {
1589 int err = __get_user(c, addr);
1593 return __get_user(c, end - 1);
1596 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1598 struct drm_i915_gem_relocation_entry *relocs;
1599 const unsigned int count = eb->buffer_count;
1603 for (i = 0; i < count; i++) {
1604 const unsigned int nreloc = eb->exec[i].relocation_count;
1605 struct drm_i915_gem_relocation_entry __user *urelocs;
1607 unsigned long copied;
1612 err = check_relocations(&eb->exec[i]);
1616 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1617 size = nreloc * sizeof(*relocs);
1619 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1625 /* copy_from_user is limited to < 4GiB */
1629 min_t(u64, BIT_ULL(31), size - copied);
1631 if (__copy_from_user((char *)relocs + copied,
1632 (char __user *)urelocs + copied,
1637 } while (copied < size);
1640 * As we do not update the known relocation offsets after
1641 * relocating (due to the complexities in lock handling),
1642 * we need to mark them as invalid now so that we force the
1643 * relocation processing next time. Just in case the target
1644 * object is evicted and then rebound into its old
1645 * presumed_offset before the next execbuffer - if that
1646 * happened we would make the mistake of assuming that the
1647 * relocations were valid.
1649 if (!user_access_begin(urelocs, size))
1652 for (copied = 0; copied < nreloc; copied++)
1654 &urelocs[copied].presumed_offset,
1658 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1670 relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1671 if (eb->exec[i].relocation_count)
1677 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1679 const unsigned int count = eb->buffer_count;
1682 for (i = 0; i < count; i++) {
1685 err = check_relocations(&eb->exec[i]);
1693 static int eb_reinit_userptr(struct i915_execbuffer *eb)
1695 const unsigned int count = eb->buffer_count;
1699 if (likely(!(eb->args->flags & __EXEC_USERPTR_USED)))
1702 for (i = 0; i < count; i++) {
1703 struct eb_vma *ev = &eb->vma[i];
1705 if (!i915_gem_object_is_userptr(ev->vma->obj))
1708 ret = i915_gem_object_userptr_submit_init(ev->vma->obj);
1712 ev->flags |= __EXEC_OBJECT_USERPTR_INIT;
1718 static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
1720 bool have_copy = false;
1725 if (signal_pending(current)) {
1730 /* We may process another execbuffer during the unlock... */
1731 eb_release_vmas(eb, false);
1732 i915_gem_ww_ctx_fini(&eb->ww);
1735 * We take 3 passes through the slowpatch.
1737 * 1 - we try to just prefault all the user relocation entries and
1738 * then attempt to reuse the atomic pagefault disabled fast path again.
1740 * 2 - we copy the user entries to a local buffer here outside of the
1741 * local and allow ourselves to wait upon any rendering before
1744 * 3 - we already have a local copy of the relocation entries, but
1745 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1748 err = eb_prefault_relocations(eb);
1749 } else if (!have_copy) {
1750 err = eb_copy_relocations(eb);
1751 have_copy = err == 0;
1758 err = eb_reinit_userptr(eb);
1760 i915_gem_ww_ctx_init(&eb->ww, true);
1764 /* reacquire the objects */
1766 err = eb_pin_engine(eb, false);
1770 err = eb_validate_vmas(eb);
1774 GEM_BUG_ON(!eb->batches[0]);
1776 list_for_each_entry(ev, &eb->relocs, reloc_link) {
1778 err = eb_relocate_vma(eb, ev);
1782 err = eb_relocate_vma_slow(eb, ev);
1788 if (err == -EDEADLK)
1791 if (err && !have_copy)
1797 /* as last step, parse the command buffer */
1803 * Leave the user relocations as are, this is the painfully slow path,
1804 * and we want to avoid the complication of dropping the lock whilst
1805 * having buffers reserved in the aperture and so causing spurious
1806 * ENOSPC for random operations.
1810 if (err == -EDEADLK) {
1811 eb_release_vmas(eb, false);
1812 err = i915_gem_ww_ctx_backoff(&eb->ww);
1814 goto repeat_validate;
1822 const unsigned int count = eb->buffer_count;
1825 for (i = 0; i < count; i++) {
1826 const struct drm_i915_gem_exec_object2 *entry =
1828 struct drm_i915_gem_relocation_entry *relocs;
1830 if (!entry->relocation_count)
1833 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1841 static int eb_relocate_parse(struct i915_execbuffer *eb)
1844 bool throttle = true;
1847 err = eb_pin_engine(eb, throttle);
1849 if (err != -EDEADLK)
1855 /* only throttle once, even if we didn't need to throttle */
1858 err = eb_validate_vmas(eb);
1864 /* The objects are in their final locations, apply the relocations. */
1865 if (eb->args->flags & __EXEC_HAS_RELOC) {
1868 list_for_each_entry(ev, &eb->relocs, reloc_link) {
1869 err = eb_relocate_vma(eb, ev);
1874 if (err == -EDEADLK)
1884 if (err == -EDEADLK) {
1885 eb_release_vmas(eb, false);
1886 err = i915_gem_ww_ctx_backoff(&eb->ww);
1894 err = eb_relocate_parse_slow(eb);
1897 * If the user expects the execobject.offset and
1898 * reloc.presumed_offset to be an exact match,
1899 * as for using NO_RELOC, then we cannot update
1900 * the execobject.offset until we have completed
1903 eb->args->flags &= ~__EXEC_HAS_RELOC;
1909 * Using two helper loops for the order of which requests / batches are created
1910 * and added the to backend. Requests are created in order from the parent to
1911 * the last child. Requests are added in the reverse order, from the last child
1912 * to parent. This is done for locking reasons as the timeline lock is acquired
1913 * during request creation and released when the request is added to the
1914 * backend. To make lockdep happy (see intel_context_timeline_lock) this must be
1917 #define for_each_batch_create_order(_eb, _i) \
1918 for ((_i) = 0; (_i) < (_eb)->num_batches; ++(_i))
1919 #define for_each_batch_add_order(_eb, _i) \
1920 BUILD_BUG_ON(!typecheck(int, _i)); \
1921 for ((_i) = (_eb)->num_batches - 1; (_i) >= 0; --(_i))
1923 static struct i915_request *
1924 eb_find_first_request_added(struct i915_execbuffer *eb)
1928 for_each_batch_add_order(eb, i)
1929 if (eb->requests[i])
1930 return eb->requests[i];
1932 GEM_BUG_ON("Request not found");
1937 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1939 /* Stage with GFP_KERNEL allocations before we enter the signaling critical path */
1940 static void eb_capture_stage(struct i915_execbuffer *eb)
1942 const unsigned int count = eb->buffer_count;
1943 unsigned int i = count, j;
1944 struct i915_vma_snapshot *vsnap;
1947 struct eb_vma *ev = &eb->vma[i];
1948 struct i915_vma *vma = ev->vma;
1949 unsigned int flags = ev->flags;
1951 if (!(flags & EXEC_OBJECT_CAPTURE))
1954 vsnap = i915_vma_snapshot_alloc(GFP_KERNEL);
1958 i915_vma_snapshot_init(vsnap, vma, "user");
1959 for_each_batch_create_order(eb, j) {
1960 struct i915_capture_list *capture;
1962 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1966 capture->next = eb->capture_lists[j];
1967 capture->vma_snapshot = i915_vma_snapshot_get(vsnap);
1968 eb->capture_lists[j] = capture;
1970 i915_vma_snapshot_put(vsnap);
1974 /* Commit once we're in the critical path */
1975 static void eb_capture_commit(struct i915_execbuffer *eb)
1979 for_each_batch_create_order(eb, j) {
1980 struct i915_request *rq = eb->requests[j];
1985 rq->capture_list = eb->capture_lists[j];
1986 eb->capture_lists[j] = NULL;
1991 * Release anything that didn't get committed due to errors.
1992 * The capture_list will otherwise be freed at request retire.
1994 static void eb_capture_release(struct i915_execbuffer *eb)
1998 for_each_batch_create_order(eb, j) {
1999 if (eb->capture_lists[j]) {
2000 i915_request_free_capture_list(eb->capture_lists[j]);
2001 eb->capture_lists[j] = NULL;
2006 static void eb_capture_list_clear(struct i915_execbuffer *eb)
2008 memset(eb->capture_lists, 0, sizeof(eb->capture_lists));
2013 static void eb_capture_stage(struct i915_execbuffer *eb)
2017 static void eb_capture_commit(struct i915_execbuffer *eb)
2021 static void eb_capture_release(struct i915_execbuffer *eb)
2025 static void eb_capture_list_clear(struct i915_execbuffer *eb)
2031 static int eb_move_to_gpu(struct i915_execbuffer *eb)
2033 const unsigned int count = eb->buffer_count;
2034 unsigned int i = count;
2038 struct eb_vma *ev = &eb->vma[i];
2039 struct i915_vma *vma = ev->vma;
2040 unsigned int flags = ev->flags;
2041 struct drm_i915_gem_object *obj = vma->obj;
2043 assert_vma_held(vma);
2046 * If the GPU is not _reading_ through the CPU cache, we need
2047 * to make sure that any writes (both previous GPU writes from
2048 * before a change in snooping levels and normal CPU writes)
2049 * caught in that cache are flushed to main memory.
2052 * obj->cache_dirty &&
2053 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
2054 * but gcc's optimiser doesn't handle that as well and emits
2055 * two jumps instead of one. Maybe one day...
2057 * FIXME: There is also sync flushing in set_pages(), which
2058 * serves a different purpose(some of the time at least).
2060 * We should consider:
2062 * 1. Rip out the async flush code.
2064 * 2. Or make the sync flushing use the async clflush path
2065 * using mandatory fences underneath. Currently the below
2066 * async flush happens after we bind the object.
2068 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
2069 if (i915_gem_clflush_object(obj, 0))
2070 flags &= ~EXEC_OBJECT_ASYNC;
2073 /* We only need to await on the first request */
2074 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
2075 err = i915_request_await_object
2076 (eb_find_first_request_added(eb), obj,
2077 flags & EXEC_OBJECT_WRITE);
2080 for_each_batch_add_order(eb, j) {
2083 if (!eb->requests[j])
2086 err = _i915_vma_move_to_active(vma, eb->requests[j],
2088 eb->composite_fence ?
2089 eb->composite_fence :
2090 &eb->requests[j]->fence,
2091 flags | __EXEC_OBJECT_NO_RESERVE);
2095 #ifdef CONFIG_MMU_NOTIFIER
2096 if (!err && (eb->args->flags & __EXEC_USERPTR_USED)) {
2097 read_lock(&eb->i915->mm.notifier_lock);
2100 * count is always at least 1, otherwise __EXEC_USERPTR_USED
2101 * could not have been set
2103 for (i = 0; i < count; i++) {
2104 struct eb_vma *ev = &eb->vma[i];
2105 struct drm_i915_gem_object *obj = ev->vma->obj;
2107 if (!i915_gem_object_is_userptr(obj))
2110 err = i915_gem_object_userptr_submit_done(obj);
2115 read_unlock(&eb->i915->mm.notifier_lock);
2122 /* Unconditionally flush any chipset caches (for streaming writes). */
2123 intel_gt_chipset_flush(eb->gt);
2124 eb_capture_commit(eb);
2129 for_each_batch_create_order(eb, j) {
2130 if (!eb->requests[j])
2133 i915_request_set_error_once(eb->requests[j], err);
2138 static int i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
2140 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
2143 /* Kernel clipping was a DRI1 misfeature */
2144 if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
2145 I915_EXEC_USE_EXTENSIONS))) {
2146 if (exec->num_cliprects || exec->cliprects_ptr)
2150 if (exec->DR4 == 0xffffffff) {
2151 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
2154 if (exec->DR1 || exec->DR4)
2157 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
2163 static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
2168 if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
2169 drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
2173 cs = intel_ring_begin(rq, 4 * 2 + 2);
2177 *cs++ = MI_LOAD_REGISTER_IMM(4);
2178 for (i = 0; i < 4; i++) {
2179 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
2183 intel_ring_advance(rq, cs);
2188 static struct i915_vma *
2189 shadow_batch_pin(struct i915_execbuffer *eb,
2190 struct drm_i915_gem_object *obj,
2191 struct i915_address_space *vm,
2194 struct i915_vma *vma;
2197 vma = i915_vma_instance(obj, vm, NULL);
2201 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags);
2203 return ERR_PTR(err);
2208 static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma)
2211 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2212 * batch" bit. Hence we need to pin secure batches into the global gtt.
2213 * hsw should have this fixed, but bdw mucks it up again. */
2214 if (eb->batch_flags & I915_DISPATCH_SECURE)
2215 return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, 0);
2220 static int eb_parse(struct i915_execbuffer *eb)
2222 struct drm_i915_private *i915 = eb->i915;
2223 struct intel_gt_buffer_pool_node *pool = eb->batch_pool;
2224 struct i915_vma *shadow, *trampoline, *batch;
2228 if (!eb_use_cmdparser(eb)) {
2229 batch = eb_dispatch_secure(eb, eb->batches[0]->vma);
2231 return PTR_ERR(batch);
2236 if (intel_context_is_parallel(eb->context))
2239 len = eb->batch_len[0];
2240 if (!CMDPARSER_USES_GGTT(eb->i915)) {
2242 * ppGTT backed shadow buffers must be mapped RO, to prevent
2243 * post-scan tampering
2245 if (!eb->context->vm->has_read_only) {
2247 "Cannot prevent post-scan tampering without RO capable vm\n");
2251 len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
2253 if (unlikely(len < eb->batch_len[0])) /* last paranoid check of overflow */
2257 pool = intel_gt_get_buffer_pool(eb->gt, len,
2260 return PTR_ERR(pool);
2261 eb->batch_pool = pool;
2264 err = i915_gem_object_lock(pool->obj, &eb->ww);
2268 shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER);
2269 if (IS_ERR(shadow)) {
2270 err = PTR_ERR(shadow);
2273 intel_gt_buffer_pool_mark_used(pool);
2274 i915_gem_object_set_readonly(shadow->obj);
2275 shadow->private = pool;
2278 if (CMDPARSER_USES_GGTT(eb->i915)) {
2279 trampoline = shadow;
2281 shadow = shadow_batch_pin(eb, pool->obj,
2284 if (IS_ERR(shadow)) {
2285 err = PTR_ERR(shadow);
2286 shadow = trampoline;
2289 shadow->private = pool;
2291 eb->batch_flags |= I915_DISPATCH_SECURE;
2294 batch = eb_dispatch_secure(eb, shadow);
2295 if (IS_ERR(batch)) {
2296 err = PTR_ERR(batch);
2297 goto err_trampoline;
2300 err = dma_resv_reserve_shared(shadow->obj->base.resv, 1);
2302 goto err_trampoline;
2304 err = intel_engine_cmd_parser(eb->context->engine,
2305 eb->batches[0]->vma,
2306 eb->batch_start_offset,
2308 shadow, trampoline);
2310 goto err_unpin_batch;
2312 eb->batches[0] = &eb->vma[eb->buffer_count++];
2313 eb->batches[0]->vma = i915_vma_get(shadow);
2314 eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN;
2316 eb->trampoline = trampoline;
2317 eb->batch_start_offset = 0;
2321 if (intel_context_is_parallel(eb->context))
2324 eb->batches[0] = &eb->vma[eb->buffer_count++];
2325 eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN;
2326 eb->batches[0]->vma = i915_vma_get(batch);
2332 i915_vma_unpin(batch);
2335 i915_vma_unpin(trampoline);
2337 i915_vma_unpin(shadow);
2342 static int eb_request_submit(struct i915_execbuffer *eb,
2343 struct i915_request *rq,
2344 struct i915_vma *batch,
2349 if (intel_context_nopreempt(rq->context))
2350 __set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags);
2352 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2353 err = i915_reset_gen7_sol_offsets(rq);
2359 * After we completed waiting for other engines (using HW semaphores)
2360 * then we can signal that this request/batch is ready to run. This
2361 * allows us to determine if the batch is still waiting on the GPU
2362 * or actually running by checking the breadcrumb.
2364 if (rq->context->engine->emit_init_breadcrumb) {
2365 err = rq->context->engine->emit_init_breadcrumb(rq);
2370 err = rq->context->engine->emit_bb_start(rq,
2372 eb->batch_start_offset,
2378 if (eb->trampoline) {
2379 GEM_BUG_ON(intel_context_is_parallel(rq->context));
2380 GEM_BUG_ON(eb->batch_start_offset);
2381 err = rq->context->engine->emit_bb_start(rq,
2382 eb->trampoline->node.start +
2391 static int eb_submit(struct i915_execbuffer *eb)
2396 err = eb_move_to_gpu(eb);
2398 for_each_batch_create_order(eb, i) {
2399 if (!eb->requests[i])
2402 trace_i915_request_queue(eb->requests[i], eb->batch_flags);
2404 err = eb_request_submit(eb, eb->requests[i],
2405 eb->batches[i]->vma,
2412 static int num_vcs_engines(struct drm_i915_private *i915)
2414 return hweight_long(VDBOX_MASK(to_gt(i915)));
2418 * Find one BSD ring to dispatch the corresponding BSD command.
2419 * The engine index is returned.
2422 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2423 struct drm_file *file)
2425 struct drm_i915_file_private *file_priv = file->driver_priv;
2427 /* Check whether the file_priv has already selected one ring. */
2428 if ((int)file_priv->bsd_engine < 0)
2429 file_priv->bsd_engine =
2430 get_random_int() % num_vcs_engines(dev_priv);
2432 return file_priv->bsd_engine;
2435 static const enum intel_engine_id user_ring_map[] = {
2436 [I915_EXEC_DEFAULT] = RCS0,
2437 [I915_EXEC_RENDER] = RCS0,
2438 [I915_EXEC_BLT] = BCS0,
2439 [I915_EXEC_BSD] = VCS0,
2440 [I915_EXEC_VEBOX] = VECS0
2443 static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce)
2445 struct intel_ring *ring = ce->ring;
2446 struct intel_timeline *tl = ce->timeline;
2447 struct i915_request *rq;
2450 * Completely unscientific finger-in-the-air estimates for suitable
2451 * maximum user request size (to avoid blocking) and then backoff.
2453 if (intel_ring_update_space(ring) >= PAGE_SIZE)
2457 * Find a request that after waiting upon, there will be at least half
2458 * the ring available. The hysteresis allows us to compete for the
2459 * shared ring and should mean that we sleep less often prior to
2460 * claiming our resources, but not so long that the ring completely
2461 * drains before we can submit our next request.
2463 list_for_each_entry(rq, &tl->requests, link) {
2464 if (rq->ring != ring)
2467 if (__intel_ring_space(rq->postfix,
2468 ring->emit, ring->size) > ring->size / 2)
2471 if (&rq->link == &tl->requests)
2472 return NULL; /* weird, we will check again later for real */
2474 return i915_request_get(rq);
2477 static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce,
2480 struct intel_timeline *tl;
2481 struct i915_request *rq = NULL;
2484 * Take a local wakeref for preparing to dispatch the execbuf as
2485 * we expect to access the hardware fairly frequently in the
2486 * process, and require the engine to be kept awake between accesses.
2487 * Upon dispatch, we acquire another prolonged wakeref that we hold
2488 * until the timeline is idle, which in turn releases the wakeref
2489 * taken on the engine, and the parent device.
2491 tl = intel_context_timeline_lock(ce);
2495 intel_context_enter(ce);
2497 rq = eb_throttle(eb, ce);
2498 intel_context_timeline_unlock(tl);
2501 bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
2502 long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
2504 if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
2506 i915_request_put(rq);
2508 tl = intel_context_timeline_lock(ce);
2509 intel_context_exit(ce);
2510 intel_context_timeline_unlock(tl);
2513 return -EWOULDBLOCK;
2517 i915_request_put(rq);
2523 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
2525 struct intel_context *ce = eb->context, *child;
2529 GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
2531 if (unlikely(intel_context_is_banned(ce)))
2535 * Pinning the contexts may generate requests in order to acquire
2536 * GGTT space, so do this first before we reserve a seqno for
2539 err = intel_context_pin_ww(ce, &eb->ww);
2542 for_each_child(ce, child) {
2543 err = intel_context_pin_ww(child, &eb->ww);
2544 GEM_BUG_ON(err); /* perma-pinned should incr a counter */
2547 for_each_child(ce, child) {
2548 err = eb_pin_timeline(eb, child, throttle);
2553 err = eb_pin_timeline(eb, ce, throttle);
2557 eb->args->flags |= __EXEC_ENGINE_PINNED;
2561 for_each_child(ce, child) {
2563 mutex_lock(&child->timeline->mutex);
2564 intel_context_exit(child);
2565 mutex_unlock(&child->timeline->mutex);
2568 for_each_child(ce, child)
2569 intel_context_unpin(child);
2570 intel_context_unpin(ce);
2574 static void eb_unpin_engine(struct i915_execbuffer *eb)
2576 struct intel_context *ce = eb->context, *child;
2578 if (!(eb->args->flags & __EXEC_ENGINE_PINNED))
2581 eb->args->flags &= ~__EXEC_ENGINE_PINNED;
2583 for_each_child(ce, child) {
2584 mutex_lock(&child->timeline->mutex);
2585 intel_context_exit(child);
2586 mutex_unlock(&child->timeline->mutex);
2588 intel_context_unpin(child);
2591 mutex_lock(&ce->timeline->mutex);
2592 intel_context_exit(ce);
2593 mutex_unlock(&ce->timeline->mutex);
2595 intel_context_unpin(ce);
2599 eb_select_legacy_ring(struct i915_execbuffer *eb)
2601 struct drm_i915_private *i915 = eb->i915;
2602 struct drm_i915_gem_execbuffer2 *args = eb->args;
2603 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2605 if (user_ring_id != I915_EXEC_BSD &&
2606 (args->flags & I915_EXEC_BSD_MASK)) {
2608 "execbuf with non bsd ring but with invalid "
2609 "bsd dispatch flags: %d\n", (int)(args->flags));
2613 if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) {
2614 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2616 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2617 bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
2618 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2619 bsd_idx <= I915_EXEC_BSD_RING2) {
2620 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2624 "execbuf with unknown bsd ring: %u\n",
2629 return _VCS(bsd_idx);
2632 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2633 drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n",
2638 return user_ring_map[user_ring_id];
2642 eb_select_engine(struct i915_execbuffer *eb)
2644 struct intel_context *ce, *child;
2648 if (i915_gem_context_user_engines(eb->gem_context))
2649 idx = eb->args->flags & I915_EXEC_RING_MASK;
2651 idx = eb_select_legacy_ring(eb);
2653 ce = i915_gem_context_get_engine(eb->gem_context, idx);
2657 if (intel_context_is_parallel(ce)) {
2658 if (eb->buffer_count < ce->parallel.number_children + 1) {
2659 intel_context_put(ce);
2662 if (eb->batch_start_offset || eb->args->batch_len) {
2663 intel_context_put(ce);
2667 eb->num_batches = ce->parallel.number_children + 1;
2669 for_each_child(ce, child)
2670 intel_context_get(child);
2671 intel_gt_pm_get(ce->engine->gt);
2673 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
2674 err = intel_context_alloc_state(ce);
2678 for_each_child(ce, child) {
2679 if (!test_bit(CONTEXT_ALLOC_BIT, &child->flags)) {
2680 err = intel_context_alloc_state(child);
2687 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2688 * EIO if the GPU is already wedged.
2690 err = intel_gt_terminally_wedged(ce->engine->gt);
2695 eb->gt = ce->engine->gt;
2698 * Make sure engine pool stays alive even if we call intel_context_put
2699 * during ww handling. The pool is destroyed when last pm reference
2700 * is dropped, which breaks our -EDEADLK handling.
2705 intel_gt_pm_put(ce->engine->gt);
2706 for_each_child(ce, child)
2707 intel_context_put(child);
2708 intel_context_put(ce);
2713 eb_put_engine(struct i915_execbuffer *eb)
2715 struct intel_context *child;
2717 intel_gt_pm_put(eb->gt);
2718 for_each_child(eb->context, child)
2719 intel_context_put(child);
2720 intel_context_put(eb->context);
2724 __free_fence_array(struct eb_fence *fences, unsigned int n)
2727 drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
2728 dma_fence_put(fences[n].dma_fence);
2729 dma_fence_chain_free(fences[n].chain_fence);
2735 add_timeline_fence_array(struct i915_execbuffer *eb,
2736 const struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences)
2738 struct drm_i915_gem_exec_fence __user *user_fences;
2739 u64 __user *user_values;
2744 nfences = timeline_fences->fence_count;
2748 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2749 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2750 if (nfences > min_t(unsigned long,
2751 ULONG_MAX / sizeof(*user_fences),
2752 SIZE_MAX / sizeof(*f)) - eb->num_fences)
2755 user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
2756 if (!access_ok(user_fences, nfences * sizeof(*user_fences)))
2759 user_values = u64_to_user_ptr(timeline_fences->values_ptr);
2760 if (!access_ok(user_values, nfences * sizeof(*user_values)))
2763 f = krealloc(eb->fences,
2764 (eb->num_fences + nfences) * sizeof(*f),
2765 __GFP_NOWARN | GFP_KERNEL);
2770 f += eb->num_fences;
2772 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2773 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2776 struct drm_i915_gem_exec_fence user_fence;
2777 struct drm_syncobj *syncobj;
2778 struct dma_fence *fence = NULL;
2781 if (__copy_from_user(&user_fence,
2783 sizeof(user_fence)))
2786 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2789 if (__get_user(point, user_values++))
2792 syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2794 DRM_DEBUG("Invalid syncobj handle provided\n");
2798 fence = drm_syncobj_fence_get(syncobj);
2800 if (!fence && user_fence.flags &&
2801 !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2802 DRM_DEBUG("Syncobj handle has no fence\n");
2803 drm_syncobj_put(syncobj);
2808 err = dma_fence_chain_find_seqno(&fence, point);
2810 if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2811 DRM_DEBUG("Syncobj handle missing requested point %llu\n", point);
2812 dma_fence_put(fence);
2813 drm_syncobj_put(syncobj);
2818 * A point might have been signaled already and
2819 * garbage collected from the timeline. In this case
2820 * just ignore the point and carry on.
2822 if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2823 drm_syncobj_put(syncobj);
2828 * For timeline syncobjs we need to preallocate chains for
2831 if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
2833 * Waiting and signaling the same point (when point !=
2834 * 0) would break the timeline.
2836 if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2837 DRM_DEBUG("Trying to wait & signal the same timeline point.\n");
2838 dma_fence_put(fence);
2839 drm_syncobj_put(syncobj);
2843 f->chain_fence = dma_fence_chain_alloc();
2844 if (!f->chain_fence) {
2845 drm_syncobj_put(syncobj);
2846 dma_fence_put(fence);
2850 f->chain_fence = NULL;
2853 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2854 f->dma_fence = fence;
2863 static int add_fence_array(struct i915_execbuffer *eb)
2865 struct drm_i915_gem_execbuffer2 *args = eb->args;
2866 struct drm_i915_gem_exec_fence __user *user;
2867 unsigned long num_fences = args->num_cliprects;
2870 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2876 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2877 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2878 if (num_fences > min_t(unsigned long,
2879 ULONG_MAX / sizeof(*user),
2880 SIZE_MAX / sizeof(*f) - eb->num_fences))
2883 user = u64_to_user_ptr(args->cliprects_ptr);
2884 if (!access_ok(user, num_fences * sizeof(*user)))
2887 f = krealloc(eb->fences,
2888 (eb->num_fences + num_fences) * sizeof(*f),
2889 __GFP_NOWARN | GFP_KERNEL);
2894 f += eb->num_fences;
2895 while (num_fences--) {
2896 struct drm_i915_gem_exec_fence user_fence;
2897 struct drm_syncobj *syncobj;
2898 struct dma_fence *fence = NULL;
2900 if (__copy_from_user(&user_fence, user++, sizeof(user_fence)))
2903 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2906 syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2908 DRM_DEBUG("Invalid syncobj handle provided\n");
2912 if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2913 fence = drm_syncobj_fence_get(syncobj);
2915 DRM_DEBUG("Syncobj handle has no fence\n");
2916 drm_syncobj_put(syncobj);
2921 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2922 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2924 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2925 f->dma_fence = fence;
2927 f->chain_fence = NULL;
2935 static void put_fence_array(struct eb_fence *fences, int num_fences)
2938 __free_fence_array(fences, num_fences);
2942 await_fence_array(struct i915_execbuffer *eb,
2943 struct i915_request *rq)
2948 for (n = 0; n < eb->num_fences; n++) {
2949 struct drm_syncobj *syncobj;
2952 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
2954 if (!eb->fences[n].dma_fence)
2957 err = i915_request_await_dma_fence(rq, eb->fences[n].dma_fence);
2965 static void signal_fence_array(const struct i915_execbuffer *eb,
2966 struct dma_fence * const fence)
2970 for (n = 0; n < eb->num_fences; n++) {
2971 struct drm_syncobj *syncobj;
2974 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
2975 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2978 if (eb->fences[n].chain_fence) {
2979 drm_syncobj_add_point(syncobj,
2980 eb->fences[n].chain_fence,
2982 eb->fences[n].value);
2984 * The chain's ownership is transferred to the
2987 eb->fences[n].chain_fence = NULL;
2989 drm_syncobj_replace_fence(syncobj, fence);
2995 parse_timeline_fences(struct i915_user_extension __user *ext, void *data)
2997 struct i915_execbuffer *eb = data;
2998 struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
3000 if (copy_from_user(&timeline_fences, ext, sizeof(timeline_fences)))
3003 return add_timeline_fence_array(eb, &timeline_fences);
3006 static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
3008 struct i915_request *rq, *rn;
3010 list_for_each_entry_safe(rq, rn, &tl->requests, link)
3011 if (rq == end || !i915_request_retire(rq))
3015 static int eb_request_add(struct i915_execbuffer *eb, struct i915_request *rq,
3016 int err, bool last_parallel)
3018 struct intel_timeline * const tl = i915_request_timeline(rq);
3019 struct i915_sched_attr attr = {};
3020 struct i915_request *prev;
3022 lockdep_assert_held(&tl->mutex);
3023 lockdep_unpin_lock(&tl->mutex, rq->cookie);
3025 trace_i915_request_add(rq);
3027 prev = __i915_request_commit(rq);
3029 /* Check that the context wasn't destroyed before submission */
3030 if (likely(!intel_context_is_closed(eb->context))) {
3031 attr = eb->gem_context->sched;
3033 /* Serialise with context_close via the add_to_timeline */
3034 i915_request_set_error_once(rq, -ENOENT);
3035 __i915_request_skip(rq);
3036 err = -ENOENT; /* override any transient errors */
3039 if (intel_context_is_parallel(eb->context)) {
3041 __i915_request_skip(rq);
3042 set_bit(I915_FENCE_FLAG_SKIP_PARALLEL,
3046 set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL,
3050 __i915_request_queue(rq, &attr);
3052 /* Try to clean up the client's timeline after submitting the request */
3054 retire_requests(tl, prev);
3056 mutex_unlock(&tl->mutex);
3061 static int eb_requests_add(struct i915_execbuffer *eb, int err)
3066 * We iterate in reverse order of creation to release timeline mutexes in
3069 for_each_batch_add_order(eb, i) {
3070 struct i915_request *rq = eb->requests[i];
3074 err |= eb_request_add(eb, rq, err, i == 0);
3080 static const i915_user_extension_fn execbuf_extensions[] = {
3081 [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
3085 parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
3086 struct i915_execbuffer *eb)
3088 if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
3091 /* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
3092 * have another flag also using it at the same time.
3094 if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
3097 if (args->num_cliprects != 0)
3100 return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
3102 ARRAY_SIZE(execbuf_extensions),
3106 static void eb_requests_get(struct i915_execbuffer *eb)
3110 for_each_batch_create_order(eb, i) {
3111 if (!eb->requests[i])
3114 i915_request_get(eb->requests[i]);
3118 static void eb_requests_put(struct i915_execbuffer *eb)
3122 for_each_batch_create_order(eb, i) {
3123 if (!eb->requests[i])
3126 i915_request_put(eb->requests[i]);
3130 static struct sync_file *
3131 eb_composite_fence_create(struct i915_execbuffer *eb, int out_fence_fd)
3133 struct sync_file *out_fence = NULL;
3134 struct dma_fence_array *fence_array;
3135 struct dma_fence **fences;
3138 GEM_BUG_ON(!intel_context_is_parent(eb->context));
3140 fences = kmalloc_array(eb->num_batches, sizeof(*fences), GFP_KERNEL);
3142 return ERR_PTR(-ENOMEM);
3144 for_each_batch_create_order(eb, i) {
3145 fences[i] = &eb->requests[i]->fence;
3146 __set_bit(I915_FENCE_FLAG_COMPOSITE,
3147 &eb->requests[i]->fence.flags);
3150 fence_array = dma_fence_array_create(eb->num_batches,
3152 eb->context->parallel.fence_context,
3153 eb->context->parallel.seqno++,
3157 return ERR_PTR(-ENOMEM);
3160 /* Move ownership to the dma_fence_array created above */
3161 for_each_batch_create_order(eb, i)
3162 dma_fence_get(fences[i]);
3164 if (out_fence_fd != -1) {
3165 out_fence = sync_file_create(&fence_array->base);
3166 /* sync_file now owns fence_arry, drop creation ref */
3167 dma_fence_put(&fence_array->base);
3169 return ERR_PTR(-ENOMEM);
3172 eb->composite_fence = &fence_array->base;
3177 static struct sync_file *
3178 eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq,
3179 struct dma_fence *in_fence, int out_fence_fd)
3181 struct sync_file *out_fence = NULL;
3184 if (unlikely(eb->gem_context->syncobj)) {
3185 struct dma_fence *fence;
3187 fence = drm_syncobj_fence_get(eb->gem_context->syncobj);
3188 err = i915_request_await_dma_fence(rq, fence);
3189 dma_fence_put(fence);
3191 return ERR_PTR(err);
3195 if (eb->args->flags & I915_EXEC_FENCE_SUBMIT)
3196 err = i915_request_await_execution(rq, in_fence);
3198 err = i915_request_await_dma_fence(rq, in_fence);
3200 return ERR_PTR(err);
3204 err = await_fence_array(eb, rq);
3206 return ERR_PTR(err);
3209 if (intel_context_is_parallel(eb->context)) {
3210 out_fence = eb_composite_fence_create(eb, out_fence_fd);
3211 if (IS_ERR(out_fence))
3212 return ERR_PTR(-ENOMEM);
3213 } else if (out_fence_fd != -1) {
3214 out_fence = sync_file_create(&rq->fence);
3216 return ERR_PTR(-ENOMEM);
3222 static struct intel_context *
3223 eb_find_context(struct i915_execbuffer *eb, unsigned int context_number)
3225 struct intel_context *child;
3227 if (likely(context_number == 0))
3230 for_each_child(eb->context, child)
3231 if (!--context_number)
3234 GEM_BUG_ON("Context not found");
3239 static struct sync_file *
3240 eb_requests_create(struct i915_execbuffer *eb, struct dma_fence *in_fence,
3243 struct sync_file *out_fence = NULL;
3246 for_each_batch_create_order(eb, i) {
3247 /* Allocate a request for this batch buffer nice and early. */
3248 eb->requests[i] = i915_request_create(eb_find_context(eb, i));
3249 if (IS_ERR(eb->requests[i])) {
3250 out_fence = ERR_CAST(eb->requests[i]);
3251 eb->requests[i] = NULL;
3256 * Only the first request added (committed to backend) has to
3257 * take the in fences into account as all subsequent requests
3258 * will have fences inserted inbetween them.
3260 if (i + 1 == eb->num_batches) {
3261 out_fence = eb_fences_add(eb, eb->requests[i],
3262 in_fence, out_fence_fd);
3263 if (IS_ERR(out_fence))
3268 * Not really on stack, but we don't want to call
3269 * kfree on the batch_snapshot when we put it, so use the
3270 * _onstack interface.
3272 if (eb->batches[i]->vma)
3273 i915_vma_snapshot_init_onstack(&eb->requests[i]->batch_snapshot,
3274 eb->batches[i]->vma,
3276 if (eb->batch_pool) {
3277 GEM_BUG_ON(intel_context_is_parallel(eb->context));
3278 intel_gt_buffer_pool_mark_active(eb->batch_pool,
3287 i915_gem_do_execbuffer(struct drm_device *dev,
3288 struct drm_file *file,
3289 struct drm_i915_gem_execbuffer2 *args,
3290 struct drm_i915_gem_exec_object2 *exec)
3292 struct drm_i915_private *i915 = to_i915(dev);
3293 struct i915_execbuffer eb;
3294 struct dma_fence *in_fence = NULL;
3295 struct sync_file *out_fence = NULL;
3296 int out_fence_fd = -1;
3299 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
3300 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
3301 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
3306 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
3307 args->flags |= __EXEC_HAS_RELOC;
3310 eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
3311 eb.vma[0].vma = NULL;
3312 eb.batch_pool = NULL;
3314 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
3315 reloc_cache_init(&eb.reloc_cache, eb.i915);
3317 eb.buffer_count = args->buffer_count;
3318 eb.batch_start_offset = args->batch_start_offset;
3319 eb.trampoline = NULL;
3324 eb_capture_list_clear(&eb);
3326 memset(eb.requests, 0, sizeof(struct i915_request *) *
3327 ARRAY_SIZE(eb.requests));
3328 eb.composite_fence = NULL;
3331 if (args->flags & I915_EXEC_SECURE) {
3332 if (GRAPHICS_VER(i915) >= 11)
3335 /* Return -EPERM to trigger fallback code on old binaries. */
3336 if (!HAS_SECURE_BATCHES(i915))
3339 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
3342 eb.batch_flags |= I915_DISPATCH_SECURE;
3344 if (args->flags & I915_EXEC_IS_PINNED)
3345 eb.batch_flags |= I915_DISPATCH_PINNED;
3347 err = parse_execbuf2_extensions(args, &eb);
3351 err = add_fence_array(&eb);
3355 #define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT)
3356 if (args->flags & IN_FENCES) {
3357 if ((args->flags & IN_FENCES) == IN_FENCES)
3360 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
3368 if (args->flags & I915_EXEC_FENCE_OUT) {
3369 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3370 if (out_fence_fd < 0) {
3376 err = eb_create(&eb);
3380 GEM_BUG_ON(!eb.lut_size);
3382 err = eb_select_context(&eb);
3386 err = eb_select_engine(&eb);
3390 err = eb_lookup_vmas(&eb);
3392 eb_release_vmas(&eb, true);
3396 i915_gem_ww_ctx_init(&eb.ww, true);
3398 err = eb_relocate_parse(&eb);
3401 * If the user expects the execobject.offset and
3402 * reloc.presumed_offset to be an exact match,
3403 * as for using NO_RELOC, then we cannot update
3404 * the execobject.offset until we have completed
3407 args->flags &= ~__EXEC_HAS_RELOC;
3411 ww_acquire_done(&eb.ww.ctx);
3412 eb_capture_stage(&eb);
3414 out_fence = eb_requests_create(&eb, in_fence, out_fence_fd);
3415 if (IS_ERR(out_fence)) {
3416 err = PTR_ERR(out_fence);
3424 err = eb_submit(&eb);
3427 eb_requests_get(&eb);
3428 err = eb_requests_add(&eb, err);
3431 signal_fence_array(&eb, eb.composite_fence ?
3432 eb.composite_fence :
3433 &eb.requests[0]->fence);
3437 fd_install(out_fence_fd, out_fence->file);
3438 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
3439 args->rsvd2 |= (u64)out_fence_fd << 32;
3442 fput(out_fence->file);
3446 if (unlikely(eb.gem_context->syncobj)) {
3447 drm_syncobj_replace_fence(eb.gem_context->syncobj,
3448 eb.composite_fence ?
3449 eb.composite_fence :
3450 &eb.requests[0]->fence);
3453 if (!out_fence && eb.composite_fence)
3454 dma_fence_put(eb.composite_fence);
3456 eb_requests_put(&eb);
3459 eb_release_vmas(&eb, true);
3461 i915_vma_unpin(eb.trampoline);
3462 WARN_ON(err == -EDEADLK);
3463 i915_gem_ww_ctx_fini(&eb.ww);
3466 intel_gt_buffer_pool_put(eb.batch_pool);
3470 i915_gem_context_put(eb.gem_context);
3474 if (out_fence_fd != -1)
3475 put_unused_fd(out_fence_fd);
3477 dma_fence_put(in_fence);
3479 put_fence_array(eb.fences, eb.num_fences);
3483 static size_t eb_element_size(void)
3485 return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma);
3488 static bool check_buffer_count(size_t count)
3490 const size_t sz = eb_element_size();
3493 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
3494 * array size (see eb_create()). Otherwise, we can accept an array as
3495 * large as can be addressed (though use large arrays at your peril)!
3498 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
3502 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
3503 struct drm_file *file)
3505 struct drm_i915_private *i915 = to_i915(dev);
3506 struct drm_i915_gem_execbuffer2 *args = data;
3507 struct drm_i915_gem_exec_object2 *exec2_list;
3508 const size_t count = args->buffer_count;
3511 if (!check_buffer_count(count)) {
3512 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3516 err = i915_gem_check_execbuffer(args);
3520 /* Allocate extra slots for use by the command parser */
3521 exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3522 __GFP_NOWARN | GFP_KERNEL);
3523 if (exec2_list == NULL) {
3524 drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n",
3528 if (copy_from_user(exec2_list,
3529 u64_to_user_ptr(args->buffers_ptr),
3530 sizeof(*exec2_list) * count)) {
3531 drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count);
3536 err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
3539 * Now that we have begun execution of the batchbuffer, we ignore
3540 * any new error after this point. Also given that we have already
3541 * updated the associated relocations, we try to write out the current
3542 * object locations irrespective of any error.
3544 if (args->flags & __EXEC_HAS_RELOC) {
3545 struct drm_i915_gem_exec_object2 __user *user_exec_list =
3546 u64_to_user_ptr(args->buffers_ptr);
3549 /* Copy the new buffer offsets back to the user's exec list. */
3551 * Note: count * sizeof(*user_exec_list) does not overflow,
3552 * because we checked 'count' in check_buffer_count().
3554 * And this range already got effectively checked earlier
3555 * when we did the "copy_from_user()" above.
3557 if (!user_write_access_begin(user_exec_list,
3558 count * sizeof(*user_exec_list)))
3561 for (i = 0; i < args->buffer_count; i++) {
3562 if (!(exec2_list[i].offset & UPDATE))
3565 exec2_list[i].offset =
3566 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3567 unsafe_put_user(exec2_list[i].offset,
3568 &user_exec_list[i].offset,
3572 user_write_access_end();
3576 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;