2 * SPDX-License-Identifier: MIT
4 * Copyright © 2014-2016 Intel Corporation
7 #include "display/intel_display.h"
8 #include "gt/intel_gt.h"
11 #include "i915_gem_clflush.h"
12 #include "i915_gem_domain.h"
13 #include "i915_gem_gtt.h"
14 #include "i915_gem_ioctls.h"
15 #include "i915_gem_lmem.h"
16 #include "i915_gem_mman.h"
17 #include "i915_gem_object.h"
18 #include "i915_gem_object_frontbuffer.h"
21 #define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */
23 static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
25 struct drm_i915_private *i915 = to_i915(obj->base.dev);
31 * For objects created by userspace through GEM_CREATE with pat_index
32 * set by set_pat extension, i915_gem_object_has_cache_level() will
33 * always return true, because the coherency of such object is managed
34 * by userspace. Othereise the call here would fall back to checking
35 * whether the object is un-cached or write-through.
37 return !(i915_gem_object_has_cache_level(obj, I915_CACHE_NONE) ||
38 i915_gem_object_has_cache_level(obj, I915_CACHE_WT));
41 bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
43 struct drm_i915_private *i915 = to_i915(obj->base.dev);
51 if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
54 /* Currently in use by HW (display engine)? Keep flushed. */
55 return i915_gem_object_is_framebuffer(obj);
59 flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
63 assert_object_held(obj);
65 if (!(obj->write_domain & flush_domains))
68 switch (obj->write_domain) {
69 case I915_GEM_DOMAIN_GTT:
70 spin_lock(&obj->vma.lock);
71 for_each_ggtt_vma(vma, obj)
72 i915_vma_flush_writes(vma);
73 spin_unlock(&obj->vma.lock);
75 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
78 case I915_GEM_DOMAIN_WC:
82 case I915_GEM_DOMAIN_CPU:
83 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
86 case I915_GEM_DOMAIN_RENDER:
87 if (gpu_write_needs_clflush(obj))
88 obj->cache_dirty = true;
92 obj->write_domain = 0;
95 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
98 * We manually flush the CPU domain so that we can override and
99 * force the flush for the display, and perform it asyncrhonously.
101 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
102 if (obj->cache_dirty)
103 i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
104 obj->write_domain = 0;
107 void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj)
109 if (!i915_gem_object_is_framebuffer(obj))
112 i915_gem_object_lock(obj, NULL);
113 __i915_gem_object_flush_for_display(obj);
114 i915_gem_object_unlock(obj);
117 void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj)
119 if (i915_gem_object_is_framebuffer(obj))
120 __i915_gem_object_flush_for_display(obj);
124 * i915_gem_object_set_to_wc_domain - Moves a single object to the WC read, and
125 * possibly write domain.
126 * @obj: object to act on
127 * @write: ask for write access or read only
129 * This function returns when the move is complete, including waiting on
133 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
137 assert_object_held(obj);
139 ret = i915_gem_object_wait(obj,
140 I915_WAIT_INTERRUPTIBLE |
141 (write ? I915_WAIT_ALL : 0),
142 MAX_SCHEDULE_TIMEOUT);
146 if (obj->write_domain == I915_GEM_DOMAIN_WC)
149 /* Flush and acquire obj->pages so that we are coherent through
150 * direct access in memory with previous cached writes through
151 * shmemfs and that our cache domain tracking remains valid.
152 * For example, if the obj->filp was moved to swap without us
153 * being notified and releasing the pages, we would mistakenly
154 * continue to assume that the obj remained out of the CPU cached
157 ret = i915_gem_object_pin_pages(obj);
161 flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
163 /* Serialise direct access to this object with the barriers for
164 * coherent writes from the GPU, by effectively invalidating the
165 * WC domain upon first access.
167 if ((obj->read_domains & I915_GEM_DOMAIN_WC) == 0)
170 /* It should now be out of any other write domains, and we can update
171 * the domain values for our changes.
173 GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_WC) != 0);
174 obj->read_domains |= I915_GEM_DOMAIN_WC;
176 obj->read_domains = I915_GEM_DOMAIN_WC;
177 obj->write_domain = I915_GEM_DOMAIN_WC;
178 obj->mm.dirty = true;
181 i915_gem_object_unpin_pages(obj);
186 * i915_gem_object_set_to_gtt_domain - Moves a single object to the GTT read,
187 * and possibly write domain.
188 * @obj: object to act on
189 * @write: ask for write access or read only
191 * This function returns when the move is complete, including waiting on
195 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
199 assert_object_held(obj);
201 ret = i915_gem_object_wait(obj,
202 I915_WAIT_INTERRUPTIBLE |
203 (write ? I915_WAIT_ALL : 0),
204 MAX_SCHEDULE_TIMEOUT);
208 if (obj->write_domain == I915_GEM_DOMAIN_GTT)
211 /* Flush and acquire obj->pages so that we are coherent through
212 * direct access in memory with previous cached writes through
213 * shmemfs and that our cache domain tracking remains valid.
214 * For example, if the obj->filp was moved to swap without us
215 * being notified and releasing the pages, we would mistakenly
216 * continue to assume that the obj remained out of the CPU cached
219 ret = i915_gem_object_pin_pages(obj);
223 flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
225 /* Serialise direct access to this object with the barriers for
226 * coherent writes from the GPU, by effectively invalidating the
227 * GTT domain upon first access.
229 if ((obj->read_domains & I915_GEM_DOMAIN_GTT) == 0)
232 /* It should now be out of any other write domains, and we can update
233 * the domain values for our changes.
235 GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
236 obj->read_domains |= I915_GEM_DOMAIN_GTT;
238 struct i915_vma *vma;
240 obj->read_domains = I915_GEM_DOMAIN_GTT;
241 obj->write_domain = I915_GEM_DOMAIN_GTT;
242 obj->mm.dirty = true;
244 spin_lock(&obj->vma.lock);
245 for_each_ggtt_vma(vma, obj)
246 if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
247 i915_vma_set_ggtt_write(vma);
248 spin_unlock(&obj->vma.lock);
251 i915_gem_object_unpin_pages(obj);
256 * i915_gem_object_set_cache_level - Changes the cache-level of an object across all VMA.
257 * @obj: object to act on
258 * @cache_level: new cache level to set for the object
260 * After this function returns, the object will be in the new cache-level
261 * across all GTT and the contents of the backing storage will be coherent,
262 * with respect to the new cache-level. In order to keep the backing storage
263 * coherent for all users, we only allow a single cache level to be set
264 * globally on the object and prevent it from being changed whilst the
265 * hardware is reading from the object. That is if the object is currently
266 * on the scanout it will be set to uncached (or equivalent display
267 * cache coherency) and all non-MOCS GPU access will also be uncached so
268 * that all direct access to the scanout remains coherent.
270 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
271 enum i915_cache_level cache_level)
276 * For objects created by userspace through GEM_CREATE with pat_index
277 * set by set_pat extension, simply return 0 here without touching
278 * the cache setting, because such objects should have an immutable
279 * cache setting by desgin and always managed by userspace.
281 if (i915_gem_object_has_cache_level(obj, cache_level))
284 ret = i915_gem_object_wait(obj,
285 I915_WAIT_INTERRUPTIBLE |
287 MAX_SCHEDULE_TIMEOUT);
291 /* Always invalidate stale cachelines */
292 i915_gem_object_set_cache_coherency(obj, cache_level);
293 obj->cache_dirty = true;
295 /* The cache-level will be applied when each vma is rebound. */
296 return i915_gem_object_unbind(obj,
297 I915_GEM_OBJECT_UNBIND_ACTIVE |
298 I915_GEM_OBJECT_UNBIND_BARRIER);
301 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
302 struct drm_file *file)
304 struct drm_i915_gem_caching *args = data;
305 struct drm_i915_gem_object *obj;
308 if (IS_DGFX(to_i915(dev)))
312 obj = i915_gem_object_lookup_rcu(file, args->handle);
319 * This ioctl should be disabled for the objects with pat_index
322 if (obj->pat_set_by_user) {
327 if (i915_gem_object_has_cache_level(obj, I915_CACHE_LLC) ||
328 i915_gem_object_has_cache_level(obj, I915_CACHE_L3_LLC))
329 args->caching = I915_CACHING_CACHED;
330 else if (i915_gem_object_has_cache_level(obj, I915_CACHE_WT))
331 args->caching = I915_CACHING_DISPLAY;
333 args->caching = I915_CACHING_NONE;
339 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
340 struct drm_file *file)
342 struct drm_i915_private *i915 = to_i915(dev);
343 struct drm_i915_gem_caching *args = data;
344 struct drm_i915_gem_object *obj;
345 enum i915_cache_level level;
351 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
354 switch (args->caching) {
355 case I915_CACHING_NONE:
356 level = I915_CACHE_NONE;
358 case I915_CACHING_CACHED:
360 * Due to a HW issue on BXT A stepping, GPU stores via a
361 * snooped mapping may leave stale data in a corresponding CPU
362 * cacheline, whereas normally such cachelines would get
365 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
368 level = I915_CACHE_LLC;
370 case I915_CACHING_DISPLAY:
371 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
377 obj = i915_gem_object_lookup(file, args->handle);
382 * This ioctl should be disabled for the objects with pat_index
385 if (obj->pat_set_by_user) {
391 * The caching mode of proxy object is handled by its generator, and
392 * not allowed to be changed by userspace.
394 if (i915_gem_object_is_proxy(obj)) {
396 * Silently allow cached for userptr; the vulkan driver
397 * sets all objects to cached
399 if (!i915_gem_object_is_userptr(obj) ||
400 args->caching != I915_CACHING_CACHED)
406 ret = i915_gem_object_lock_interruptible(obj, NULL);
410 ret = i915_gem_object_set_cache_level(obj, level);
411 i915_gem_object_unlock(obj);
414 i915_gem_object_put(obj);
419 * Prepare buffer for display plane (scanout, cursors, etc). Can be called from
420 * an uninterruptible phase (modesetting) and allows any flushes to be pipelined
421 * (for pageflips). We only flush the caches while preparing the buffer for
422 * display, the callers are responsible for frontbuffer flush.
425 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
426 struct i915_gem_ww_ctx *ww,
428 const struct i915_gtt_view *view,
431 struct drm_i915_private *i915 = to_i915(obj->base.dev);
432 struct i915_vma *vma;
435 /* Frame buffer must be in LMEM */
436 if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj))
437 return ERR_PTR(-EINVAL);
440 * The display engine is not coherent with the LLC cache on gen6. As
441 * a result, we make sure that the pinning that is about to occur is
442 * done with uncached PTEs. This is lowest common denominator for all
445 * However for gen6+, we could do better by using the GFDT bit instead
446 * of uncaching, which would allow us to flush all the LLC-cached data
447 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
449 ret = i915_gem_object_set_cache_level(obj,
451 I915_CACHE_WT : I915_CACHE_NONE);
455 /* VT-d may overfetch before/after the vma, so pad with scratch */
456 if (intel_scanout_needs_vtd_wa(i915)) {
457 unsigned int guard = VTD_GUARD;
459 if (i915_gem_object_is_tiled(obj))
461 i915_gem_object_get_tile_row_size(obj));
463 flags |= PIN_OFFSET_GUARD | guard;
467 * As the user may map the buffer once pinned in the display plane
468 * (e.g. libkms for the bootup splash), we have to ensure that we
469 * always use map_and_fenceable for all scanout buffers. However,
470 * it may simply be too big to fit into mappable, in which case
471 * put it anyway and hope that userspace can cope (but always first
472 * try to preserve the existing ABI).
474 vma = ERR_PTR(-ENOSPC);
475 if ((flags & PIN_MAPPABLE) == 0 &&
476 (!view || view->type == I915_GTT_VIEW_NORMAL))
477 vma = i915_gem_object_ggtt_pin_ww(obj, ww, view, 0, alignment,
478 flags | PIN_MAPPABLE |
480 if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK))
481 vma = i915_gem_object_ggtt_pin_ww(obj, ww, view, 0,
486 vma->display_alignment = max(vma->display_alignment, alignment);
487 i915_vma_mark_scanout(vma);
489 i915_gem_object_flush_if_display_locked(obj);
495 * i915_gem_object_set_to_cpu_domain - Moves a single object to the CPU read,
496 * and possibly write domain.
497 * @obj: object to act on
498 * @write: requesting write or read-only access
500 * This function returns when the move is complete, including waiting on
504 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
508 assert_object_held(obj);
510 ret = i915_gem_object_wait(obj,
511 I915_WAIT_INTERRUPTIBLE |
512 (write ? I915_WAIT_ALL : 0),
513 MAX_SCHEDULE_TIMEOUT);
517 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
519 /* Flush the CPU cache if it's still invalid. */
520 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
521 i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
522 obj->read_domains |= I915_GEM_DOMAIN_CPU;
525 /* It should now be out of any other write domains, and we can update
526 * the domain values for our changes.
528 GEM_BUG_ON(obj->write_domain & ~I915_GEM_DOMAIN_CPU);
530 /* If we're writing through the CPU, then the GPU read domains will
531 * need to be invalidated at next use.
534 __start_cpu_write(obj);
540 * i915_gem_set_domain_ioctl - Called when user space prepares to use an
541 * object with the CPU, either
542 * through the mmap ioctl's mapping or a GTT mapping.
544 * @data: ioctl data blob
548 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
549 struct drm_file *file)
551 struct drm_i915_gem_set_domain *args = data;
552 struct drm_i915_gem_object *obj;
553 u32 read_domains = args->read_domains;
554 u32 write_domain = args->write_domain;
557 if (IS_DGFX(to_i915(dev)))
560 /* Only handle setting domains to types used by the CPU. */
561 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
565 * Having something in the write domain implies it's in the read
566 * domain, and only that read domain. Enforce that in the request.
568 if (write_domain && read_domains != write_domain)
574 obj = i915_gem_object_lookup(file, args->handle);
579 * Try to flush the object off the GPU without holding the lock.
580 * We will repeat the flush holding the lock in the normal manner
581 * to catch cases where we are gazumped.
583 err = i915_gem_object_wait(obj,
584 I915_WAIT_INTERRUPTIBLE |
586 (write_domain ? I915_WAIT_ALL : 0),
587 MAX_SCHEDULE_TIMEOUT);
591 if (i915_gem_object_is_userptr(obj)) {
593 * Try to grab userptr pages, iris uses set_domain to check
596 err = i915_gem_object_userptr_validate(obj);
598 err = i915_gem_object_wait(obj,
599 I915_WAIT_INTERRUPTIBLE |
601 (write_domain ? I915_WAIT_ALL : 0),
602 MAX_SCHEDULE_TIMEOUT);
607 * Proxy objects do not control access to the backing storage, ergo
608 * they cannot be used as a means to manipulate the cache domain
609 * tracking for that backing storage. The proxy object is always
610 * considered to be outside of any cache domain.
612 if (i915_gem_object_is_proxy(obj)) {
617 err = i915_gem_object_lock_interruptible(obj, NULL);
622 * Flush and acquire obj->pages so that we are coherent through
623 * direct access in memory with previous cached writes through
624 * shmemfs and that our cache domain tracking remains valid.
625 * For example, if the obj->filp was moved to swap without us
626 * being notified and releasing the pages, we would mistakenly
627 * continue to assume that the obj remained out of the CPU cached
630 err = i915_gem_object_pin_pages(obj);
635 * Already in the desired write domain? Nothing for us to do!
637 * We apply a little bit of cunning here to catch a broader set of
638 * no-ops. If obj->write_domain is set, we must be in the same
639 * obj->read_domains, and only that domain. Therefore, if that
640 * obj->write_domain matches the request read_domains, we are
641 * already in the same read/write domain and can skip the operation,
642 * without having to further check the requested write_domain.
644 if (READ_ONCE(obj->write_domain) == read_domains)
647 if (read_domains & I915_GEM_DOMAIN_WC)
648 err = i915_gem_object_set_to_wc_domain(obj, write_domain);
649 else if (read_domains & I915_GEM_DOMAIN_GTT)
650 err = i915_gem_object_set_to_gtt_domain(obj, write_domain);
652 err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
655 i915_gem_object_unpin_pages(obj);
658 i915_gem_object_unlock(obj);
660 if (!err && write_domain)
661 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
664 i915_gem_object_put(obj);
669 * Pins the specified object's pages and synchronizes the object with
670 * GPU accesses. Sets needs_clflush to non-zero if the caller should
671 * flush the object from the CPU cache.
673 int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,
674 unsigned int *needs_clflush)
679 if (!i915_gem_object_has_struct_page(obj))
682 assert_object_held(obj);
684 ret = i915_gem_object_wait(obj,
685 I915_WAIT_INTERRUPTIBLE,
686 MAX_SCHEDULE_TIMEOUT);
690 ret = i915_gem_object_pin_pages(obj);
694 if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
695 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
696 ret = i915_gem_object_set_to_cpu_domain(obj, false);
703 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
705 /* If we're not in the cpu read domain, set ourself into the gtt
706 * read domain and manually flush cachelines (if required). This
707 * optimizes for the case when the gpu will dirty the data
708 * anyway again before the next pread happens.
710 if (!obj->cache_dirty &&
711 !(obj->read_domains & I915_GEM_DOMAIN_CPU))
712 *needs_clflush = CLFLUSH_BEFORE;
715 /* return with the pages pinned */
719 i915_gem_object_unpin_pages(obj);
723 int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,
724 unsigned int *needs_clflush)
729 if (!i915_gem_object_has_struct_page(obj))
732 assert_object_held(obj);
734 ret = i915_gem_object_wait(obj,
735 I915_WAIT_INTERRUPTIBLE |
737 MAX_SCHEDULE_TIMEOUT);
741 ret = i915_gem_object_pin_pages(obj);
745 if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
746 !static_cpu_has(X86_FEATURE_CLFLUSH)) {
747 ret = i915_gem_object_set_to_cpu_domain(obj, true);
754 flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
756 /* If we're not in the cpu write domain, set ourself into the
757 * gtt write domain and manually flush cachelines (as required).
758 * This optimizes for the case when the gpu will use the data
759 * right away and we therefore have to clflush anyway.
761 if (!obj->cache_dirty) {
762 *needs_clflush |= CLFLUSH_AFTER;
765 * Same trick applies to invalidate partially written
766 * cachelines read before writing.
768 if (!(obj->read_domains & I915_GEM_DOMAIN_CPU))
769 *needs_clflush |= CLFLUSH_BEFORE;
773 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
774 obj->mm.dirty = true;
775 /* return with the pages pinned */
779 i915_gem_object_unpin_pages(obj);