drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright 2012 Red Hat Inc
   5  */
   6
   7 #include <linux/dma-buf.h>
   8 #include <linux/highmem.h>
   9 #include <linux/dma-resv.h>
  10 #include <linux/module.h>
  11
  12 #include <asm/smp.h>
  13
  14 #include "i915_drv.h"
  15 #include "i915_gem_object.h"
  16 #include "i915_scatterlist.h"
  17
  18 MODULE_IMPORT_NS(DMA_BUF);
  19
  20 #if defined(CONFIG_X86)
  21 #include <asm/smp.h>
  22 #else
  23 #define wbinvd_on_all_cpus() \
  24         pr_warn(DRIVER_NAME ": Missing cache flush in %s\n", __func__)
  25 #endif
  26
  27 I915_SELFTEST_DECLARE(static bool force_different_devices;)
  28
  29 static struct drm_i915_gem_object *dma_buf_to_obj(struct dma_buf *buf)
  30 {
  31         return to_intel_bo(buf->priv);
  32 }
  33
  34 static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attachment,
  35                                              enum dma_data_direction dir)
  36 {
  37         struct drm_i915_gem_object *obj = dma_buf_to_obj(attachment->dmabuf);
  38         struct sg_table *st;
  39         struct scatterlist *src, *dst;
  40         int ret, i;
  41
  42         /* Copy sg so that we make an independent mapping */
  43         st = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
  44         if (st == NULL) {
  45                 ret = -ENOMEM;
  46                 goto err;
  47         }
  48
  49         ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL);
  50         if (ret)
  51                 goto err_free;
  52
  53         src = obj->mm.pages->sgl;
  54         dst = st->sgl;
  55         for (i = 0; i < obj->mm.pages->nents; i++) {
  56                 sg_set_page(dst, sg_page(src), src->length, 0);
  57                 dst = sg_next(dst);
  58                 src = sg_next(src);
  59         }
  60
  61         ret = dma_map_sgtable(attachment->dev, st, dir, DMA_ATTR_SKIP_CPU_SYNC);
  62         if (ret)
  63                 goto err_free_sg;
  64
  65         return st;
  66
  67 err_free_sg:
  68         sg_free_table(st);
  69 err_free:
  70         kfree(st);
  71 err:
  72         return ERR_PTR(ret);
  73 }
  74
  75 static void i915_gem_unmap_dma_buf(struct dma_buf_attachment *attachment,
  76                                    struct sg_table *sg,
  77                                    enum dma_data_direction dir)
  78 {
  79         dma_unmap_sgtable(attachment->dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC);
  80         sg_free_table(sg);
  81         kfree(sg);
  82 }
  83
  84 static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
  85 {
  86         struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
  87         void *vaddr;
  88
  89         vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
  90         if (IS_ERR(vaddr))
  91                 return PTR_ERR(vaddr);
  92
  93         dma_buf_map_set_vaddr(map, vaddr);
  94
  95         return 0;
  96 }
  97
  98 static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf, struct dma_buf_map *map)
  99 {
 100         struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
 101
 102         i915_gem_object_flush_map(obj);
 103         i915_gem_object_unpin_map(obj);
 104 }
 105
 106 static int i915_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma)
 107 {
 108         struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
 109         int ret;
 110
 111         if (obj->base.size < vma->vm_end - vma->vm_start)
 112                 return -EINVAL;
 113
 114         if (!obj->base.filp)
 115                 return -ENODEV;
 116
 117         ret = call_mmap(obj->base.filp, vma);
 118         if (ret)
 119                 return ret;
 120
 121         vma_set_file(vma, obj->base.filp);
 122
 123         return 0;
 124 }
 125
 126 static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction)
 127 {
 128         struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
 129         bool write = (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE);
 130         struct i915_gem_ww_ctx ww;
 131         int err;
 132
 133         i915_gem_ww_ctx_init(&ww, true);
 134 retry:
 135         err = i915_gem_object_lock(obj, &ww);
 136         if (!err)
 137                 err = i915_gem_object_pin_pages(obj);
 138         if (!err) {
 139                 err = i915_gem_object_set_to_cpu_domain(obj, write);
 140                 i915_gem_object_unpin_pages(obj);
 141         }
 142         if (err == -EDEADLK) {
 143                 err = i915_gem_ww_ctx_backoff(&ww);
 144                 if (!err)
 145                         goto retry;
 146         }
 147         i915_gem_ww_ctx_fini(&ww);
 148         return err;
 149 }
 150
 151 static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction)
 152 {
 153         struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
 154         struct i915_gem_ww_ctx ww;
 155         int err;
 156
 157         i915_gem_ww_ctx_init(&ww, true);
 158 retry:
 159         err = i915_gem_object_lock(obj, &ww);
 160         if (!err)
 161                 err = i915_gem_object_pin_pages(obj);
 162         if (!err) {
 163                 err = i915_gem_object_set_to_gtt_domain(obj, false);
 164                 i915_gem_object_unpin_pages(obj);
 165         }
 166         if (err == -EDEADLK) {
 167                 err = i915_gem_ww_ctx_backoff(&ww);
 168                 if (!err)
 169                         goto retry;
 170         }
 171         i915_gem_ww_ctx_fini(&ww);
 172         return err;
 173 }
 174
 175 static int i915_gem_dmabuf_attach(struct dma_buf *dmabuf,
 176                                   struct dma_buf_attachment *attach)
 177 {
 178         struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf);
 179         struct i915_gem_ww_ctx ww;
 180         int err;
 181
 182         if (!i915_gem_object_can_migrate(obj, INTEL_REGION_SMEM))
 183                 return -EOPNOTSUPP;
 184
 185         for_i915_gem_ww(&ww, err, true) {
 186                 err = i915_gem_object_lock(obj, &ww);
 187                 if (err)
 188                         continue;
 189
 190                 err = i915_gem_object_migrate(obj, &ww, INTEL_REGION_SMEM);
 191                 if (err)
 192                         continue;
 193
 194                 err = i915_gem_object_wait_migration(obj, 0);
 195                 if (err)
 196                         continue;
 197
 198                 err = i915_gem_object_pin_pages(obj);
 199         }
 200
 201         return err;
 202 }
 203
 204 static void i915_gem_dmabuf_detach(struct dma_buf *dmabuf,
 205                                    struct dma_buf_attachment *attach)
 206 {
 207         struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf);
 208
 209         i915_gem_object_unpin_pages(obj);
 210 }
 211
 212 static const struct dma_buf_ops i915_dmabuf_ops =  {
 213         .attach = i915_gem_dmabuf_attach,
 214         .detach = i915_gem_dmabuf_detach,
 215         .map_dma_buf = i915_gem_map_dma_buf,
 216         .unmap_dma_buf = i915_gem_unmap_dma_buf,
 217         .release = drm_gem_dmabuf_release,
 218         .mmap = i915_gem_dmabuf_mmap,
 219         .vmap = i915_gem_dmabuf_vmap,
 220         .vunmap = i915_gem_dmabuf_vunmap,
 221         .begin_cpu_access = i915_gem_begin_cpu_access,
 222         .end_cpu_access = i915_gem_end_cpu_access,
 223 };
 224
 225 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags)
 226 {
 227         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
 228         DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
 229
 230         exp_info.ops = &i915_dmabuf_ops;
 231         exp_info.size = gem_obj->size;
 232         exp_info.flags = flags;
 233         exp_info.priv = gem_obj;
 234         exp_info.resv = obj->base.resv;
 235
 236         if (obj->ops->dmabuf_export) {
 237                 int ret = obj->ops->dmabuf_export(obj);
 238                 if (ret)
 239                         return ERR_PTR(ret);
 240         }
 241
 242         return drm_gem_dmabuf_export(gem_obj->dev, &exp_info);
 243 }
 244
 245 static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
 246 {
 247         struct drm_i915_private *i915 = to_i915(obj->base.dev);
 248         struct sg_table *pages;
 249         unsigned int sg_page_sizes;
 250
 251         assert_object_held(obj);
 252
 253         pages = dma_buf_map_attachment(obj->base.import_attach,
 254                                        DMA_BIDIRECTIONAL);
 255         if (IS_ERR(pages))
 256                 return PTR_ERR(pages);
 257
 258         /*
 259          * DG1 is special here since it still snoops transactions even with
 260          * CACHE_NONE. This is not the case with other HAS_SNOOP platforms. We
 261          * might need to revisit this as we add new discrete platforms.
 262          *
 263          * XXX: Consider doing a vmap flush or something, where possible.
 264          * Currently we just do a heavy handed wbinvd_on_all_cpus() here since
 265          * the underlying sg_table might not even point to struct pages, so we
 266          * can't just call drm_clflush_sg or similar, like we do elsewhere in
 267          * the driver.
 268          */
 269         if (i915_gem_object_can_bypass_llc(obj) ||
 270             (!HAS_LLC(i915) && !IS_DG1(i915)))
 271                 wbinvd_on_all_cpus();
 272
 273         sg_page_sizes = i915_sg_dma_sizes(pages->sgl);
 274         __i915_gem_object_set_pages(obj, pages, sg_page_sizes);
 275
 276         return 0;
 277 }
 278
 279 static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj,
 280                                              struct sg_table *pages)
 281 {
 282         dma_buf_unmap_attachment(obj->base.import_attach, pages,
 283                                  DMA_BIDIRECTIONAL);
 284 }
 285
 286 static const struct drm_i915_gem_object_ops i915_gem_object_dmabuf_ops = {
 287         .name = "i915_gem_object_dmabuf",
 288         .get_pages = i915_gem_object_get_pages_dmabuf,
 289         .put_pages = i915_gem_object_put_pages_dmabuf,
 290 };
 291
 292 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
 293                                              struct dma_buf *dma_buf)
 294 {
 295         static struct lock_class_key lock_class;
 296         struct dma_buf_attachment *attach;
 297         struct drm_i915_gem_object *obj;
 298         int ret;
 299
 300         /* is this one of own objects? */
 301         if (dma_buf->ops == &i915_dmabuf_ops) {
 302                 obj = dma_buf_to_obj(dma_buf);
 303                 /* is it from our device? */
 304                 if (obj->base.dev == dev &&
 305                     !I915_SELFTEST_ONLY(force_different_devices)) {
 306                         /*
 307                          * Importing dmabuf exported from out own gem increases
 308                          * refcount on gem itself instead of f_count of dmabuf.
 309                          */
 310                         return &i915_gem_object_get(obj)->base;
 311                 }
 312         }
 313
 314         if (i915_gem_object_size_2big(dma_buf->size))
 315                 return ERR_PTR(-E2BIG);
 316
 317         /* need to attach */
 318         attach = dma_buf_attach(dma_buf, dev->dev);
 319         if (IS_ERR(attach))
 320                 return ERR_CAST(attach);
 321
 322         get_dma_buf(dma_buf);
 323
 324         obj = i915_gem_object_alloc();
 325         if (obj == NULL) {
 326                 ret = -ENOMEM;
 327                 goto fail_detach;
 328         }
 329
 330         drm_gem_private_object_init(dev, &obj->base, dma_buf->size);
 331         i915_gem_object_init(obj, &i915_gem_object_dmabuf_ops, &lock_class,
 332                              I915_BO_ALLOC_USER);
 333         obj->base.import_attach = attach;
 334         obj->base.resv = dma_buf->resv;
 335
 336         /* We use GTT as shorthand for a coherent domain, one that is
 337          * neither in the GPU cache nor in the CPU cache, where all
 338          * writes are immediately visible in memory. (That's not strictly
 339          * true, but it's close! There are internal buffers such as the
 340          * write-combined buffer or a delay through the chipset for GTT
 341          * writes that do require us to treat GTT as a separate cache domain.)
 342          */
 343         obj->read_domains = I915_GEM_DOMAIN_GTT;
 344         obj->write_domain = 0;
 345
 346         return &obj->base;
 347
 348 fail_detach:
 349         dma_buf_detach(dma_buf, attach);
 350         dma_buf_put(dma_buf);
 351
 352         return ERR_PTR(ret);
 353 }
 354
 355 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 356 #include "selftests/mock_dmabuf.c"
 357 #include "selftests/i915_gem_dmabuf.c"
 358 #endif