2 * SPDX-License-Identifier: MIT
4 * Copyright © 2011-2012 Intel Corporation
8 * This file implements HW context support. On gen5+ a HW context consists of an
9 * opaque GPU object which is referenced at times of context saves and restores.
10 * With RC6 enabled, the context is also referenced as the GPU enters and exists
11 * from RC6 (GPU has it's own internal power context, except on gen5). Though
12 * something like a context does exist for the media ring, the code only
13 * supports contexts for the render ring.
15 * In software, there is a distinction between contexts created by the user,
16 * and the default HW context. The default HW context is used by GPU clients
17 * that do not request setup of their own hardware context. The default
18 * context's state is never restored to help prevent programming errors. This
19 * would happen if a client ran and piggy-backed off another clients GPU state.
20 * The default context only exists to give the GPU some offset to load as the
21 * current to invoke a save of the context we actually care about. In fact, the
22 * code could likely be constructed, albeit in a more complicated fashion, to
23 * never use the default context, though that limits the driver's ability to
24 * swap out, and/or destroy other contexts.
26 * All other contexts are created as a request by the GPU client. These contexts
27 * store GPU state, and thus allow GPU clients to not re-emit state (and
28 * potentially query certain state) at any time. The kernel driver makes
29 * certain that the appropriate commands are inserted.
31 * The context life cycle is semi-complicated in that context BOs may live
32 * longer than the context itself because of the way the hardware, and object
33 * tracking works. Below is a very crude representation of the state machine
34 * describing the context life.
35 * refcount pincount active
36 * S0: initial state 0 0 0
37 * S1: context created 1 0 0
38 * S2: context is currently running 2 1 X
39 * S3: GPU referenced, but not current 2 0 1
40 * S4: context is current, but destroyed 1 1 0
41 * S5: like S3, but destroyed 1 0 1
43 * The most common (but not all) transitions:
44 * S0->S1: client creates a context
45 * S1->S2: client submits execbuf with context
46 * S2->S3: other clients submits execbuf with context
47 * S3->S1: context object was retired
48 * S3->S2: clients submits another execbuf
49 * S2->S4: context destroy called with current context
50 * S3->S5->S0: destroy path
51 * S4->S5->S0: destroy path on current context
53 * There are two confusing terms used above:
54 * The "current context" means the context which is currently running on the
55 * GPU. The GPU has loaded its state already and has stored away the gtt
56 * offset of the BO. The GPU is not actively referencing the data at this
57 * offset, but it will on the next context switch. The only way to avoid this
58 * is to do a GPU reset.
60 * An "active context' is one which was previously the "current context" and is
61 * on the active list waiting for the next context switch to occur. Until this
62 * happens, the object must remain at the same gtt offset. It is therefore
63 * possible to destroy a context, but it is still active.
67 #include <linux/log2.h>
68 #include <linux/nospec.h>
70 #include <drm/drm_syncobj.h>
72 #include "gt/gen6_ppgtt.h"
73 #include "gt/intel_context.h"
74 #include "gt/intel_context_param.h"
75 #include "gt/intel_engine_heartbeat.h"
76 #include "gt/intel_engine_user.h"
77 #include "gt/intel_gpu_commands.h"
78 #include "gt/intel_ring.h"
80 #include "pxp/intel_pxp.h"
82 #include "i915_gem_context.h"
83 #include "i915_trace.h"
84 #include "i915_user_extensions.h"
86 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
88 static struct kmem_cache *slab_luts;
90 struct i915_lut_handle *i915_lut_handle_alloc(void)
92 return kmem_cache_alloc(slab_luts, GFP_KERNEL);
95 void i915_lut_handle_free(struct i915_lut_handle *lut)
97 return kmem_cache_free(slab_luts, lut);
100 static void lut_close(struct i915_gem_context *ctx)
102 struct radix_tree_iter iter;
105 mutex_lock(&ctx->lut_mutex);
107 radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
108 struct i915_vma *vma = rcu_dereference_raw(*slot);
109 struct drm_i915_gem_object *obj = vma->obj;
110 struct i915_lut_handle *lut;
112 if (!kref_get_unless_zero(&obj->base.refcount))
115 spin_lock(&obj->lut_lock);
116 list_for_each_entry(lut, &obj->lut_list, obj_link) {
120 if (lut->handle != iter.index)
123 list_del(&lut->obj_link);
126 spin_unlock(&obj->lut_lock);
128 if (&lut->obj_link != &obj->lut_list) {
129 i915_lut_handle_free(lut);
130 radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
132 i915_gem_object_put(obj);
135 i915_gem_object_put(obj);
138 mutex_unlock(&ctx->lut_mutex);
141 static struct intel_context *
142 lookup_user_engine(struct i915_gem_context *ctx,
144 const struct i915_engine_class_instance *ci)
145 #define LOOKUP_USER_INDEX BIT(0)
149 if (!!(flags & LOOKUP_USER_INDEX) != i915_gem_context_user_engines(ctx))
150 return ERR_PTR(-EINVAL);
152 if (!i915_gem_context_user_engines(ctx)) {
153 struct intel_engine_cs *engine;
155 engine = intel_engine_lookup_user(ctx->i915,
157 ci->engine_instance);
159 return ERR_PTR(-EINVAL);
161 idx = engine->legacy_idx;
163 idx = ci->engine_instance;
166 return i915_gem_context_get_engine(ctx, idx);
169 static int validate_priority(struct drm_i915_private *i915,
170 const struct drm_i915_gem_context_param *args)
172 s64 priority = args->value;
177 if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
180 if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
181 priority < I915_CONTEXT_MIN_USER_PRIORITY)
184 if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
185 !capable(CAP_SYS_NICE))
191 static void proto_context_close(struct drm_i915_private *i915,
192 struct i915_gem_proto_context *pc)
197 intel_runtime_pm_put(&i915->runtime_pm, pc->pxp_wakeref);
200 if (pc->user_engines) {
201 for (i = 0; i < pc->num_user_engines; i++)
202 kfree(pc->user_engines[i].siblings);
203 kfree(pc->user_engines);
208 static int proto_context_set_persistence(struct drm_i915_private *i915,
209 struct i915_gem_proto_context *pc,
214 * Only contexts that are short-lived [that will expire or be
215 * reset] are allowed to survive past termination. We require
216 * hangcheck to ensure that the persistent requests are healthy.
218 if (!i915->params.enable_hangcheck)
221 pc->user_flags |= BIT(UCONTEXT_PERSISTENCE);
223 /* To cancel a context we use "preempt-to-idle" */
224 if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
228 * If the cancel fails, we then need to reset, cleanly!
230 * If the per-engine reset fails, all hope is lost! We resort
231 * to a full GPU reset in that unlikely case, but realistically
232 * if the engine could not reset, the full reset does not fare
233 * much better. The damage has been done.
235 * However, if we cannot reset an engine by itself, we cannot
236 * cleanup a hanging persistent context without causing
237 * colateral damage, and we should not pretend we can by
238 * exposing the interface.
240 if (!intel_has_reset_engine(to_gt(i915)))
243 pc->user_flags &= ~BIT(UCONTEXT_PERSISTENCE);
249 static int proto_context_set_protected(struct drm_i915_private *i915,
250 struct i915_gem_proto_context *pc,
256 pc->uses_protected_content = false;
257 } else if (!intel_pxp_is_enabled(&to_gt(i915)->pxp)) {
259 } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
260 !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
263 pc->uses_protected_content = true;
266 * protected context usage requires the PXP session to be up,
267 * which in turn requires the device to be active.
269 pc->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm);
271 if (!intel_pxp_is_active(&to_gt(i915)->pxp))
272 ret = intel_pxp_start(&to_gt(i915)->pxp);
278 static struct i915_gem_proto_context *
279 proto_context_create(struct drm_i915_private *i915, unsigned int flags)
281 struct i915_gem_proto_context *pc, *err;
283 pc = kzalloc(sizeof(*pc), GFP_KERNEL);
285 return ERR_PTR(-ENOMEM);
287 pc->num_user_engines = -1;
288 pc->user_engines = NULL;
289 pc->user_flags = BIT(UCONTEXT_BANNABLE) |
290 BIT(UCONTEXT_RECOVERABLE);
291 if (i915->params.enable_hangcheck)
292 pc->user_flags |= BIT(UCONTEXT_PERSISTENCE);
293 pc->sched.priority = I915_PRIORITY_NORMAL;
295 if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
296 if (!HAS_EXECLISTS(i915)) {
297 err = ERR_PTR(-EINVAL);
300 pc->single_timeline = true;
306 proto_context_close(i915, pc);
310 static int proto_context_register_locked(struct drm_i915_file_private *fpriv,
311 struct i915_gem_proto_context *pc,
317 lockdep_assert_held(&fpriv->proto_context_lock);
319 ret = xa_alloc(&fpriv->context_xa, id, NULL, xa_limit_32b, GFP_KERNEL);
323 old = xa_store(&fpriv->proto_context_xa, *id, pc, GFP_KERNEL);
324 if (xa_is_err(old)) {
325 xa_erase(&fpriv->context_xa, *id);
333 static int proto_context_register(struct drm_i915_file_private *fpriv,
334 struct i915_gem_proto_context *pc,
339 mutex_lock(&fpriv->proto_context_lock);
340 ret = proto_context_register_locked(fpriv, pc, id);
341 mutex_unlock(&fpriv->proto_context_lock);
346 static int set_proto_ctx_vm(struct drm_i915_file_private *fpriv,
347 struct i915_gem_proto_context *pc,
348 const struct drm_i915_gem_context_param *args)
350 struct drm_i915_private *i915 = fpriv->dev_priv;
351 struct i915_address_space *vm;
356 if (!HAS_FULL_PPGTT(i915))
359 if (upper_32_bits(args->value))
362 vm = i915_gem_vm_lookup(fpriv, args->value);
373 struct set_proto_ctx_engines {
374 struct drm_i915_private *i915;
375 unsigned num_engines;
376 struct i915_gem_proto_engine *engines;
380 set_proto_ctx_engines_balance(struct i915_user_extension __user *base,
383 struct i915_context_engines_load_balance __user *ext =
384 container_of_user(base, typeof(*ext), base);
385 const struct set_proto_ctx_engines *set = data;
386 struct drm_i915_private *i915 = set->i915;
387 struct intel_engine_cs **siblings;
388 u16 num_siblings, idx;
392 if (!HAS_EXECLISTS(i915))
395 if (get_user(idx, &ext->engine_index))
398 if (idx >= set->num_engines) {
399 drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
400 idx, set->num_engines);
404 idx = array_index_nospec(idx, set->num_engines);
405 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_INVALID) {
407 "Invalid placement[%d], already occupied\n", idx);
411 if (get_user(num_siblings, &ext->num_siblings))
414 err = check_user_mbz(&ext->flags);
418 err = check_user_mbz(&ext->mbz64);
422 if (num_siblings == 0)
425 siblings = kmalloc_array(num_siblings, sizeof(*siblings), GFP_KERNEL);
429 for (n = 0; n < num_siblings; n++) {
430 struct i915_engine_class_instance ci;
432 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
437 siblings[n] = intel_engine_lookup_user(i915,
442 "Invalid sibling[%d]: { class:%d, inst:%d }\n",
443 n, ci.engine_class, ci.engine_instance);
449 if (num_siblings == 1) {
450 set->engines[idx].type = I915_GEM_ENGINE_TYPE_PHYSICAL;
451 set->engines[idx].engine = siblings[0];
454 set->engines[idx].type = I915_GEM_ENGINE_TYPE_BALANCED;
455 set->engines[idx].num_siblings = num_siblings;
456 set->engines[idx].siblings = siblings;
468 set_proto_ctx_engines_bond(struct i915_user_extension __user *base, void *data)
470 struct i915_context_engines_bond __user *ext =
471 container_of_user(base, typeof(*ext), base);
472 const struct set_proto_ctx_engines *set = data;
473 struct drm_i915_private *i915 = set->i915;
474 struct i915_engine_class_instance ci;
475 struct intel_engine_cs *master;
479 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915) &&
480 !IS_ROCKETLAKE(i915) && !IS_ALDERLAKE_S(i915)) {
482 "Bonding not supported on this platform\n");
486 if (get_user(idx, &ext->virtual_index))
489 if (idx >= set->num_engines) {
491 "Invalid index for virtual engine: %d >= %d\n",
492 idx, set->num_engines);
496 idx = array_index_nospec(idx, set->num_engines);
497 if (set->engines[idx].type == I915_GEM_ENGINE_TYPE_INVALID) {
498 drm_dbg(&i915->drm, "Invalid engine at %d\n", idx);
502 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_PHYSICAL) {
504 "Bonding with virtual engines not allowed\n");
508 err = check_user_mbz(&ext->flags);
512 for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
513 err = check_user_mbz(&ext->mbz64[n]);
518 if (copy_from_user(&ci, &ext->master, sizeof(ci)))
521 master = intel_engine_lookup_user(i915,
526 "Unrecognised master engine: { class:%u, instance:%u }\n",
527 ci.engine_class, ci.engine_instance);
531 if (intel_engine_uses_guc(master)) {
532 DRM_DEBUG("bonding extension not supported with GuC submission");
536 if (get_user(num_bonds, &ext->num_bonds))
539 for (n = 0; n < num_bonds; n++) {
540 struct intel_engine_cs *bond;
542 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci)))
545 bond = intel_engine_lookup_user(i915,
550 "Unrecognised engine[%d] for bonding: { class:%d, instance: %d }\n",
551 n, ci.engine_class, ci.engine_instance);
560 set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
563 struct i915_context_engines_parallel_submit __user *ext =
564 container_of_user(base, typeof(*ext), base);
565 const struct set_proto_ctx_engines *set = data;
566 struct drm_i915_private *i915 = set->i915;
567 struct i915_engine_class_instance prev_engine;
569 int err = 0, n, i, j;
570 u16 slot, width, num_siblings;
571 struct intel_engine_cs **siblings = NULL;
572 intel_engine_mask_t prev_mask;
574 /* FIXME: This is NIY for execlists */
575 if (!(intel_uc_uses_guc_submission(&to_gt(i915)->uc)))
578 if (get_user(slot, &ext->engine_index))
581 if (get_user(width, &ext->width))
584 if (get_user(num_siblings, &ext->num_siblings))
587 if (slot >= set->num_engines) {
588 drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
589 slot, set->num_engines);
593 if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
595 "Invalid placement[%d], already occupied\n", slot);
599 if (get_user(flags, &ext->flags))
603 drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
607 for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
608 err = check_user_mbz(&ext->mbz64[n]);
614 drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
618 if (num_siblings < 1) {
619 drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
624 siblings = kmalloc_array(num_siblings * width,
630 /* Create contexts / engines */
631 for (i = 0; i < width; ++i) {
632 intel_engine_mask_t current_mask = 0;
634 for (j = 0; j < num_siblings; ++j) {
635 struct i915_engine_class_instance ci;
637 n = i * num_siblings + j;
638 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
644 intel_engine_lookup_user(i915, ci.engine_class,
648 "Invalid sibling[%d]: { class:%d, inst:%d }\n",
649 n, ci.engine_class, ci.engine_instance);
655 if (prev_engine.engine_class !=
658 "Mismatched class %d, %d\n",
659 prev_engine.engine_class,
667 current_mask |= siblings[n]->logical_mask;
671 if (current_mask != prev_mask << 1) {
673 "Non contiguous logical mask 0x%x, 0x%x\n",
674 prev_mask, current_mask);
679 prev_mask = current_mask;
682 set->engines[slot].type = I915_GEM_ENGINE_TYPE_PARALLEL;
683 set->engines[slot].num_siblings = num_siblings;
684 set->engines[slot].width = width;
685 set->engines[slot].siblings = siblings;
695 static const i915_user_extension_fn set_proto_ctx_engines_extensions[] = {
696 [I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_proto_ctx_engines_balance,
697 [I915_CONTEXT_ENGINES_EXT_BOND] = set_proto_ctx_engines_bond,
698 [I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT] =
699 set_proto_ctx_engines_parallel_submit,
702 static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
703 struct i915_gem_proto_context *pc,
704 const struct drm_i915_gem_context_param *args)
706 struct drm_i915_private *i915 = fpriv->dev_priv;
707 struct set_proto_ctx_engines set = { .i915 = i915 };
708 struct i915_context_param_engines __user *user =
709 u64_to_user_ptr(args->value);
714 if (pc->num_user_engines >= 0) {
715 drm_dbg(&i915->drm, "Cannot set engines twice");
719 if (args->size < sizeof(*user) ||
720 !IS_ALIGNED(args->size - sizeof(*user), sizeof(*user->engines))) {
721 drm_dbg(&i915->drm, "Invalid size for engine array: %d\n",
726 set.num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines);
727 /* RING_MASK has no shift so we can use it directly here */
728 if (set.num_engines > I915_EXEC_RING_MASK + 1)
731 set.engines = kmalloc_array(set.num_engines, sizeof(*set.engines), GFP_KERNEL);
735 for (n = 0; n < set.num_engines; n++) {
736 struct i915_engine_class_instance ci;
737 struct intel_engine_cs *engine;
739 if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) {
744 memset(&set.engines[n], 0, sizeof(set.engines[n]));
746 if (ci.engine_class == (u16)I915_ENGINE_CLASS_INVALID &&
747 ci.engine_instance == (u16)I915_ENGINE_CLASS_INVALID_NONE)
750 engine = intel_engine_lookup_user(i915,
755 "Invalid engine[%d]: { class:%d, instance:%d }\n",
756 n, ci.engine_class, ci.engine_instance);
761 set.engines[n].type = I915_GEM_ENGINE_TYPE_PHYSICAL;
762 set.engines[n].engine = engine;
766 if (!get_user(extensions, &user->extensions))
767 err = i915_user_extensions(u64_to_user_ptr(extensions),
768 set_proto_ctx_engines_extensions,
769 ARRAY_SIZE(set_proto_ctx_engines_extensions),
776 pc->num_user_engines = set.num_engines;
777 pc->user_engines = set.engines;
782 static int set_proto_ctx_sseu(struct drm_i915_file_private *fpriv,
783 struct i915_gem_proto_context *pc,
784 struct drm_i915_gem_context_param *args)
786 struct drm_i915_private *i915 = fpriv->dev_priv;
787 struct drm_i915_gem_context_param_sseu user_sseu;
788 struct intel_sseu *sseu;
791 if (args->size < sizeof(user_sseu))
794 if (GRAPHICS_VER(i915) != 11)
797 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
804 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
807 if (!!(user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX) != (pc->num_user_engines >= 0))
810 if (pc->num_user_engines >= 0) {
811 int idx = user_sseu.engine.engine_instance;
812 struct i915_gem_proto_engine *pe;
814 if (idx >= pc->num_user_engines)
817 pe = &pc->user_engines[idx];
819 /* Only render engine supports RPCS configuration. */
820 if (pe->engine->class != RENDER_CLASS)
825 /* Only render engine supports RPCS configuration. */
826 if (user_sseu.engine.engine_class != I915_ENGINE_CLASS_RENDER)
829 /* There is only one render engine */
830 if (user_sseu.engine.engine_instance != 0)
833 sseu = &pc->legacy_rcs_sseu;
836 ret = i915_gem_user_to_context_sseu(to_gt(i915), &user_sseu, sseu);
840 args->size = sizeof(user_sseu);
845 static int set_proto_ctx_param(struct drm_i915_file_private *fpriv,
846 struct i915_gem_proto_context *pc,
847 struct drm_i915_gem_context_param *args)
851 switch (args->param) {
852 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
855 else if (args->value)
856 pc->user_flags |= BIT(UCONTEXT_NO_ERROR_CAPTURE);
858 pc->user_flags &= ~BIT(UCONTEXT_NO_ERROR_CAPTURE);
861 case I915_CONTEXT_PARAM_BANNABLE:
864 else if (!capable(CAP_SYS_ADMIN) && !args->value)
866 else if (args->value)
867 pc->user_flags |= BIT(UCONTEXT_BANNABLE);
868 else if (pc->uses_protected_content)
871 pc->user_flags &= ~BIT(UCONTEXT_BANNABLE);
874 case I915_CONTEXT_PARAM_RECOVERABLE:
877 else if (!args->value)
878 pc->user_flags &= ~BIT(UCONTEXT_RECOVERABLE);
879 else if (pc->uses_protected_content)
882 pc->user_flags |= BIT(UCONTEXT_RECOVERABLE);
885 case I915_CONTEXT_PARAM_PRIORITY:
886 ret = validate_priority(fpriv->dev_priv, args);
888 pc->sched.priority = args->value;
891 case I915_CONTEXT_PARAM_SSEU:
892 ret = set_proto_ctx_sseu(fpriv, pc, args);
895 case I915_CONTEXT_PARAM_VM:
896 ret = set_proto_ctx_vm(fpriv, pc, args);
899 case I915_CONTEXT_PARAM_ENGINES:
900 ret = set_proto_ctx_engines(fpriv, pc, args);
903 case I915_CONTEXT_PARAM_PERSISTENCE:
906 ret = proto_context_set_persistence(fpriv->dev_priv, pc,
910 case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
911 ret = proto_context_set_protected(fpriv->dev_priv, pc,
915 case I915_CONTEXT_PARAM_NO_ZEROMAP:
916 case I915_CONTEXT_PARAM_BAN_PERIOD:
917 case I915_CONTEXT_PARAM_RINGSIZE:
926 static int intel_context_set_gem(struct intel_context *ce,
927 struct i915_gem_context *ctx,
928 struct intel_sseu sseu)
932 GEM_BUG_ON(rcu_access_pointer(ce->gem_context));
933 RCU_INIT_POINTER(ce->gem_context, ctx);
935 GEM_BUG_ON(intel_context_is_pinned(ce));
936 ce->ring_size = SZ_16K;
939 ce->vm = i915_gem_context_get_eb_vm(ctx);
941 if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
942 intel_engine_has_timeslices(ce->engine) &&
943 intel_engine_has_semaphores(ce->engine))
944 __set_bit(CONTEXT_USE_SEMAPHORES, &ce->flags);
946 if (CONFIG_DRM_I915_REQUEST_TIMEOUT &&
947 ctx->i915->params.request_timeout_ms) {
948 unsigned int timeout_ms = ctx->i915->params.request_timeout_ms;
950 intel_context_set_watchdog_us(ce, (u64)timeout_ms * 1000);
953 /* A valid SSEU has no zero fields */
954 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS))
955 ret = intel_context_reconfigure_sseu(ce, sseu);
960 static void __unpin_engines(struct i915_gem_engines *e, unsigned int count)
963 struct intel_context *ce = e->engines[count], *child;
965 if (!ce || !test_bit(CONTEXT_PERMA_PIN, &ce->flags))
968 for_each_child(ce, child)
969 intel_context_unpin(child);
970 intel_context_unpin(ce);
974 static void unpin_engines(struct i915_gem_engines *e)
976 __unpin_engines(e, e->num_engines);
979 static void __free_engines(struct i915_gem_engines *e, unsigned int count)
982 if (!e->engines[count])
985 intel_context_put(e->engines[count]);
990 static void free_engines(struct i915_gem_engines *e)
992 __free_engines(e, e->num_engines);
995 static void free_engines_rcu(struct rcu_head *rcu)
997 struct i915_gem_engines *engines =
998 container_of(rcu, struct i915_gem_engines, rcu);
1000 i915_sw_fence_fini(&engines->fence);
1001 free_engines(engines);
1005 engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
1007 struct i915_gem_engines *engines =
1008 container_of(fence, typeof(*engines), fence);
1011 case FENCE_COMPLETE:
1012 if (!list_empty(&engines->link)) {
1013 struct i915_gem_context *ctx = engines->ctx;
1014 unsigned long flags;
1016 spin_lock_irqsave(&ctx->stale.lock, flags);
1017 list_del(&engines->link);
1018 spin_unlock_irqrestore(&ctx->stale.lock, flags);
1020 i915_gem_context_put(engines->ctx);
1024 init_rcu_head(&engines->rcu);
1025 call_rcu(&engines->rcu, free_engines_rcu);
1032 static struct i915_gem_engines *alloc_engines(unsigned int count)
1034 struct i915_gem_engines *e;
1036 e = kzalloc(struct_size(e, engines, count), GFP_KERNEL);
1040 i915_sw_fence_init(&e->fence, engines_notify);
1044 static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,
1045 struct intel_sseu rcs_sseu)
1047 const struct intel_gt *gt = to_gt(ctx->i915);
1048 struct intel_engine_cs *engine;
1049 struct i915_gem_engines *e, *err;
1050 enum intel_engine_id id;
1052 e = alloc_engines(I915_NUM_ENGINES);
1054 return ERR_PTR(-ENOMEM);
1056 for_each_engine(engine, gt, id) {
1057 struct intel_context *ce;
1058 struct intel_sseu sseu = {};
1061 if (engine->legacy_idx == INVALID_ENGINE)
1064 GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);
1065 GEM_BUG_ON(e->engines[engine->legacy_idx]);
1067 ce = intel_context_create(engine);
1073 e->engines[engine->legacy_idx] = ce;
1074 e->num_engines = max(e->num_engines, engine->legacy_idx + 1);
1076 if (engine->class == RENDER_CLASS)
1079 ret = intel_context_set_gem(ce, ctx, sseu);
1094 static int perma_pin_contexts(struct intel_context *ce)
1096 struct intel_context *child;
1097 int i = 0, j = 0, ret;
1099 GEM_BUG_ON(!intel_context_is_parent(ce));
1101 ret = intel_context_pin(ce);
1105 for_each_child(ce, child) {
1106 ret = intel_context_pin(child);
1112 set_bit(CONTEXT_PERMA_PIN, &ce->flags);
1117 intel_context_unpin(ce);
1118 for_each_child(ce, child) {
1120 intel_context_unpin(child);
1128 static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
1129 unsigned int num_engines,
1130 struct i915_gem_proto_engine *pe)
1132 struct i915_gem_engines *e, *err;
1135 e = alloc_engines(num_engines);
1137 return ERR_PTR(-ENOMEM);
1138 e->num_engines = num_engines;
1140 for (n = 0; n < num_engines; n++) {
1141 struct intel_context *ce, *child;
1144 switch (pe[n].type) {
1145 case I915_GEM_ENGINE_TYPE_PHYSICAL:
1146 ce = intel_context_create(pe[n].engine);
1149 case I915_GEM_ENGINE_TYPE_BALANCED:
1150 ce = intel_engine_create_virtual(pe[n].siblings,
1151 pe[n].num_siblings, 0);
1154 case I915_GEM_ENGINE_TYPE_PARALLEL:
1155 ce = intel_engine_create_parallel(pe[n].siblings,
1160 case I915_GEM_ENGINE_TYPE_INVALID:
1162 GEM_WARN_ON(pe[n].type != I915_GEM_ENGINE_TYPE_INVALID);
1173 ret = intel_context_set_gem(ce, ctx, pe->sseu);
1178 for_each_child(ce, child) {
1179 ret = intel_context_set_gem(child, ctx, pe->sseu);
1187 * XXX: Must be done after calling intel_context_set_gem as that
1188 * function changes the ring size. The ring is allocated when
1189 * the context is pinned. If the ring size is changed after
1190 * allocation we have a mismatch of the ring size and will cause
1191 * the context to hang. Presumably with a bit of reordering we
1192 * could move the perma-pin step to the backend function
1193 * intel_engine_create_parallel.
1195 if (pe[n].type == I915_GEM_ENGINE_TYPE_PARALLEL) {
1196 ret = perma_pin_contexts(ce);
1211 static void i915_gem_context_release_work(struct work_struct *work)
1213 struct i915_gem_context *ctx = container_of(work, typeof(*ctx),
1215 struct i915_address_space *vm;
1217 trace_i915_context_free(ctx);
1218 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
1221 drm_syncobj_put(ctx->syncobj);
1227 if (ctx->pxp_wakeref)
1228 intel_runtime_pm_put(&ctx->i915->runtime_pm, ctx->pxp_wakeref);
1230 mutex_destroy(&ctx->engines_mutex);
1231 mutex_destroy(&ctx->lut_mutex);
1234 mutex_destroy(&ctx->mutex);
1236 kfree_rcu(ctx, rcu);
1239 void i915_gem_context_release(struct kref *ref)
1241 struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
1243 queue_work(ctx->i915->wq, &ctx->release_work);
1246 static inline struct i915_gem_engines *
1247 __context_engines_static(const struct i915_gem_context *ctx)
1249 return rcu_dereference_protected(ctx->engines, true);
1252 static void __reset_context(struct i915_gem_context *ctx,
1253 struct intel_engine_cs *engine)
1255 intel_gt_handle_error(engine->gt, engine->mask, 0,
1256 "context closure in %s", ctx->name);
1259 static bool __cancel_engine(struct intel_engine_cs *engine)
1262 * Send a "high priority pulse" down the engine to cause the
1263 * current request to be momentarily preempted. (If it fails to
1264 * be preempted, it will be reset). As we have marked our context
1265 * as banned, any incomplete request, including any running, will
1266 * be skipped following the preemption.
1268 * If there is no hangchecking (one of the reasons why we try to
1269 * cancel the context) and no forced preemption, there may be no
1270 * means by which we reset the GPU and evict the persistent hog.
1271 * Ergo if we are unable to inject a preemptive pulse that can
1272 * kill the banned context, we fallback to doing a local reset
1275 return intel_engine_pulse(engine) == 0;
1278 static struct intel_engine_cs *active_engine(struct intel_context *ce)
1280 struct intel_engine_cs *engine = NULL;
1281 struct i915_request *rq;
1283 if (intel_context_has_inflight(ce))
1284 return intel_context_inflight(ce);
1290 * rq->link is only SLAB_TYPESAFE_BY_RCU, we need to hold a reference
1291 * to the request to prevent it being transferred to a new timeline
1292 * (and onto a new timeline->requests list).
1295 list_for_each_entry_reverse(rq, &ce->timeline->requests, link) {
1298 /* timeline is already completed upto this point? */
1299 if (!i915_request_get_rcu(rq))
1302 /* Check with the backend if the request is inflight */
1304 if (likely(rcu_access_pointer(rq->timeline) == ce->timeline))
1305 found = i915_request_active_engine(rq, &engine);
1307 i915_request_put(rq);
1316 static void kill_engines(struct i915_gem_engines *engines, bool ban)
1318 struct i915_gem_engines_iter it;
1319 struct intel_context *ce;
1322 * Map the user's engine back to the actual engines; one virtual
1323 * engine will be mapped to multiple engines, and using ctx->engine[]
1324 * the same engine may be have multiple instances in the user's map.
1325 * However, we only care about pending requests, so only include
1326 * engines on which there are incomplete requests.
1328 for_each_gem_engine(ce, engines, it) {
1329 struct intel_engine_cs *engine;
1331 if (ban && intel_context_ban(ce, NULL))
1335 * Check the current active state of this context; if we
1336 * are currently executing on the GPU we need to evict
1337 * ourselves. On the other hand, if we haven't yet been
1338 * submitted to the GPU or if everything is complete,
1339 * we have nothing to do.
1341 engine = active_engine(ce);
1343 /* First attempt to gracefully cancel the context */
1344 if (engine && !__cancel_engine(engine) && ban)
1346 * If we are unable to send a preemptive pulse to bump
1347 * the context from the GPU, we have to resort to a full
1348 * reset. We hope the collateral damage is worth it.
1350 __reset_context(engines->ctx, engine);
1354 static void kill_context(struct i915_gem_context *ctx)
1356 bool ban = (!i915_gem_context_is_persistent(ctx) ||
1357 !ctx->i915->params.enable_hangcheck);
1358 struct i915_gem_engines *pos, *next;
1360 spin_lock_irq(&ctx->stale.lock);
1361 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
1362 list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
1363 if (!i915_sw_fence_await(&pos->fence)) {
1364 list_del_init(&pos->link);
1368 spin_unlock_irq(&ctx->stale.lock);
1370 kill_engines(pos, ban);
1372 spin_lock_irq(&ctx->stale.lock);
1373 GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
1374 list_safe_reset_next(pos, next, link);
1375 list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
1377 i915_sw_fence_complete(&pos->fence);
1379 spin_unlock_irq(&ctx->stale.lock);
1382 static void engines_idle_release(struct i915_gem_context *ctx,
1383 struct i915_gem_engines *engines)
1385 struct i915_gem_engines_iter it;
1386 struct intel_context *ce;
1388 INIT_LIST_HEAD(&engines->link);
1390 engines->ctx = i915_gem_context_get(ctx);
1392 for_each_gem_engine(ce, engines, it) {
1395 /* serialises with execbuf */
1396 set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
1397 if (!intel_context_pin_if_active(ce))
1400 /* Wait until context is finally scheduled out and retired */
1401 err = i915_sw_fence_await_active(&engines->fence,
1403 I915_ACTIVE_AWAIT_BARRIER);
1404 intel_context_unpin(ce);
1409 spin_lock_irq(&ctx->stale.lock);
1410 if (!i915_gem_context_is_closed(ctx))
1411 list_add_tail(&engines->link, &ctx->stale.engines);
1412 spin_unlock_irq(&ctx->stale.lock);
1415 if (list_empty(&engines->link)) /* raced, already closed */
1416 kill_engines(engines, true);
1418 i915_sw_fence_commit(&engines->fence);
1421 static void set_closed_name(struct i915_gem_context *ctx)
1425 /* Replace '[]' with '<>' to indicate closed in debug prints */
1427 s = strrchr(ctx->name, '[');
1433 s = strchr(s + 1, ']');
1438 static void context_close(struct i915_gem_context *ctx)
1440 struct i915_address_space *vm;
1442 /* Flush any concurrent set_engines() */
1443 mutex_lock(&ctx->engines_mutex);
1444 unpin_engines(__context_engines_static(ctx));
1445 engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
1446 i915_gem_context_set_closed(ctx);
1447 mutex_unlock(&ctx->engines_mutex);
1449 mutex_lock(&ctx->mutex);
1451 set_closed_name(ctx);
1455 /* i915_vm_close drops the final reference, which is a bit too
1456 * early and could result in surprises with concurrent
1457 * operations racing with thist ctx close. Keep a full reference
1464 ctx->file_priv = ERR_PTR(-EBADF);
1467 * The LUT uses the VMA as a backpointer to unref the object,
1468 * so we need to clear the LUT before we close all the VMA (inside
1473 spin_lock(&ctx->i915->gem.contexts.lock);
1474 list_del(&ctx->link);
1475 spin_unlock(&ctx->i915->gem.contexts.lock);
1477 mutex_unlock(&ctx->mutex);
1480 * If the user has disabled hangchecking, we can not be sure that
1481 * the batches will ever complete after the context is closed,
1482 * keeping the context and all resources pinned forever. So in this
1483 * case we opt to forcibly kill off all remaining requests on
1488 i915_gem_context_put(ctx);
1491 static int __context_set_persistence(struct i915_gem_context *ctx, bool state)
1493 if (i915_gem_context_is_persistent(ctx) == state)
1498 * Only contexts that are short-lived [that will expire or be
1499 * reset] are allowed to survive past termination. We require
1500 * hangcheck to ensure that the persistent requests are healthy.
1502 if (!ctx->i915->params.enable_hangcheck)
1505 i915_gem_context_set_persistence(ctx);
1507 /* To cancel a context we use "preempt-to-idle" */
1508 if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
1512 * If the cancel fails, we then need to reset, cleanly!
1514 * If the per-engine reset fails, all hope is lost! We resort
1515 * to a full GPU reset in that unlikely case, but realistically
1516 * if the engine could not reset, the full reset does not fare
1517 * much better. The damage has been done.
1519 * However, if we cannot reset an engine by itself, we cannot
1520 * cleanup a hanging persistent context without causing
1521 * colateral damage, and we should not pretend we can by
1522 * exposing the interface.
1524 if (!intel_has_reset_engine(to_gt(ctx->i915)))
1527 i915_gem_context_clear_persistence(ctx);
1533 static struct i915_gem_context *
1534 i915_gem_create_context(struct drm_i915_private *i915,
1535 const struct i915_gem_proto_context *pc)
1537 struct i915_gem_context *ctx;
1538 struct i915_address_space *vm = NULL;
1539 struct i915_gem_engines *e;
1543 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1545 return ERR_PTR(-ENOMEM);
1547 kref_init(&ctx->ref);
1549 ctx->sched = pc->sched;
1550 mutex_init(&ctx->mutex);
1551 INIT_LIST_HEAD(&ctx->link);
1552 INIT_WORK(&ctx->release_work, i915_gem_context_release_work);
1554 spin_lock_init(&ctx->stale.lock);
1555 INIT_LIST_HEAD(&ctx->stale.engines);
1558 vm = i915_vm_get(pc->vm);
1559 } else if (HAS_FULL_PPGTT(i915)) {
1560 struct i915_ppgtt *ppgtt;
1562 ppgtt = i915_ppgtt_create(to_gt(i915), 0);
1563 if (IS_ERR(ppgtt)) {
1564 drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
1566 err = PTR_ERR(ppgtt);
1572 ctx->vm = i915_vm_open(vm);
1574 /* i915_vm_open() takes a reference */
1578 mutex_init(&ctx->engines_mutex);
1579 if (pc->num_user_engines >= 0) {
1580 i915_gem_context_set_user_engines(ctx);
1581 e = user_engines(ctx, pc->num_user_engines, pc->user_engines);
1583 i915_gem_context_clear_user_engines(ctx);
1584 e = default_engines(ctx, pc->legacy_rcs_sseu);
1590 RCU_INIT_POINTER(ctx->engines, e);
1592 INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
1593 mutex_init(&ctx->lut_mutex);
1595 /* NB: Mark all slices as needing a remap so that when the context first
1596 * loads it will restore whatever remap state already exists. If there
1597 * is no remap info, it will be a NOP. */
1598 ctx->remap_slice = ALL_L3_SLICES(i915);
1600 ctx->user_flags = pc->user_flags;
1602 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
1603 ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
1605 if (pc->single_timeline) {
1606 err = drm_syncobj_create(&ctx->syncobj,
1607 DRM_SYNCOBJ_CREATE_SIGNALED,
1613 if (pc->uses_protected_content) {
1614 ctx->pxp_wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1615 ctx->uses_protected_content = true;
1618 trace_i915_context_create(ctx);
1626 i915_vm_close(ctx->vm);
1629 return ERR_PTR(err);
1632 static void init_contexts(struct i915_gem_contexts *gc)
1634 spin_lock_init(&gc->lock);
1635 INIT_LIST_HEAD(&gc->list);
1638 void i915_gem_init__contexts(struct drm_i915_private *i915)
1640 init_contexts(&i915->gem.contexts);
1643 static void gem_context_register(struct i915_gem_context *ctx,
1644 struct drm_i915_file_private *fpriv,
1647 struct drm_i915_private *i915 = ctx->i915;
1650 ctx->file_priv = fpriv;
1652 ctx->pid = get_task_pid(current, PIDTYPE_PID);
1653 snprintf(ctx->name, sizeof(ctx->name), "%s[%d]",
1654 current->comm, pid_nr(ctx->pid));
1656 /* And finally expose ourselves to userspace via the idr */
1657 old = xa_store(&fpriv->context_xa, id, ctx, GFP_KERNEL);
1660 spin_lock(&i915->gem.contexts.lock);
1661 list_add_tail(&ctx->link, &i915->gem.contexts.list);
1662 spin_unlock(&i915->gem.contexts.lock);
1665 int i915_gem_context_open(struct drm_i915_private *i915,
1666 struct drm_file *file)
1668 struct drm_i915_file_private *file_priv = file->driver_priv;
1669 struct i915_gem_proto_context *pc;
1670 struct i915_gem_context *ctx;
1673 mutex_init(&file_priv->proto_context_lock);
1674 xa_init_flags(&file_priv->proto_context_xa, XA_FLAGS_ALLOC);
1676 /* 0 reserved for the default context */
1677 xa_init_flags(&file_priv->context_xa, XA_FLAGS_ALLOC1);
1679 /* 0 reserved for invalid/unassigned ppgtt */
1680 xa_init_flags(&file_priv->vm_xa, XA_FLAGS_ALLOC1);
1682 pc = proto_context_create(i915, 0);
1688 ctx = i915_gem_create_context(i915, pc);
1689 proto_context_close(i915, pc);
1695 gem_context_register(ctx, file_priv, 0);
1700 xa_destroy(&file_priv->vm_xa);
1701 xa_destroy(&file_priv->context_xa);
1702 xa_destroy(&file_priv->proto_context_xa);
1703 mutex_destroy(&file_priv->proto_context_lock);
1707 void i915_gem_context_close(struct drm_file *file)
1709 struct drm_i915_file_private *file_priv = file->driver_priv;
1710 struct i915_gem_proto_context *pc;
1711 struct i915_address_space *vm;
1712 struct i915_gem_context *ctx;
1715 xa_for_each(&file_priv->proto_context_xa, idx, pc)
1716 proto_context_close(file_priv->dev_priv, pc);
1717 xa_destroy(&file_priv->proto_context_xa);
1718 mutex_destroy(&file_priv->proto_context_lock);
1720 xa_for_each(&file_priv->context_xa, idx, ctx)
1722 xa_destroy(&file_priv->context_xa);
1724 xa_for_each(&file_priv->vm_xa, idx, vm)
1726 xa_destroy(&file_priv->vm_xa);
1729 int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
1730 struct drm_file *file)
1732 struct drm_i915_private *i915 = to_i915(dev);
1733 struct drm_i915_gem_vm_control *args = data;
1734 struct drm_i915_file_private *file_priv = file->driver_priv;
1735 struct i915_ppgtt *ppgtt;
1739 if (!HAS_FULL_PPGTT(i915))
1745 ppgtt = i915_ppgtt_create(to_gt(i915), 0);
1747 return PTR_ERR(ppgtt);
1749 if (args->extensions) {
1750 err = i915_user_extensions(u64_to_user_ptr(args->extensions),
1757 err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm,
1758 xa_limit_32b, GFP_KERNEL);
1762 GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
1767 i915_vm_put(&ppgtt->vm);
1771 int i915_gem_vm_destroy_ioctl(struct drm_device *dev, void *data,
1772 struct drm_file *file)
1774 struct drm_i915_file_private *file_priv = file->driver_priv;
1775 struct drm_i915_gem_vm_control *args = data;
1776 struct i915_address_space *vm;
1781 if (args->extensions)
1784 vm = xa_erase(&file_priv->vm_xa, args->vm_id);
1792 static int get_ppgtt(struct drm_i915_file_private *file_priv,
1793 struct i915_gem_context *ctx,
1794 struct drm_i915_gem_context_param *args)
1796 struct i915_address_space *vm;
1800 if (!i915_gem_context_has_full_ppgtt(ctx))
1806 err = xa_alloc(&file_priv->vm_xa, &id, vm, xa_limit_32b, GFP_KERNEL);
1812 GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
1820 i915_gem_user_to_context_sseu(struct intel_gt *gt,
1821 const struct drm_i915_gem_context_param_sseu *user,
1822 struct intel_sseu *context)
1824 const struct sseu_dev_info *device = >->info.sseu;
1825 struct drm_i915_private *i915 = gt->i915;
1827 /* No zeros in any field. */
1828 if (!user->slice_mask || !user->subslice_mask ||
1829 !user->min_eus_per_subslice || !user->max_eus_per_subslice)
1833 if (user->max_eus_per_subslice < user->min_eus_per_subslice)
1837 * Some future proofing on the types since the uAPI is wider than the
1838 * current internal implementation.
1840 if (overflows_type(user->slice_mask, context->slice_mask) ||
1841 overflows_type(user->subslice_mask, context->subslice_mask) ||
1842 overflows_type(user->min_eus_per_subslice,
1843 context->min_eus_per_subslice) ||
1844 overflows_type(user->max_eus_per_subslice,
1845 context->max_eus_per_subslice))
1848 /* Check validity against hardware. */
1849 if (user->slice_mask & ~device->slice_mask)
1852 if (user->subslice_mask & ~device->subslice_mask[0])
1855 if (user->max_eus_per_subslice > device->max_eus_per_subslice)
1858 context->slice_mask = user->slice_mask;
1859 context->subslice_mask = user->subslice_mask;
1860 context->min_eus_per_subslice = user->min_eus_per_subslice;
1861 context->max_eus_per_subslice = user->max_eus_per_subslice;
1863 /* Part specific restrictions. */
1864 if (GRAPHICS_VER(i915) == 11) {
1865 unsigned int hw_s = hweight8(device->slice_mask);
1866 unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
1867 unsigned int req_s = hweight8(context->slice_mask);
1868 unsigned int req_ss = hweight8(context->subslice_mask);
1871 * Only full subslice enablement is possible if more than one
1872 * slice is turned on.
1874 if (req_s > 1 && req_ss != hw_ss_per_s)
1878 * If more than four (SScount bitfield limit) subslices are
1879 * requested then the number has to be even.
1881 if (req_ss > 4 && (req_ss & 1))
1885 * If only one slice is enabled and subslice count is below the
1886 * device full enablement, it must be at most half of the all
1887 * available subslices.
1889 if (req_s == 1 && req_ss < hw_ss_per_s &&
1890 req_ss > (hw_ss_per_s / 2))
1893 /* ABI restriction - VME use case only. */
1895 /* All slices or one slice only. */
1896 if (req_s != 1 && req_s != hw_s)
1900 * Half subslices or full enablement only when one slice is
1904 (req_ss != hw_ss_per_s && req_ss != (hw_ss_per_s / 2)))
1907 /* No EU configuration changes. */
1908 if ((user->min_eus_per_subslice !=
1909 device->max_eus_per_subslice) ||
1910 (user->max_eus_per_subslice !=
1911 device->max_eus_per_subslice))
1918 static int set_sseu(struct i915_gem_context *ctx,
1919 struct drm_i915_gem_context_param *args)
1921 struct drm_i915_private *i915 = ctx->i915;
1922 struct drm_i915_gem_context_param_sseu user_sseu;
1923 struct intel_context *ce;
1924 struct intel_sseu sseu;
1925 unsigned long lookup;
1928 if (args->size < sizeof(user_sseu))
1931 if (GRAPHICS_VER(i915) != 11)
1934 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
1941 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
1945 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
1946 lookup |= LOOKUP_USER_INDEX;
1948 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
1952 /* Only render engine supports RPCS configuration. */
1953 if (ce->engine->class != RENDER_CLASS) {
1958 ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu);
1962 ret = intel_context_reconfigure_sseu(ce, sseu);
1966 args->size = sizeof(user_sseu);
1969 intel_context_put(ce);
1974 set_persistence(struct i915_gem_context *ctx,
1975 const struct drm_i915_gem_context_param *args)
1980 return __context_set_persistence(ctx, args->value);
1983 static int set_priority(struct i915_gem_context *ctx,
1984 const struct drm_i915_gem_context_param *args)
1986 struct i915_gem_engines_iter it;
1987 struct intel_context *ce;
1990 err = validate_priority(ctx->i915, args);
1994 ctx->sched.priority = args->value;
1996 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1997 if (!intel_engine_has_timeslices(ce->engine))
2000 if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
2001 intel_engine_has_semaphores(ce->engine))
2002 intel_context_set_use_semaphores(ce);
2004 intel_context_clear_use_semaphores(ce);
2006 i915_gem_context_unlock_engines(ctx);
2011 static int get_protected(struct i915_gem_context *ctx,
2012 struct drm_i915_gem_context_param *args)
2015 args->value = i915_gem_context_uses_protected_content(ctx);
2020 static int ctx_setparam(struct drm_i915_file_private *fpriv,
2021 struct i915_gem_context *ctx,
2022 struct drm_i915_gem_context_param *args)
2026 switch (args->param) {
2027 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
2030 else if (args->value)
2031 i915_gem_context_set_no_error_capture(ctx);
2033 i915_gem_context_clear_no_error_capture(ctx);
2036 case I915_CONTEXT_PARAM_BANNABLE:
2039 else if (!capable(CAP_SYS_ADMIN) && !args->value)
2041 else if (args->value)
2042 i915_gem_context_set_bannable(ctx);
2043 else if (i915_gem_context_uses_protected_content(ctx))
2044 ret = -EPERM; /* can't clear this for protected contexts */
2046 i915_gem_context_clear_bannable(ctx);
2049 case I915_CONTEXT_PARAM_RECOVERABLE:
2052 else if (!args->value)
2053 i915_gem_context_clear_recoverable(ctx);
2054 else if (i915_gem_context_uses_protected_content(ctx))
2055 ret = -EPERM; /* can't set this for protected contexts */
2057 i915_gem_context_set_recoverable(ctx);
2060 case I915_CONTEXT_PARAM_PRIORITY:
2061 ret = set_priority(ctx, args);
2064 case I915_CONTEXT_PARAM_SSEU:
2065 ret = set_sseu(ctx, args);
2068 case I915_CONTEXT_PARAM_PERSISTENCE:
2069 ret = set_persistence(ctx, args);
2072 case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
2073 case I915_CONTEXT_PARAM_NO_ZEROMAP:
2074 case I915_CONTEXT_PARAM_BAN_PERIOD:
2075 case I915_CONTEXT_PARAM_RINGSIZE:
2076 case I915_CONTEXT_PARAM_VM:
2077 case I915_CONTEXT_PARAM_ENGINES:
2087 struct i915_gem_proto_context *pc;
2088 struct drm_i915_file_private *fpriv;
2091 static int create_setparam(struct i915_user_extension __user *ext, void *data)
2093 struct drm_i915_gem_context_create_ext_setparam local;
2094 const struct create_ext *arg = data;
2096 if (copy_from_user(&local, ext, sizeof(local)))
2099 if (local.param.ctx_id)
2102 return set_proto_ctx_param(arg->fpriv, arg->pc, &local.param);
2105 static int invalid_ext(struct i915_user_extension __user *ext, void *data)
2110 static const i915_user_extension_fn create_extensions[] = {
2111 [I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam,
2112 [I915_CONTEXT_CREATE_EXT_CLONE] = invalid_ext,
2115 static bool client_is_banned(struct drm_i915_file_private *file_priv)
2117 return atomic_read(&file_priv->ban_score) >= I915_CLIENT_SCORE_BANNED;
2120 static inline struct i915_gem_context *
2121 __context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2123 struct i915_gem_context *ctx;
2126 ctx = xa_load(&file_priv->context_xa, id);
2127 if (ctx && !kref_get_unless_zero(&ctx->ref))
2134 static struct i915_gem_context *
2135 finalize_create_context_locked(struct drm_i915_file_private *file_priv,
2136 struct i915_gem_proto_context *pc, u32 id)
2138 struct i915_gem_context *ctx;
2141 lockdep_assert_held(&file_priv->proto_context_lock);
2143 ctx = i915_gem_create_context(file_priv->dev_priv, pc);
2147 gem_context_register(ctx, file_priv, id);
2149 old = xa_erase(&file_priv->proto_context_xa, id);
2150 GEM_BUG_ON(old != pc);
2151 proto_context_close(file_priv->dev_priv, pc);
2153 /* One for the xarray and one for the caller */
2154 return i915_gem_context_get(ctx);
2157 struct i915_gem_context *
2158 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2160 struct i915_gem_proto_context *pc;
2161 struct i915_gem_context *ctx;
2163 ctx = __context_lookup(file_priv, id);
2167 mutex_lock(&file_priv->proto_context_lock);
2168 /* Try one more time under the lock */
2169 ctx = __context_lookup(file_priv, id);
2171 pc = xa_load(&file_priv->proto_context_xa, id);
2173 ctx = ERR_PTR(-ENOENT);
2175 ctx = finalize_create_context_locked(file_priv, pc, id);
2177 mutex_unlock(&file_priv->proto_context_lock);
2182 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2183 struct drm_file *file)
2185 struct drm_i915_private *i915 = to_i915(dev);
2186 struct drm_i915_gem_context_create_ext *args = data;
2187 struct create_ext ext_data;
2191 if (!DRIVER_CAPS(i915)->has_logical_contexts)
2194 if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN)
2197 ret = intel_gt_terminally_wedged(to_gt(i915));
2201 ext_data.fpriv = file->driver_priv;
2202 if (client_is_banned(ext_data.fpriv)) {
2204 "client %s[%d] banned from creating ctx\n",
2205 current->comm, task_pid_nr(current));
2209 ext_data.pc = proto_context_create(i915, args->flags);
2210 if (IS_ERR(ext_data.pc))
2211 return PTR_ERR(ext_data.pc);
2213 if (args->flags & I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS) {
2214 ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
2216 ARRAY_SIZE(create_extensions),
2222 if (GRAPHICS_VER(i915) > 12) {
2223 struct i915_gem_context *ctx;
2225 /* Get ourselves a context ID */
2226 ret = xa_alloc(&ext_data.fpriv->context_xa, &id, NULL,
2227 xa_limit_32b, GFP_KERNEL);
2231 ctx = i915_gem_create_context(i915, ext_data.pc);
2237 proto_context_close(i915, ext_data.pc);
2238 gem_context_register(ctx, ext_data.fpriv, id);
2240 ret = proto_context_register(ext_data.fpriv, ext_data.pc, &id);
2246 drm_dbg(&i915->drm, "HW context %d created\n", args->ctx_id);
2251 proto_context_close(i915, ext_data.pc);
2255 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2256 struct drm_file *file)
2258 struct drm_i915_gem_context_destroy *args = data;
2259 struct drm_i915_file_private *file_priv = file->driver_priv;
2260 struct i915_gem_proto_context *pc;
2261 struct i915_gem_context *ctx;
2269 /* We need to hold the proto-context lock here to prevent races
2270 * with finalize_create_context_locked().
2272 mutex_lock(&file_priv->proto_context_lock);
2273 ctx = xa_erase(&file_priv->context_xa, args->ctx_id);
2274 pc = xa_erase(&file_priv->proto_context_xa, args->ctx_id);
2275 mutex_unlock(&file_priv->proto_context_lock);
2279 GEM_WARN_ON(ctx && pc);
2282 proto_context_close(file_priv->dev_priv, pc);
2290 static int get_sseu(struct i915_gem_context *ctx,
2291 struct drm_i915_gem_context_param *args)
2293 struct drm_i915_gem_context_param_sseu user_sseu;
2294 struct intel_context *ce;
2295 unsigned long lookup;
2298 if (args->size == 0)
2300 else if (args->size < sizeof(user_sseu))
2303 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
2310 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
2314 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
2315 lookup |= LOOKUP_USER_INDEX;
2317 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
2321 err = intel_context_lock_pinned(ce); /* serialises with set_sseu */
2323 intel_context_put(ce);
2327 user_sseu.slice_mask = ce->sseu.slice_mask;
2328 user_sseu.subslice_mask = ce->sseu.subslice_mask;
2329 user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice;
2330 user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice;
2332 intel_context_unlock_pinned(ce);
2333 intel_context_put(ce);
2335 if (copy_to_user(u64_to_user_ptr(args->value), &user_sseu,
2340 args->size = sizeof(user_sseu);
2345 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2346 struct drm_file *file)
2348 struct drm_i915_file_private *file_priv = file->driver_priv;
2349 struct drm_i915_gem_context_param *args = data;
2350 struct i915_gem_context *ctx;
2351 struct i915_address_space *vm;
2354 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
2356 return PTR_ERR(ctx);
2358 switch (args->param) {
2359 case I915_CONTEXT_PARAM_GTT_SIZE:
2361 vm = i915_gem_context_get_eb_vm(ctx);
2362 args->value = vm->total;
2367 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
2369 args->value = i915_gem_context_no_error_capture(ctx);
2372 case I915_CONTEXT_PARAM_BANNABLE:
2374 args->value = i915_gem_context_is_bannable(ctx);
2377 case I915_CONTEXT_PARAM_RECOVERABLE:
2379 args->value = i915_gem_context_is_recoverable(ctx);
2382 case I915_CONTEXT_PARAM_PRIORITY:
2384 args->value = ctx->sched.priority;
2387 case I915_CONTEXT_PARAM_SSEU:
2388 ret = get_sseu(ctx, args);
2391 case I915_CONTEXT_PARAM_VM:
2392 ret = get_ppgtt(file_priv, ctx, args);
2395 case I915_CONTEXT_PARAM_PERSISTENCE:
2397 args->value = i915_gem_context_is_persistent(ctx);
2400 case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
2401 ret = get_protected(ctx, args);
2404 case I915_CONTEXT_PARAM_NO_ZEROMAP:
2405 case I915_CONTEXT_PARAM_BAN_PERIOD:
2406 case I915_CONTEXT_PARAM_ENGINES:
2407 case I915_CONTEXT_PARAM_RINGSIZE:
2413 i915_gem_context_put(ctx);
2417 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2418 struct drm_file *file)
2420 struct drm_i915_file_private *file_priv = file->driver_priv;
2421 struct drm_i915_gem_context_param *args = data;
2422 struct i915_gem_proto_context *pc;
2423 struct i915_gem_context *ctx;
2426 mutex_lock(&file_priv->proto_context_lock);
2427 ctx = __context_lookup(file_priv, args->ctx_id);
2429 pc = xa_load(&file_priv->proto_context_xa, args->ctx_id);
2431 /* Contexts should be finalized inside
2432 * GEM_CONTEXT_CREATE starting with graphics
2435 WARN_ON(GRAPHICS_VER(file_priv->dev_priv) > 12);
2436 ret = set_proto_ctx_param(file_priv, pc, args);
2441 mutex_unlock(&file_priv->proto_context_lock);
2444 ret = ctx_setparam(file_priv, ctx, args);
2445 i915_gem_context_put(ctx);
2451 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
2452 void *data, struct drm_file *file)
2454 struct drm_i915_private *i915 = to_i915(dev);
2455 struct drm_i915_reset_stats *args = data;
2456 struct i915_gem_context *ctx;
2458 if (args->flags || args->pad)
2461 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
2463 return PTR_ERR(ctx);
2466 * We opt for unserialised reads here. This may result in tearing
2467 * in the extremely unlikely event of a GPU hang on this context
2468 * as we are querying them. If we need that extra layer of protection,
2469 * we should wrap the hangstats with a seqlock.
2472 if (capable(CAP_SYS_ADMIN))
2473 args->reset_count = i915_reset_count(&i915->gpu_error);
2475 args->reset_count = 0;
2477 args->batch_active = atomic_read(&ctx->guilty_count);
2478 args->batch_pending = atomic_read(&ctx->active_count);
2480 i915_gem_context_put(ctx);
2484 /* GEM context-engines iterator: for_each_gem_engine() */
2485 struct intel_context *
2486 i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
2488 const struct i915_gem_engines *e = it->engines;
2489 struct intel_context *ctx;
2495 if (it->idx >= e->num_engines)
2498 ctx = e->engines[it->idx++];
2504 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2505 #include "selftests/mock_context.c"
2506 #include "selftests/i915_gem_context.c"
2509 void i915_gem_context_module_exit(void)
2511 kmem_cache_destroy(slab_luts);
2514 int __init i915_gem_context_module_init(void)
2516 slab_luts = KMEM_CACHE(i915_lut_handle, 0);