2 * SPDX-License-Identifier: MIT
4 * Copyright © 2011-2012 Intel Corporation
8 * This file implements HW context support. On gen5+ a HW context consists of an
9 * opaque GPU object which is referenced at times of context saves and restores.
10 * With RC6 enabled, the context is also referenced as the GPU enters and exists
11 * from RC6 (GPU has it's own internal power context, except on gen5). Though
12 * something like a context does exist for the media ring, the code only
13 * supports contexts for the render ring.
15 * In software, there is a distinction between contexts created by the user,
16 * and the default HW context. The default HW context is used by GPU clients
17 * that do not request setup of their own hardware context. The default
18 * context's state is never restored to help prevent programming errors. This
19 * would happen if a client ran and piggy-backed off another clients GPU state.
20 * The default context only exists to give the GPU some offset to load as the
21 * current to invoke a save of the context we actually care about. In fact, the
22 * code could likely be constructed, albeit in a more complicated fashion, to
23 * never use the default context, though that limits the driver's ability to
24 * swap out, and/or destroy other contexts.
26 * All other contexts are created as a request by the GPU client. These contexts
27 * store GPU state, and thus allow GPU clients to not re-emit state (and
28 * potentially query certain state) at any time. The kernel driver makes
29 * certain that the appropriate commands are inserted.
31 * The context life cycle is semi-complicated in that context BOs may live
32 * longer than the context itself because of the way the hardware, and object
33 * tracking works. Below is a very crude representation of the state machine
34 * describing the context life.
35 * refcount pincount active
36 * S0: initial state 0 0 0
37 * S1: context created 1 0 0
38 * S2: context is currently running 2 1 X
39 * S3: GPU referenced, but not current 2 0 1
40 * S4: context is current, but destroyed 1 1 0
41 * S5: like S3, but destroyed 1 0 1
43 * The most common (but not all) transitions:
44 * S0->S1: client creates a context
45 * S1->S2: client submits execbuf with context
46 * S2->S3: other clients submits execbuf with context
47 * S3->S1: context object was retired
48 * S3->S2: clients submits another execbuf
49 * S2->S4: context destroy called with current context
50 * S3->S5->S0: destroy path
51 * S4->S5->S0: destroy path on current context
53 * There are two confusing terms used above:
54 * The "current context" means the context which is currently running on the
55 * GPU. The GPU has loaded its state already and has stored away the gtt
56 * offset of the BO. The GPU is not actively referencing the data at this
57 * offset, but it will on the next context switch. The only way to avoid this
58 * is to do a GPU reset.
60 * An "active context' is one which was previously the "current context" and is
61 * on the active list waiting for the next context switch to occur. Until this
62 * happens, the object must remain at the same gtt offset. It is therefore
63 * possible to destroy a context, but it is still active.
67 #include <linux/log2.h>
68 #include <linux/nospec.h>
70 #include "gt/gen6_ppgtt.h"
71 #include "gt/intel_context.h"
72 #include "gt/intel_context_param.h"
73 #include "gt/intel_engine_heartbeat.h"
74 #include "gt/intel_engine_user.h"
75 #include "gt/intel_ring.h"
77 #include "i915_gem_context.h"
78 #include "i915_globals.h"
79 #include "i915_trace.h"
80 #include "i915_user_extensions.h"
82 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
84 static struct i915_global_gem_context {
85 struct i915_global base;
86 struct kmem_cache *slab_luts;
89 struct i915_lut_handle *i915_lut_handle_alloc(void)
91 return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
94 void i915_lut_handle_free(struct i915_lut_handle *lut)
96 return kmem_cache_free(global.slab_luts, lut);
99 static void lut_close(struct i915_gem_context *ctx)
101 struct radix_tree_iter iter;
104 lockdep_assert_held(&ctx->mutex);
107 radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
108 struct i915_vma *vma = rcu_dereference_raw(*slot);
109 struct drm_i915_gem_object *obj = vma->obj;
110 struct i915_lut_handle *lut;
112 if (!kref_get_unless_zero(&obj->base.refcount))
116 i915_gem_object_lock(obj);
117 list_for_each_entry(lut, &obj->lut_list, obj_link) {
121 if (lut->handle != iter.index)
124 list_del(&lut->obj_link);
127 i915_gem_object_unlock(obj);
130 if (&lut->obj_link != &obj->lut_list) {
131 i915_lut_handle_free(lut);
132 radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
133 if (atomic_dec_and_test(&vma->open_count) &&
134 !i915_vma_is_ggtt(vma))
136 i915_gem_object_put(obj);
139 i915_gem_object_put(obj);
144 static struct intel_context *
145 lookup_user_engine(struct i915_gem_context *ctx,
147 const struct i915_engine_class_instance *ci)
148 #define LOOKUP_USER_INDEX BIT(0)
152 if (!!(flags & LOOKUP_USER_INDEX) != i915_gem_context_user_engines(ctx))
153 return ERR_PTR(-EINVAL);
155 if (!i915_gem_context_user_engines(ctx)) {
156 struct intel_engine_cs *engine;
158 engine = intel_engine_lookup_user(ctx->i915,
160 ci->engine_instance);
162 return ERR_PTR(-EINVAL);
164 idx = engine->legacy_idx;
166 idx = ci->engine_instance;
169 return i915_gem_context_get_engine(ctx, idx);
172 static struct i915_address_space *
173 context_get_vm_rcu(struct i915_gem_context *ctx)
175 GEM_BUG_ON(!rcu_access_pointer(ctx->vm));
178 struct i915_address_space *vm;
181 * We do not allow downgrading from full-ppgtt [to a shared
182 * global gtt], so ctx->vm cannot become NULL.
184 vm = rcu_dereference(ctx->vm);
185 if (!kref_get_unless_zero(&vm->ref))
189 * This ppgtt may have be reallocated between
190 * the read and the kref, and reassigned to a third
191 * context. In order to avoid inadvertent sharing
192 * of this ppgtt with that third context (and not
193 * src), we have to confirm that we have the same
194 * ppgtt after passing through the strong memory
195 * barrier implied by a successful
196 * kref_get_unless_zero().
198 * Once we have acquired the current ppgtt of ctx,
199 * we no longer care if it is released from ctx, as
200 * it cannot be reallocated elsewhere.
203 if (vm == rcu_access_pointer(ctx->vm))
204 return rcu_pointer_handoff(vm);
210 static void intel_context_set_gem(struct intel_context *ce,
211 struct i915_gem_context *ctx)
213 GEM_BUG_ON(rcu_access_pointer(ce->gem_context));
214 RCU_INIT_POINTER(ce->gem_context, ctx);
216 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
217 ce->ring = __intel_context_ring_size(SZ_16K);
219 if (rcu_access_pointer(ctx->vm)) {
220 struct i915_address_space *vm;
223 vm = context_get_vm_rcu(ctx); /* hmm */
230 GEM_BUG_ON(ce->timeline);
232 ce->timeline = intel_timeline_get(ctx->timeline);
234 if (ctx->sched.priority >= I915_PRIORITY_NORMAL &&
235 intel_engine_has_semaphores(ce->engine))
236 __set_bit(CONTEXT_USE_SEMAPHORES, &ce->flags);
239 static void __free_engines(struct i915_gem_engines *e, unsigned int count)
242 if (!e->engines[count])
245 intel_context_put(e->engines[count]);
250 static void free_engines(struct i915_gem_engines *e)
252 __free_engines(e, e->num_engines);
255 static void free_engines_rcu(struct rcu_head *rcu)
257 struct i915_gem_engines *engines =
258 container_of(rcu, struct i915_gem_engines, rcu);
260 i915_sw_fence_fini(&engines->fence);
261 free_engines(engines);
264 static int __i915_sw_fence_call
265 engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
267 struct i915_gem_engines *engines =
268 container_of(fence, typeof(*engines), fence);
272 if (!list_empty(&engines->link)) {
273 struct i915_gem_context *ctx = engines->ctx;
276 spin_lock_irqsave(&ctx->stale.lock, flags);
277 list_del(&engines->link);
278 spin_unlock_irqrestore(&ctx->stale.lock, flags);
280 i915_gem_context_put(engines->ctx);
284 init_rcu_head(&engines->rcu);
285 call_rcu(&engines->rcu, free_engines_rcu);
292 static struct i915_gem_engines *alloc_engines(unsigned int count)
294 struct i915_gem_engines *e;
296 e = kzalloc(struct_size(e, engines, count), GFP_KERNEL);
300 i915_sw_fence_init(&e->fence, engines_notify);
304 static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
306 const struct intel_gt *gt = &ctx->i915->gt;
307 struct intel_engine_cs *engine;
308 struct i915_gem_engines *e;
309 enum intel_engine_id id;
311 e = alloc_engines(I915_NUM_ENGINES);
313 return ERR_PTR(-ENOMEM);
315 for_each_engine(engine, gt, id) {
316 struct intel_context *ce;
318 if (engine->legacy_idx == INVALID_ENGINE)
321 GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);
322 GEM_BUG_ON(e->engines[engine->legacy_idx]);
324 ce = intel_context_create(engine);
326 __free_engines(e, e->num_engines + 1);
330 intel_context_set_gem(ce, ctx);
332 e->engines[engine->legacy_idx] = ce;
333 e->num_engines = max(e->num_engines, engine->legacy_idx);
340 static void i915_gem_context_free(struct i915_gem_context *ctx)
342 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
344 spin_lock(&ctx->i915->gem.contexts.lock);
345 list_del(&ctx->link);
346 spin_unlock(&ctx->i915->gem.contexts.lock);
348 mutex_destroy(&ctx->engines_mutex);
351 intel_timeline_put(ctx->timeline);
354 mutex_destroy(&ctx->mutex);
359 static void contexts_free_all(struct llist_node *list)
361 struct i915_gem_context *ctx, *cn;
363 llist_for_each_entry_safe(ctx, cn, list, free_link)
364 i915_gem_context_free(ctx);
367 static void contexts_flush_free(struct i915_gem_contexts *gc)
369 contexts_free_all(llist_del_all(&gc->free_list));
372 static void contexts_free_worker(struct work_struct *work)
374 struct i915_gem_contexts *gc =
375 container_of(work, typeof(*gc), free_work);
377 contexts_flush_free(gc);
380 void i915_gem_context_release(struct kref *ref)
382 struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
383 struct i915_gem_contexts *gc = &ctx->i915->gem.contexts;
385 trace_i915_context_free(ctx);
386 if (llist_add(&ctx->free_link, &gc->free_list))
387 schedule_work(&gc->free_work);
390 static inline struct i915_gem_engines *
391 __context_engines_static(const struct i915_gem_context *ctx)
393 return rcu_dereference_protected(ctx->engines, true);
396 static bool __reset_engine(struct intel_engine_cs *engine)
398 struct intel_gt *gt = engine->gt;
399 bool success = false;
401 if (!intel_has_reset_engine(gt))
404 if (!test_and_set_bit(I915_RESET_ENGINE + engine->id,
406 success = intel_engine_reset(engine, NULL) == 0;
407 clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
414 static void __reset_context(struct i915_gem_context *ctx,
415 struct intel_engine_cs *engine)
417 intel_gt_handle_error(engine->gt, engine->mask, 0,
418 "context closure in %s", ctx->name);
421 static bool __cancel_engine(struct intel_engine_cs *engine)
424 * Send a "high priority pulse" down the engine to cause the
425 * current request to be momentarily preempted. (If it fails to
426 * be preempted, it will be reset). As we have marked our context
427 * as banned, any incomplete request, including any running, will
428 * be skipped following the preemption.
430 * If there is no hangchecking (one of the reasons why we try to
431 * cancel the context) and no forced preemption, there may be no
432 * means by which we reset the GPU and evict the persistent hog.
433 * Ergo if we are unable to inject a preemptive pulse that can
434 * kill the banned context, we fallback to doing a local reset
437 if (IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT) &&
438 !intel_engine_pulse(engine))
441 /* If we are unable to send a pulse, try resetting this engine. */
442 return __reset_engine(engine);
445 static struct intel_engine_cs *__active_engine(struct i915_request *rq)
447 struct intel_engine_cs *engine, *locked;
450 * Serialise with __i915_request_submit() so that it sees
451 * is-banned?, or we know the request is already inflight.
453 locked = READ_ONCE(rq->engine);
454 spin_lock_irq(&locked->active.lock);
455 while (unlikely(locked != (engine = READ_ONCE(rq->engine)))) {
456 spin_unlock(&locked->active.lock);
457 spin_lock(&engine->active.lock);
462 if (i915_request_is_active(rq) && rq->fence.error != -EIO)
465 spin_unlock_irq(&locked->active.lock);
470 static struct intel_engine_cs *active_engine(struct intel_context *ce)
472 struct intel_engine_cs *engine = NULL;
473 struct i915_request *rq;
478 mutex_lock(&ce->timeline->mutex);
479 list_for_each_entry_reverse(rq, &ce->timeline->requests, link) {
480 if (i915_request_completed(rq))
483 /* Check with the backend if the request is inflight */
484 engine = __active_engine(rq);
488 mutex_unlock(&ce->timeline->mutex);
493 static void kill_engines(struct i915_gem_engines *engines)
495 struct i915_gem_engines_iter it;
496 struct intel_context *ce;
499 * Map the user's engine back to the actual engines; one virtual
500 * engine will be mapped to multiple engines, and using ctx->engine[]
501 * the same engine may be have multiple instances in the user's map.
502 * However, we only care about pending requests, so only include
503 * engines on which there are incomplete requests.
505 for_each_gem_engine(ce, engines, it) {
506 struct intel_engine_cs *engine;
508 if (intel_context_set_banned(ce))
512 * Check the current active state of this context; if we
513 * are currently executing on the GPU we need to evict
514 * ourselves. On the other hand, if we haven't yet been
515 * submitted to the GPU or if everything is complete,
516 * we have nothing to do.
518 engine = active_engine(ce);
520 /* First attempt to gracefully cancel the context */
521 if (engine && !__cancel_engine(engine))
523 * If we are unable to send a preemptive pulse to bump
524 * the context from the GPU, we have to resort to a full
525 * reset. We hope the collateral damage is worth it.
527 __reset_context(engines->ctx, engine);
531 static void kill_stale_engines(struct i915_gem_context *ctx)
533 struct i915_gem_engines *pos, *next;
535 spin_lock_irq(&ctx->stale.lock);
536 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
537 list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
538 if (!i915_sw_fence_await(&pos->fence)) {
539 list_del_init(&pos->link);
543 spin_unlock_irq(&ctx->stale.lock);
547 spin_lock_irq(&ctx->stale.lock);
548 GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
549 list_safe_reset_next(pos, next, link);
550 list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
552 i915_sw_fence_complete(&pos->fence);
554 spin_unlock_irq(&ctx->stale.lock);
557 static void kill_context(struct i915_gem_context *ctx)
559 kill_stale_engines(ctx);
562 static void engines_idle_release(struct i915_gem_context *ctx,
563 struct i915_gem_engines *engines)
565 struct i915_gem_engines_iter it;
566 struct intel_context *ce;
568 INIT_LIST_HEAD(&engines->link);
570 engines->ctx = i915_gem_context_get(ctx);
572 for_each_gem_engine(ce, engines, it) {
575 /* serialises with execbuf */
576 set_bit(CONTEXT_CLOSED_BIT, &ce->flags);
577 if (!intel_context_pin_if_active(ce))
580 /* Wait until context is finally scheduled out and retired */
581 err = i915_sw_fence_await_active(&engines->fence,
583 I915_ACTIVE_AWAIT_BARRIER);
584 intel_context_unpin(ce);
589 spin_lock_irq(&ctx->stale.lock);
590 if (!i915_gem_context_is_closed(ctx))
591 list_add_tail(&engines->link, &ctx->stale.engines);
592 spin_unlock_irq(&ctx->stale.lock);
595 if (list_empty(&engines->link)) /* raced, already closed */
596 kill_engines(engines);
598 i915_sw_fence_commit(&engines->fence);
601 static void set_closed_name(struct i915_gem_context *ctx)
605 /* Replace '[]' with '<>' to indicate closed in debug prints */
607 s = strrchr(ctx->name, '[');
613 s = strchr(s + 1, ']');
618 static void context_close(struct i915_gem_context *ctx)
620 struct i915_address_space *vm;
622 /* Flush any concurrent set_engines() */
623 mutex_lock(&ctx->engines_mutex);
624 engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
625 i915_gem_context_set_closed(ctx);
626 mutex_unlock(&ctx->engines_mutex);
628 mutex_lock(&ctx->mutex);
630 set_closed_name(ctx);
632 vm = i915_gem_context_vm(ctx);
636 ctx->file_priv = ERR_PTR(-EBADF);
639 * The LUT uses the VMA as a backpointer to unref the object,
640 * so we need to clear the LUT before we close all the VMA (inside
645 mutex_unlock(&ctx->mutex);
648 * If the user has disabled hangchecking, we can not be sure that
649 * the batches will ever complete after the context is closed,
650 * keeping the context and all resources pinned forever. So in this
651 * case we opt to forcibly kill off all remaining requests on
654 if (!i915_gem_context_is_persistent(ctx) ||
655 !i915_modparams.enable_hangcheck)
658 i915_gem_context_put(ctx);
661 static int __context_set_persistence(struct i915_gem_context *ctx, bool state)
663 if (i915_gem_context_is_persistent(ctx) == state)
668 * Only contexts that are short-lived [that will expire or be
669 * reset] are allowed to survive past termination. We require
670 * hangcheck to ensure that the persistent requests are healthy.
672 if (!i915_modparams.enable_hangcheck)
675 i915_gem_context_set_persistence(ctx);
677 /* To cancel a context we use "preempt-to-idle" */
678 if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
682 * If the cancel fails, we then need to reset, cleanly!
684 * If the per-engine reset fails, all hope is lost! We resort
685 * to a full GPU reset in that unlikely case, but realistically
686 * if the engine could not reset, the full reset does not fare
687 * much better. The damage has been done.
689 * However, if we cannot reset an engine by itself, we cannot
690 * cleanup a hanging persistent context without causing
691 * colateral damage, and we should not pretend we can by
692 * exposing the interface.
694 if (!intel_has_reset_engine(&ctx->i915->gt))
697 i915_gem_context_clear_persistence(ctx);
703 static struct i915_gem_context *
704 __create_context(struct drm_i915_private *i915)
706 struct i915_gem_context *ctx;
707 struct i915_gem_engines *e;
711 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
713 return ERR_PTR(-ENOMEM);
715 kref_init(&ctx->ref);
717 ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
718 mutex_init(&ctx->mutex);
720 spin_lock_init(&ctx->stale.lock);
721 INIT_LIST_HEAD(&ctx->stale.engines);
723 mutex_init(&ctx->engines_mutex);
724 e = default_engines(ctx);
729 RCU_INIT_POINTER(ctx->engines, e);
731 INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
733 /* NB: Mark all slices as needing a remap so that when the context first
734 * loads it will restore whatever remap state already exists. If there
735 * is no remap info, it will be a NOP. */
736 ctx->remap_slice = ALL_L3_SLICES(i915);
738 i915_gem_context_set_bannable(ctx);
739 i915_gem_context_set_recoverable(ctx);
740 __context_set_persistence(ctx, true /* cgroup hook? */);
742 for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
743 ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
745 spin_lock(&i915->gem.contexts.lock);
746 list_add_tail(&ctx->link, &i915->gem.contexts.list);
747 spin_unlock(&i915->gem.contexts.lock);
756 static inline struct i915_gem_engines *
757 __context_engines_await(const struct i915_gem_context *ctx)
759 struct i915_gem_engines *engines;
763 engines = rcu_dereference(ctx->engines);
764 GEM_BUG_ON(!engines);
766 if (unlikely(!i915_sw_fence_await(&engines->fence)))
769 if (likely(engines == rcu_access_pointer(ctx->engines)))
772 i915_sw_fence_complete(&engines->fence);
780 context_apply_all(struct i915_gem_context *ctx,
781 int (*fn)(struct intel_context *ce, void *data),
784 struct i915_gem_engines_iter it;
785 struct i915_gem_engines *e;
786 struct intel_context *ce;
789 e = __context_engines_await(ctx);
790 for_each_gem_engine(ce, e, it) {
795 i915_sw_fence_complete(&e->fence);
800 static int __apply_ppgtt(struct intel_context *ce, void *vm)
803 ce->vm = i915_vm_get(vm);
807 static struct i915_address_space *
808 __set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
810 struct i915_address_space *old;
812 old = rcu_replace_pointer(ctx->vm,
814 lockdep_is_held(&ctx->mutex));
815 GEM_BUG_ON(old && i915_vm_is_4lvl(vm) != i915_vm_is_4lvl(old));
817 context_apply_all(ctx, __apply_ppgtt, vm);
822 static void __assign_ppgtt(struct i915_gem_context *ctx,
823 struct i915_address_space *vm)
825 if (vm == rcu_access_pointer(ctx->vm))
828 vm = __set_ppgtt(ctx, vm);
833 static void __set_timeline(struct intel_timeline **dst,
834 struct intel_timeline *src)
836 struct intel_timeline *old = *dst;
838 *dst = src ? intel_timeline_get(src) : NULL;
841 intel_timeline_put(old);
844 static int __apply_timeline(struct intel_context *ce, void *timeline)
846 __set_timeline(&ce->timeline, timeline);
850 static void __assign_timeline(struct i915_gem_context *ctx,
851 struct intel_timeline *timeline)
853 __set_timeline(&ctx->timeline, timeline);
854 context_apply_all(ctx, __apply_timeline, timeline);
857 static struct i915_gem_context *
858 i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
860 struct i915_gem_context *ctx;
862 if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE &&
863 !HAS_EXECLISTS(i915))
864 return ERR_PTR(-EINVAL);
866 /* Reap the stale contexts */
867 contexts_flush_free(&i915->gem.contexts);
869 ctx = __create_context(i915);
873 if (HAS_FULL_PPGTT(i915)) {
874 struct i915_ppgtt *ppgtt;
876 ppgtt = i915_ppgtt_create(&i915->gt);
878 drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
881 return ERR_CAST(ppgtt);
884 mutex_lock(&ctx->mutex);
885 __assign_ppgtt(ctx, &ppgtt->vm);
886 mutex_unlock(&ctx->mutex);
888 i915_vm_put(&ppgtt->vm);
891 if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
892 struct intel_timeline *timeline;
894 timeline = intel_timeline_create(&i915->gt, NULL);
895 if (IS_ERR(timeline)) {
897 return ERR_CAST(timeline);
900 __assign_timeline(ctx, timeline);
901 intel_timeline_put(timeline);
904 trace_i915_context_create(ctx);
909 static void init_contexts(struct i915_gem_contexts *gc)
911 spin_lock_init(&gc->lock);
912 INIT_LIST_HEAD(&gc->list);
914 INIT_WORK(&gc->free_work, contexts_free_worker);
915 init_llist_head(&gc->free_list);
918 void i915_gem_init__contexts(struct drm_i915_private *i915)
920 init_contexts(&i915->gem.contexts);
921 drm_dbg(&i915->drm, "%s context support initialized\n",
922 DRIVER_CAPS(i915)->has_logical_contexts ?
926 void i915_gem_driver_release__contexts(struct drm_i915_private *i915)
928 flush_work(&i915->gem.contexts.free_work);
929 rcu_barrier(); /* and flush the left over RCU frees */
932 static int gem_context_register(struct i915_gem_context *ctx,
933 struct drm_i915_file_private *fpriv,
936 struct i915_address_space *vm;
939 ctx->file_priv = fpriv;
941 mutex_lock(&ctx->mutex);
942 vm = i915_gem_context_vm(ctx);
944 WRITE_ONCE(vm->file, fpriv); /* XXX */
945 mutex_unlock(&ctx->mutex);
947 ctx->pid = get_task_pid(current, PIDTYPE_PID);
948 snprintf(ctx->name, sizeof(ctx->name), "%s[%d]",
949 current->comm, pid_nr(ctx->pid));
951 /* And finally expose ourselves to userspace via the idr */
952 ret = xa_alloc(&fpriv->context_xa, id, ctx, xa_limit_32b, GFP_KERNEL);
954 put_pid(fetch_and_zero(&ctx->pid));
959 int i915_gem_context_open(struct drm_i915_private *i915,
960 struct drm_file *file)
962 struct drm_i915_file_private *file_priv = file->driver_priv;
963 struct i915_gem_context *ctx;
967 xa_init_flags(&file_priv->context_xa, XA_FLAGS_ALLOC);
969 /* 0 reserved for invalid/unassigned ppgtt */
970 xa_init_flags(&file_priv->vm_xa, XA_FLAGS_ALLOC1);
972 ctx = i915_gem_create_context(i915, 0);
978 err = gem_context_register(ctx, file_priv, &id);
988 xa_destroy(&file_priv->vm_xa);
989 xa_destroy(&file_priv->context_xa);
993 void i915_gem_context_close(struct drm_file *file)
995 struct drm_i915_file_private *file_priv = file->driver_priv;
996 struct drm_i915_private *i915 = file_priv->dev_priv;
997 struct i915_address_space *vm;
998 struct i915_gem_context *ctx;
1001 xa_for_each(&file_priv->context_xa, idx, ctx)
1003 xa_destroy(&file_priv->context_xa);
1005 xa_for_each(&file_priv->vm_xa, idx, vm)
1007 xa_destroy(&file_priv->vm_xa);
1009 contexts_flush_free(&i915->gem.contexts);
1012 int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
1013 struct drm_file *file)
1015 struct drm_i915_private *i915 = to_i915(dev);
1016 struct drm_i915_gem_vm_control *args = data;
1017 struct drm_i915_file_private *file_priv = file->driver_priv;
1018 struct i915_ppgtt *ppgtt;
1022 if (!HAS_FULL_PPGTT(i915))
1028 ppgtt = i915_ppgtt_create(&i915->gt);
1030 return PTR_ERR(ppgtt);
1032 ppgtt->vm.file = file_priv;
1034 if (args->extensions) {
1035 err = i915_user_extensions(u64_to_user_ptr(args->extensions),
1042 err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm,
1043 xa_limit_32b, GFP_KERNEL);
1047 GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
1052 i915_vm_put(&ppgtt->vm);
1056 int i915_gem_vm_destroy_ioctl(struct drm_device *dev, void *data,
1057 struct drm_file *file)
1059 struct drm_i915_file_private *file_priv = file->driver_priv;
1060 struct drm_i915_gem_vm_control *args = data;
1061 struct i915_address_space *vm;
1066 if (args->extensions)
1069 vm = xa_erase(&file_priv->vm_xa, args->vm_id);
1077 struct context_barrier_task {
1078 struct i915_active base;
1079 void (*task)(void *data);
1084 static void cb_retire(struct i915_active *base)
1086 struct context_barrier_task *cb = container_of(base, typeof(*cb), base);
1091 i915_active_fini(&cb->base);
1095 I915_SELFTEST_DECLARE(static intel_engine_mask_t context_barrier_inject_fault);
1096 static int context_barrier_task(struct i915_gem_context *ctx,
1097 intel_engine_mask_t engines,
1098 bool (*skip)(struct intel_context *ce, void *data),
1099 int (*emit)(struct i915_request *rq, void *data),
1100 void (*task)(void *data),
1103 struct context_barrier_task *cb;
1104 struct i915_gem_engines_iter it;
1105 struct i915_gem_engines *e;
1106 struct intel_context *ce;
1111 cb = kmalloc(sizeof(*cb), GFP_KERNEL);
1115 i915_active_init(&cb->base, NULL, cb_retire);
1116 err = i915_active_acquire(&cb->base);
1122 e = __context_engines_await(ctx);
1124 i915_active_release(&cb->base);
1128 for_each_gem_engine(ce, e, it) {
1129 struct i915_request *rq;
1131 if (I915_SELFTEST_ONLY(context_barrier_inject_fault &
1132 ce->engine->mask)) {
1137 if (!(ce->engine->mask & engines))
1140 if (skip && skip(ce, data))
1143 rq = intel_context_create_request(ce);
1151 err = emit(rq, data);
1153 err = i915_active_add_request(&cb->base, rq);
1155 i915_request_add(rq);
1159 i915_sw_fence_complete(&e->fence);
1161 cb->task = err ? NULL : task; /* caller needs to unwind instead */
1164 i915_active_release(&cb->base);
1169 static int get_ppgtt(struct drm_i915_file_private *file_priv,
1170 struct i915_gem_context *ctx,
1171 struct drm_i915_gem_context_param *args)
1173 struct i915_address_space *vm;
1177 if (!rcu_access_pointer(ctx->vm))
1181 vm = context_get_vm_rcu(ctx);
1186 err = xa_alloc(&file_priv->vm_xa, &id, vm, xa_limit_32b, GFP_KERNEL);
1192 GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
1201 static void set_ppgtt_barrier(void *data)
1203 struct i915_address_space *old = data;
1205 if (INTEL_GEN(old->i915) < 8)
1206 gen6_ppgtt_unpin_all(i915_vm_to_ppgtt(old));
1211 static int emit_ppgtt_update(struct i915_request *rq, void *data)
1213 struct i915_address_space *vm = rq->context->vm;
1214 struct intel_engine_cs *engine = rq->engine;
1215 u32 base = engine->mmio_base;
1219 if (i915_vm_is_4lvl(vm)) {
1220 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1221 const dma_addr_t pd_daddr = px_dma(ppgtt->pd);
1223 cs = intel_ring_begin(rq, 6);
1227 *cs++ = MI_LOAD_REGISTER_IMM(2);
1229 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
1230 *cs++ = upper_32_bits(pd_daddr);
1231 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
1232 *cs++ = lower_32_bits(pd_daddr);
1235 intel_ring_advance(rq, cs);
1236 } else if (HAS_LOGICAL_RING_CONTEXTS(engine->i915)) {
1237 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1240 /* Magic required to prevent forcewake errors! */
1241 err = engine->emit_flush(rq, EMIT_INVALIDATE);
1245 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
1249 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
1250 for (i = GEN8_3LVL_PDPES; i--; ) {
1251 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1253 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
1254 *cs++ = upper_32_bits(pd_daddr);
1255 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
1256 *cs++ = lower_32_bits(pd_daddr);
1259 intel_ring_advance(rq, cs);
1265 static bool skip_ppgtt_update(struct intel_context *ce, void *data)
1267 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
1270 if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
1273 if (!atomic_read(&ce->pin_count))
1276 /* ppGTT is not part of the legacy context image */
1277 if (gen6_ppgtt_pin(i915_vm_to_ppgtt(ce->vm)))
1283 static int set_ppgtt(struct drm_i915_file_private *file_priv,
1284 struct i915_gem_context *ctx,
1285 struct drm_i915_gem_context_param *args)
1287 struct i915_address_space *vm, *old;
1293 if (!rcu_access_pointer(ctx->vm))
1296 if (upper_32_bits(args->value))
1300 vm = xa_load(&file_priv->vm_xa, args->value);
1301 if (vm && !kref_get_unless_zero(&vm->ref))
1307 err = mutex_lock_interruptible(&ctx->mutex);
1311 if (i915_gem_context_is_closed(ctx)) {
1316 if (vm == rcu_access_pointer(ctx->vm))
1319 /* Teardown the existing obj:vma cache, it will have to be rebuilt. */
1322 old = __set_ppgtt(ctx, vm);
1325 * We need to flush any requests using the current ppgtt before
1326 * we release it as the requests do not hold a reference themselves,
1327 * only indirectly through the context.
1329 err = context_barrier_task(ctx, ALL_ENGINES,
1335 i915_vm_close(__set_ppgtt(ctx, old));
1340 mutex_unlock(&ctx->mutex);
1346 static int __apply_ringsize(struct intel_context *ce, void *sz)
1348 return intel_context_set_ring_size(ce, (unsigned long)sz);
1351 static int set_ringsize(struct i915_gem_context *ctx,
1352 struct drm_i915_gem_context_param *args)
1354 if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
1360 if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE))
1363 if (args->value < I915_GTT_PAGE_SIZE)
1366 if (args->value > 128 * I915_GTT_PAGE_SIZE)
1369 return context_apply_all(ctx,
1371 __intel_context_ring_size(args->value));
1374 static int __get_ringsize(struct intel_context *ce, void *arg)
1378 sz = intel_context_get_ring_size(ce);
1379 GEM_BUG_ON(sz > INT_MAX);
1381 return sz; /* stop on first engine */
1384 static int get_ringsize(struct i915_gem_context *ctx,
1385 struct drm_i915_gem_context_param *args)
1389 if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915))
1395 sz = context_apply_all(ctx, __get_ringsize, NULL);
1404 i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
1405 const struct drm_i915_gem_context_param_sseu *user,
1406 struct intel_sseu *context)
1408 const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
1410 /* No zeros in any field. */
1411 if (!user->slice_mask || !user->subslice_mask ||
1412 !user->min_eus_per_subslice || !user->max_eus_per_subslice)
1416 if (user->max_eus_per_subslice < user->min_eus_per_subslice)
1420 * Some future proofing on the types since the uAPI is wider than the
1421 * current internal implementation.
1423 if (overflows_type(user->slice_mask, context->slice_mask) ||
1424 overflows_type(user->subslice_mask, context->subslice_mask) ||
1425 overflows_type(user->min_eus_per_subslice,
1426 context->min_eus_per_subslice) ||
1427 overflows_type(user->max_eus_per_subslice,
1428 context->max_eus_per_subslice))
1431 /* Check validity against hardware. */
1432 if (user->slice_mask & ~device->slice_mask)
1435 if (user->subslice_mask & ~device->subslice_mask[0])
1438 if (user->max_eus_per_subslice > device->max_eus_per_subslice)
1441 context->slice_mask = user->slice_mask;
1442 context->subslice_mask = user->subslice_mask;
1443 context->min_eus_per_subslice = user->min_eus_per_subslice;
1444 context->max_eus_per_subslice = user->max_eus_per_subslice;
1446 /* Part specific restrictions. */
1447 if (IS_GEN(i915, 11)) {
1448 unsigned int hw_s = hweight8(device->slice_mask);
1449 unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
1450 unsigned int req_s = hweight8(context->slice_mask);
1451 unsigned int req_ss = hweight8(context->subslice_mask);
1454 * Only full subslice enablement is possible if more than one
1455 * slice is turned on.
1457 if (req_s > 1 && req_ss != hw_ss_per_s)
1461 * If more than four (SScount bitfield limit) subslices are
1462 * requested then the number has to be even.
1464 if (req_ss > 4 && (req_ss & 1))
1468 * If only one slice is enabled and subslice count is below the
1469 * device full enablement, it must be at most half of the all
1470 * available subslices.
1472 if (req_s == 1 && req_ss < hw_ss_per_s &&
1473 req_ss > (hw_ss_per_s / 2))
1476 /* ABI restriction - VME use case only. */
1478 /* All slices or one slice only. */
1479 if (req_s != 1 && req_s != hw_s)
1483 * Half subslices or full enablement only when one slice is
1487 (req_ss != hw_ss_per_s && req_ss != (hw_ss_per_s / 2)))
1490 /* No EU configuration changes. */
1491 if ((user->min_eus_per_subslice !=
1492 device->max_eus_per_subslice) ||
1493 (user->max_eus_per_subslice !=
1494 device->max_eus_per_subslice))
1501 static int set_sseu(struct i915_gem_context *ctx,
1502 struct drm_i915_gem_context_param *args)
1504 struct drm_i915_private *i915 = ctx->i915;
1505 struct drm_i915_gem_context_param_sseu user_sseu;
1506 struct intel_context *ce;
1507 struct intel_sseu sseu;
1508 unsigned long lookup;
1511 if (args->size < sizeof(user_sseu))
1514 if (!IS_GEN(i915, 11))
1517 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
1524 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
1528 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
1529 lookup |= LOOKUP_USER_INDEX;
1531 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
1535 /* Only render engine supports RPCS configuration. */
1536 if (ce->engine->class != RENDER_CLASS) {
1541 ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu);
1545 ret = intel_context_reconfigure_sseu(ce, sseu);
1549 args->size = sizeof(user_sseu);
1552 intel_context_put(ce);
1556 struct set_engines {
1557 struct i915_gem_context *ctx;
1558 struct i915_gem_engines *engines;
1562 set_engines__load_balance(struct i915_user_extension __user *base, void *data)
1564 struct i915_context_engines_load_balance __user *ext =
1565 container_of_user(base, typeof(*ext), base);
1566 const struct set_engines *set = data;
1567 struct drm_i915_private *i915 = set->ctx->i915;
1568 struct intel_engine_cs *stack[16];
1569 struct intel_engine_cs **siblings;
1570 struct intel_context *ce;
1571 u16 num_siblings, idx;
1575 if (!HAS_EXECLISTS(i915))
1578 if (intel_uc_uses_guc_submission(&i915->gt.uc))
1579 return -ENODEV; /* not implement yet */
1581 if (get_user(idx, &ext->engine_index))
1584 if (idx >= set->engines->num_engines) {
1585 drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
1586 idx, set->engines->num_engines);
1590 idx = array_index_nospec(idx, set->engines->num_engines);
1591 if (set->engines->engines[idx]) {
1593 "Invalid placement[%d], already occupied\n", idx);
1597 if (get_user(num_siblings, &ext->num_siblings))
1600 err = check_user_mbz(&ext->flags);
1604 err = check_user_mbz(&ext->mbz64);
1609 if (num_siblings > ARRAY_SIZE(stack)) {
1610 siblings = kmalloc_array(num_siblings,
1617 for (n = 0; n < num_siblings; n++) {
1618 struct i915_engine_class_instance ci;
1620 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
1625 siblings[n] = intel_engine_lookup_user(i915,
1627 ci.engine_instance);
1630 "Invalid sibling[%d]: { class:%d, inst:%d }\n",
1631 n, ci.engine_class, ci.engine_instance);
1637 ce = intel_execlists_create_virtual(siblings, n);
1643 intel_context_set_gem(ce, set->ctx);
1645 if (cmpxchg(&set->engines->engines[idx], NULL, ce)) {
1646 intel_context_put(ce);
1652 if (siblings != stack)
1659 set_engines__bond(struct i915_user_extension __user *base, void *data)
1661 struct i915_context_engines_bond __user *ext =
1662 container_of_user(base, typeof(*ext), base);
1663 const struct set_engines *set = data;
1664 struct drm_i915_private *i915 = set->ctx->i915;
1665 struct i915_engine_class_instance ci;
1666 struct intel_engine_cs *virtual;
1667 struct intel_engine_cs *master;
1671 if (get_user(idx, &ext->virtual_index))
1674 if (idx >= set->engines->num_engines) {
1676 "Invalid index for virtual engine: %d >= %d\n",
1677 idx, set->engines->num_engines);
1681 idx = array_index_nospec(idx, set->engines->num_engines);
1682 if (!set->engines->engines[idx]) {
1683 drm_dbg(&i915->drm, "Invalid engine at %d\n", idx);
1686 virtual = set->engines->engines[idx]->engine;
1688 err = check_user_mbz(&ext->flags);
1692 for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
1693 err = check_user_mbz(&ext->mbz64[n]);
1698 if (copy_from_user(&ci, &ext->master, sizeof(ci)))
1701 master = intel_engine_lookup_user(i915,
1702 ci.engine_class, ci.engine_instance);
1705 "Unrecognised master engine: { class:%u, instance:%u }\n",
1706 ci.engine_class, ci.engine_instance);
1710 if (get_user(num_bonds, &ext->num_bonds))
1713 for (n = 0; n < num_bonds; n++) {
1714 struct intel_engine_cs *bond;
1716 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci)))
1719 bond = intel_engine_lookup_user(i915,
1721 ci.engine_instance);
1724 "Unrecognised engine[%d] for bonding: { class:%d, instance: %d }\n",
1725 n, ci.engine_class, ci.engine_instance);
1730 * A non-virtual engine has no siblings to choose between; and
1731 * a submit fence will always be directed to the one engine.
1733 if (intel_engine_is_virtual(virtual)) {
1734 err = intel_virtual_engine_attach_bond(virtual,
1745 static const i915_user_extension_fn set_engines__extensions[] = {
1746 [I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_engines__load_balance,
1747 [I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
1751 set_engines(struct i915_gem_context *ctx,
1752 const struct drm_i915_gem_context_param *args)
1754 struct drm_i915_private *i915 = ctx->i915;
1755 struct i915_context_param_engines __user *user =
1756 u64_to_user_ptr(args->value);
1757 struct set_engines set = { .ctx = ctx };
1758 unsigned int num_engines, n;
1762 if (!args->size) { /* switch back to legacy user_ring_map */
1763 if (!i915_gem_context_user_engines(ctx))
1766 set.engines = default_engines(ctx);
1767 if (IS_ERR(set.engines))
1768 return PTR_ERR(set.engines);
1773 BUILD_BUG_ON(!IS_ALIGNED(sizeof(*user), sizeof(*user->engines)));
1774 if (args->size < sizeof(*user) ||
1775 !IS_ALIGNED(args->size, sizeof(*user->engines))) {
1776 drm_dbg(&i915->drm, "Invalid size for engine array: %d\n",
1782 * Note that I915_EXEC_RING_MASK limits execbuf to only using the
1783 * first 64 engines defined here.
1785 num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines);
1786 set.engines = alloc_engines(num_engines);
1790 for (n = 0; n < num_engines; n++) {
1791 struct i915_engine_class_instance ci;
1792 struct intel_engine_cs *engine;
1793 struct intel_context *ce;
1795 if (copy_from_user(&ci, &user->engines[n], sizeof(ci))) {
1796 __free_engines(set.engines, n);
1800 if (ci.engine_class == (u16)I915_ENGINE_CLASS_INVALID &&
1801 ci.engine_instance == (u16)I915_ENGINE_CLASS_INVALID_NONE) {
1802 set.engines->engines[n] = NULL;
1806 engine = intel_engine_lookup_user(ctx->i915,
1808 ci.engine_instance);
1811 "Invalid engine[%d]: { class:%d, instance:%d }\n",
1812 n, ci.engine_class, ci.engine_instance);
1813 __free_engines(set.engines, n);
1817 ce = intel_context_create(engine);
1819 __free_engines(set.engines, n);
1823 intel_context_set_gem(ce, ctx);
1825 set.engines->engines[n] = ce;
1827 set.engines->num_engines = num_engines;
1830 if (!get_user(extensions, &user->extensions))
1831 err = i915_user_extensions(u64_to_user_ptr(extensions),
1832 set_engines__extensions,
1833 ARRAY_SIZE(set_engines__extensions),
1836 free_engines(set.engines);
1841 mutex_lock(&ctx->engines_mutex);
1842 if (i915_gem_context_is_closed(ctx)) {
1843 mutex_unlock(&ctx->engines_mutex);
1844 free_engines(set.engines);
1848 i915_gem_context_set_user_engines(ctx);
1850 i915_gem_context_clear_user_engines(ctx);
1851 set.engines = rcu_replace_pointer(ctx->engines, set.engines, 1);
1852 mutex_unlock(&ctx->engines_mutex);
1854 /* Keep track of old engine sets for kill_context() */
1855 engines_idle_release(ctx, set.engines);
1860 static struct i915_gem_engines *
1861 __copy_engines(struct i915_gem_engines *e)
1863 struct i915_gem_engines *copy;
1866 copy = alloc_engines(e->num_engines);
1868 return ERR_PTR(-ENOMEM);
1870 for (n = 0; n < e->num_engines; n++) {
1872 copy->engines[n] = intel_context_get(e->engines[n]);
1874 copy->engines[n] = NULL;
1876 copy->num_engines = n;
1882 get_engines(struct i915_gem_context *ctx,
1883 struct drm_i915_gem_context_param *args)
1885 struct i915_context_param_engines __user *user;
1886 struct i915_gem_engines *e;
1887 size_t n, count, size;
1890 err = mutex_lock_interruptible(&ctx->engines_mutex);
1895 if (i915_gem_context_user_engines(ctx))
1896 e = __copy_engines(i915_gem_context_engines(ctx));
1897 mutex_unlock(&ctx->engines_mutex);
1898 if (IS_ERR_OR_NULL(e)) {
1900 return PTR_ERR_OR_ZERO(e);
1903 count = e->num_engines;
1905 /* Be paranoid in case we have an impedance mismatch */
1906 if (!check_struct_size(user, engines, count, &size)) {
1910 if (overflows_type(size, args->size)) {
1920 if (args->size < size) {
1925 user = u64_to_user_ptr(args->value);
1926 if (!access_ok(user, size)) {
1931 if (put_user(0, &user->extensions)) {
1936 for (n = 0; n < count; n++) {
1937 struct i915_engine_class_instance ci = {
1938 .engine_class = I915_ENGINE_CLASS_INVALID,
1939 .engine_instance = I915_ENGINE_CLASS_INVALID_NONE,
1942 if (e->engines[n]) {
1943 ci.engine_class = e->engines[n]->engine->uabi_class;
1944 ci.engine_instance = e->engines[n]->engine->uabi_instance;
1947 if (copy_to_user(&user->engines[n], &ci, sizeof(ci))) {
1961 set_persistence(struct i915_gem_context *ctx,
1962 const struct drm_i915_gem_context_param *args)
1967 return __context_set_persistence(ctx, args->value);
1970 static int __apply_priority(struct intel_context *ce, void *arg)
1972 struct i915_gem_context *ctx = arg;
1974 if (!intel_engine_has_semaphores(ce->engine))
1977 if (ctx->sched.priority >= I915_PRIORITY_NORMAL)
1978 intel_context_set_use_semaphores(ce);
1980 intel_context_clear_use_semaphores(ce);
1985 static int set_priority(struct i915_gem_context *ctx,
1986 const struct drm_i915_gem_context_param *args)
1988 s64 priority = args->value;
1993 if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
1996 if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
1997 priority < I915_CONTEXT_MIN_USER_PRIORITY)
2000 if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
2001 !capable(CAP_SYS_NICE))
2004 ctx->sched.priority = I915_USER_PRIORITY(priority);
2005 context_apply_all(ctx, __apply_priority, ctx);
2010 static int ctx_setparam(struct drm_i915_file_private *fpriv,
2011 struct i915_gem_context *ctx,
2012 struct drm_i915_gem_context_param *args)
2016 switch (args->param) {
2017 case I915_CONTEXT_PARAM_NO_ZEROMAP:
2020 else if (args->value)
2021 set_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
2023 clear_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
2026 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
2029 else if (args->value)
2030 i915_gem_context_set_no_error_capture(ctx);
2032 i915_gem_context_clear_no_error_capture(ctx);
2035 case I915_CONTEXT_PARAM_BANNABLE:
2038 else if (!capable(CAP_SYS_ADMIN) && !args->value)
2040 else if (args->value)
2041 i915_gem_context_set_bannable(ctx);
2043 i915_gem_context_clear_bannable(ctx);
2046 case I915_CONTEXT_PARAM_RECOVERABLE:
2049 else if (args->value)
2050 i915_gem_context_set_recoverable(ctx);
2052 i915_gem_context_clear_recoverable(ctx);
2055 case I915_CONTEXT_PARAM_PRIORITY:
2056 ret = set_priority(ctx, args);
2059 case I915_CONTEXT_PARAM_SSEU:
2060 ret = set_sseu(ctx, args);
2063 case I915_CONTEXT_PARAM_VM:
2064 ret = set_ppgtt(fpriv, ctx, args);
2067 case I915_CONTEXT_PARAM_ENGINES:
2068 ret = set_engines(ctx, args);
2071 case I915_CONTEXT_PARAM_PERSISTENCE:
2072 ret = set_persistence(ctx, args);
2075 case I915_CONTEXT_PARAM_RINGSIZE:
2076 ret = set_ringsize(ctx, args);
2079 case I915_CONTEXT_PARAM_BAN_PERIOD:
2089 struct i915_gem_context *ctx;
2090 struct drm_i915_file_private *fpriv;
2093 static int create_setparam(struct i915_user_extension __user *ext, void *data)
2095 struct drm_i915_gem_context_create_ext_setparam local;
2096 const struct create_ext *arg = data;
2098 if (copy_from_user(&local, ext, sizeof(local)))
2101 if (local.param.ctx_id)
2104 return ctx_setparam(arg->fpriv, arg->ctx, &local.param);
2107 static int copy_ring_size(struct intel_context *dst,
2108 struct intel_context *src)
2112 sz = intel_context_get_ring_size(src);
2116 return intel_context_set_ring_size(dst, sz);
2119 static int clone_engines(struct i915_gem_context *dst,
2120 struct i915_gem_context *src)
2122 struct i915_gem_engines *e = i915_gem_context_lock_engines(src);
2123 struct i915_gem_engines *clone;
2127 clone = alloc_engines(e->num_engines);
2131 for (n = 0; n < e->num_engines; n++) {
2132 struct intel_engine_cs *engine;
2134 if (!e->engines[n]) {
2135 clone->engines[n] = NULL;
2138 engine = e->engines[n]->engine;
2141 * Virtual engines are singletons; they can only exist
2142 * inside a single context, because they embed their
2143 * HW context... As each virtual context implies a single
2144 * timeline (each engine can only dequeue a single request
2145 * at any time), it would be surprising for two contexts
2146 * to use the same engine. So let's create a copy of
2147 * the virtual engine instead.
2149 if (intel_engine_is_virtual(engine))
2151 intel_execlists_clone_virtual(engine);
2153 clone->engines[n] = intel_context_create(engine);
2154 if (IS_ERR_OR_NULL(clone->engines[n])) {
2155 __free_engines(clone, n);
2159 intel_context_set_gem(clone->engines[n], dst);
2161 /* Copy across the preferred ringsize */
2162 if (copy_ring_size(clone->engines[n], e->engines[n])) {
2163 __free_engines(clone, n + 1);
2167 clone->num_engines = n;
2169 user_engines = i915_gem_context_user_engines(src);
2170 i915_gem_context_unlock_engines(src);
2172 /* Serialised by constructor */
2173 engines_idle_release(dst, rcu_replace_pointer(dst->engines, clone, 1));
2175 i915_gem_context_set_user_engines(dst);
2177 i915_gem_context_clear_user_engines(dst);
2181 i915_gem_context_unlock_engines(src);
2185 static int clone_flags(struct i915_gem_context *dst,
2186 struct i915_gem_context *src)
2188 dst->user_flags = src->user_flags;
2192 static int clone_schedattr(struct i915_gem_context *dst,
2193 struct i915_gem_context *src)
2195 dst->sched = src->sched;
2199 static int clone_sseu(struct i915_gem_context *dst,
2200 struct i915_gem_context *src)
2202 struct i915_gem_engines *e = i915_gem_context_lock_engines(src);
2203 struct i915_gem_engines *clone;
2207 /* no locking required; sole access under constructor*/
2208 clone = __context_engines_static(dst);
2209 if (e->num_engines != clone->num_engines) {
2214 for (n = 0; n < e->num_engines; n++) {
2215 struct intel_context *ce = e->engines[n];
2217 if (clone->engines[n]->engine->class != ce->engine->class) {
2218 /* Must have compatible engine maps! */
2223 /* serialises with set_sseu */
2224 err = intel_context_lock_pinned(ce);
2228 clone->engines[n]->sseu = ce->sseu;
2229 intel_context_unlock_pinned(ce);
2234 i915_gem_context_unlock_engines(src);
2238 static int clone_timeline(struct i915_gem_context *dst,
2239 struct i915_gem_context *src)
2242 __assign_timeline(dst, src->timeline);
2247 static int clone_vm(struct i915_gem_context *dst,
2248 struct i915_gem_context *src)
2250 struct i915_address_space *vm;
2253 if (!rcu_access_pointer(src->vm))
2257 vm = context_get_vm_rcu(src);
2260 if (!mutex_lock_interruptible(&dst->mutex)) {
2261 __assign_ppgtt(dst, vm);
2262 mutex_unlock(&dst->mutex);
2271 static int create_clone(struct i915_user_extension __user *ext, void *data)
2273 static int (* const fn[])(struct i915_gem_context *dst,
2274 struct i915_gem_context *src) = {
2275 #define MAP(x, y) [ilog2(I915_CONTEXT_CLONE_##x)] = y
2276 MAP(ENGINES, clone_engines),
2277 MAP(FLAGS, clone_flags),
2278 MAP(SCHEDATTR, clone_schedattr),
2279 MAP(SSEU, clone_sseu),
2280 MAP(TIMELINE, clone_timeline),
2284 struct drm_i915_gem_context_create_ext_clone local;
2285 const struct create_ext *arg = data;
2286 struct i915_gem_context *dst = arg->ctx;
2287 struct i915_gem_context *src;
2290 if (copy_from_user(&local, ext, sizeof(local)))
2293 BUILD_BUG_ON(GENMASK(BITS_PER_TYPE(local.flags) - 1, ARRAY_SIZE(fn)) !=
2294 I915_CONTEXT_CLONE_UNKNOWN);
2296 if (local.flags & I915_CONTEXT_CLONE_UNKNOWN)
2303 src = __i915_gem_context_lookup_rcu(arg->fpriv, local.clone_id);
2308 GEM_BUG_ON(src == dst);
2310 for (bit = 0; bit < ARRAY_SIZE(fn); bit++) {
2311 if (!(local.flags & BIT(bit)))
2314 err = fn[bit](dst, src);
2322 static const i915_user_extension_fn create_extensions[] = {
2323 [I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam,
2324 [I915_CONTEXT_CREATE_EXT_CLONE] = create_clone,
2327 static bool client_is_banned(struct drm_i915_file_private *file_priv)
2329 return atomic_read(&file_priv->ban_score) >= I915_CLIENT_SCORE_BANNED;
2332 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2333 struct drm_file *file)
2335 struct drm_i915_private *i915 = to_i915(dev);
2336 struct drm_i915_gem_context_create_ext *args = data;
2337 struct create_ext ext_data;
2341 if (!DRIVER_CAPS(i915)->has_logical_contexts)
2344 if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN)
2347 ret = intel_gt_terminally_wedged(&i915->gt);
2351 ext_data.fpriv = file->driver_priv;
2352 if (client_is_banned(ext_data.fpriv)) {
2354 "client %s[%d] banned from creating ctx\n",
2355 current->comm, task_pid_nr(current));
2359 ext_data.ctx = i915_gem_create_context(i915, args->flags);
2360 if (IS_ERR(ext_data.ctx))
2361 return PTR_ERR(ext_data.ctx);
2363 if (args->flags & I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS) {
2364 ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
2366 ARRAY_SIZE(create_extensions),
2372 ret = gem_context_register(ext_data.ctx, ext_data.fpriv, &id);
2377 drm_dbg(&i915->drm, "HW context %d created\n", args->ctx_id);
2382 context_close(ext_data.ctx);
2386 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2387 struct drm_file *file)
2389 struct drm_i915_gem_context_destroy *args = data;
2390 struct drm_i915_file_private *file_priv = file->driver_priv;
2391 struct i915_gem_context *ctx;
2399 ctx = xa_erase(&file_priv->context_xa, args->ctx_id);
2407 static int get_sseu(struct i915_gem_context *ctx,
2408 struct drm_i915_gem_context_param *args)
2410 struct drm_i915_gem_context_param_sseu user_sseu;
2411 struct intel_context *ce;
2412 unsigned long lookup;
2415 if (args->size == 0)
2417 else if (args->size < sizeof(user_sseu))
2420 if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
2427 if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
2431 if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
2432 lookup |= LOOKUP_USER_INDEX;
2434 ce = lookup_user_engine(ctx, lookup, &user_sseu.engine);
2438 err = intel_context_lock_pinned(ce); /* serialises with set_sseu */
2440 intel_context_put(ce);
2444 user_sseu.slice_mask = ce->sseu.slice_mask;
2445 user_sseu.subslice_mask = ce->sseu.subslice_mask;
2446 user_sseu.min_eus_per_subslice = ce->sseu.min_eus_per_subslice;
2447 user_sseu.max_eus_per_subslice = ce->sseu.max_eus_per_subslice;
2449 intel_context_unlock_pinned(ce);
2450 intel_context_put(ce);
2452 if (copy_to_user(u64_to_user_ptr(args->value), &user_sseu,
2457 args->size = sizeof(user_sseu);
2462 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2463 struct drm_file *file)
2465 struct drm_i915_file_private *file_priv = file->driver_priv;
2466 struct drm_i915_gem_context_param *args = data;
2467 struct i915_gem_context *ctx;
2470 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
2474 switch (args->param) {
2475 case I915_CONTEXT_PARAM_NO_ZEROMAP:
2477 args->value = test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags);
2480 case I915_CONTEXT_PARAM_GTT_SIZE:
2483 if (rcu_access_pointer(ctx->vm))
2484 args->value = rcu_dereference(ctx->vm)->total;
2486 args->value = to_i915(dev)->ggtt.vm.total;
2490 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
2492 args->value = i915_gem_context_no_error_capture(ctx);
2495 case I915_CONTEXT_PARAM_BANNABLE:
2497 args->value = i915_gem_context_is_bannable(ctx);
2500 case I915_CONTEXT_PARAM_RECOVERABLE:
2502 args->value = i915_gem_context_is_recoverable(ctx);
2505 case I915_CONTEXT_PARAM_PRIORITY:
2507 args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT;
2510 case I915_CONTEXT_PARAM_SSEU:
2511 ret = get_sseu(ctx, args);
2514 case I915_CONTEXT_PARAM_VM:
2515 ret = get_ppgtt(file_priv, ctx, args);
2518 case I915_CONTEXT_PARAM_ENGINES:
2519 ret = get_engines(ctx, args);
2522 case I915_CONTEXT_PARAM_PERSISTENCE:
2524 args->value = i915_gem_context_is_persistent(ctx);
2527 case I915_CONTEXT_PARAM_RINGSIZE:
2528 ret = get_ringsize(ctx, args);
2531 case I915_CONTEXT_PARAM_BAN_PERIOD:
2537 i915_gem_context_put(ctx);
2541 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2542 struct drm_file *file)
2544 struct drm_i915_file_private *file_priv = file->driver_priv;
2545 struct drm_i915_gem_context_param *args = data;
2546 struct i915_gem_context *ctx;
2549 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
2553 ret = ctx_setparam(file_priv, ctx, args);
2555 i915_gem_context_put(ctx);
2559 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
2560 void *data, struct drm_file *file)
2562 struct drm_i915_private *i915 = to_i915(dev);
2563 struct drm_i915_reset_stats *args = data;
2564 struct i915_gem_context *ctx;
2567 if (args->flags || args->pad)
2572 ctx = __i915_gem_context_lookup_rcu(file->driver_priv, args->ctx_id);
2577 * We opt for unserialised reads here. This may result in tearing
2578 * in the extremely unlikely event of a GPU hang on this context
2579 * as we are querying them. If we need that extra layer of protection,
2580 * we should wrap the hangstats with a seqlock.
2583 if (capable(CAP_SYS_ADMIN))
2584 args->reset_count = i915_reset_count(&i915->gpu_error);
2586 args->reset_count = 0;
2588 args->batch_active = atomic_read(&ctx->guilty_count);
2589 args->batch_pending = atomic_read(&ctx->active_count);
2597 /* GEM context-engines iterator: for_each_gem_engine() */
2598 struct intel_context *
2599 i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
2601 const struct i915_gem_engines *e = it->engines;
2602 struct intel_context *ctx;
2608 if (it->idx >= e->num_engines)
2611 ctx = e->engines[it->idx++];
2617 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2618 #include "selftests/mock_context.c"
2619 #include "selftests/i915_gem_context.c"
2622 static void i915_global_gem_context_shrink(void)
2624 kmem_cache_shrink(global.slab_luts);
2627 static void i915_global_gem_context_exit(void)
2629 kmem_cache_destroy(global.slab_luts);
2632 static struct i915_global_gem_context global = { {
2633 .shrink = i915_global_gem_context_shrink,
2634 .exit = i915_global_gem_context_exit,
2637 int __init i915_global_gem_context_init(void)
2639 global.slab_luts = KMEM_CACHE(i915_lut_handle, 0);
2640 if (!global.slab_luts)
2643 i915_global_register(&global.base);