drivers/gpu/drm/i915/gem/i915_gem_clflush.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2016 Intel Corporation
   5  */
   6
   7 #include "display/intel_frontbuffer.h"
   8
   9 #include "i915_drv.h"
  10 #include "i915_gem_clflush.h"
  11 #include "i915_sw_fence_work.h"
  12 #include "i915_trace.h"
  13
  14 struct clflush {
  15         struct dma_fence_work base;
  16         struct drm_i915_gem_object *obj;
  17 };
  18
  19 static void __do_clflush(struct drm_i915_gem_object *obj)
  20 {
  21         GEM_BUG_ON(!i915_gem_object_has_pages(obj));
  22         drm_clflush_sg(obj->mm.pages);
  23
  24         i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
  25 }
  26
  27 static int clflush_work(struct dma_fence_work *base)
  28 {
  29         struct clflush *clflush = container_of(base, typeof(*clflush), base);
  30
  31         __do_clflush(clflush->obj);
  32
  33         return 0;
  34 }
  35
  36 static void clflush_release(struct dma_fence_work *base)
  37 {
  38         struct clflush *clflush = container_of(base, typeof(*clflush), base);
  39
  40         i915_gem_object_unpin_pages(clflush->obj);
  41         i915_gem_object_put(clflush->obj);
  42 }
  43
  44 static const struct dma_fence_work_ops clflush_ops = {
  45         .name = "clflush",
  46         .work = clflush_work,
  47         .release = clflush_release,
  48 };
  49
  50 static struct clflush *clflush_work_create(struct drm_i915_gem_object *obj)
  51 {
  52         struct clflush *clflush;
  53
  54         GEM_BUG_ON(!obj->cache_dirty);
  55
  56         clflush = kmalloc(sizeof(*clflush), GFP_KERNEL);
  57         if (!clflush)
  58                 return NULL;
  59
  60         if (__i915_gem_object_get_pages(obj) < 0) {
  61                 kfree(clflush);
  62                 return NULL;
  63         }
  64
  65         dma_fence_work_init(&clflush->base, &clflush_ops);
  66         clflush->obj = i915_gem_object_get(obj); /* obj <-> clflush cycle */
  67
  68         return clflush;
  69 }
  70
  71 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
  72                              unsigned int flags)
  73 {
  74         struct clflush *clflush;
  75
  76         assert_object_held(obj);
  77
  78         /*
  79          * Stolen memory is always coherent with the GPU as it is explicitly
  80          * marked as wc by the system, or the system is cache-coherent.
  81          * Similarly, we only access struct pages through the CPU cache, so
  82          * anything not backed by physical memory we consider to be always
  83          * coherent and not need clflushing.
  84          */
  85         if (!i915_gem_object_has_struct_page(obj)) {
  86                 obj->cache_dirty = false;
  87                 return false;
  88         }
  89
  90         /* If the GPU is snooping the contents of the CPU cache,
  91          * we do not need to manually clear the CPU cache lines.  However,
  92          * the caches are only snooped when the render cache is
  93          * flushed/invalidated.  As we always have to emit invalidations
  94          * and flushes when moving into and out of the RENDER domain, correct
  95          * snooping behaviour occurs naturally as the result of our domain
  96          * tracking.
  97          */
  98         if (!(flags & I915_CLFLUSH_FORCE) &&
  99             obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
 100                 return false;
 101
 102         trace_i915_gem_object_clflush(obj);
 103
 104         clflush = NULL;
 105         if (!(flags & I915_CLFLUSH_SYNC))
 106                 clflush = clflush_work_create(obj);
 107         if (clflush) {
 108                 i915_sw_fence_await_reservation(&clflush->base.chain,
 109                                                 obj->base.resv, NULL, true,
 110                                                 i915_fence_timeout(to_i915(obj->base.dev)),
 111                                                 I915_FENCE_GFP);
 112                 dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma);
 113                 dma_fence_work_commit(&clflush->base);
 114         } else if (obj->mm.pages) {
 115                 __do_clflush(obj);
 116         } else {
 117                 GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
 118         }
 119
 120         obj->cache_dirty = false;
 121         return true;
 122 }