2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Shobhit Kumar <shobhit.kumar@intel.com>
25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
28 #include <linux/kernel.h>
31 #include "intel_drv.h"
32 #include "intel_dsi.h"
33 #include "intel_sideband.h"
35 static const u16 lfsr_converts[] = {
36 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
37 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
38 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
39 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
42 /* Get DSI clock from pixel clock */
43 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
47 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
49 /* DSI data rate = pixel clock * bits per pixel / lane count
50 pixel clock is converted from KHz to Hz */
51 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
56 static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
57 struct intel_crtc_state *config,
60 unsigned int m_min, m_max, p_min = 2, p_max = 6;
62 unsigned int calc_m, calc_p;
65 /* target_dsi_clk is expected in kHz */
66 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
67 DRM_ERROR("DSI CLK Out of Range\n");
71 if (IS_CHERRYVIEW(dev_priv)) {
85 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
87 for (m = m_min; m <= m_max && delta; m++) {
88 for (p = p_min; p <= p_max && delta; p++) {
90 * Find the optimal m and p divisors with minimal delta
91 * +/- the required clock
93 int calc_dsi_clk = (m * ref_clk) / (p * n);
94 int d = abs(target_dsi_clk - calc_dsi_clk);
103 /* register has log2(N1), this works fine for powers of two */
104 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
105 config->dsi_pll.div =
106 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
107 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
113 * XXX: The muxing and gating is hard coded for now. Need to add support for
114 * sharing PLLs with two DSI outputs.
116 int vlv_dsi_pll_compute(struct intel_encoder *encoder,
117 struct intel_crtc_state *config)
119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
120 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
124 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
125 intel_dsi->lane_count);
127 ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
129 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
133 if (intel_dsi->ports & (1 << PORT_A))
134 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
136 if (intel_dsi->ports & (1 << PORT_C))
137 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
139 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
141 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
142 config->dsi_pll.div, config->dsi_pll.ctrl);
147 void vlv_dsi_pll_enable(struct intel_encoder *encoder,
148 const struct intel_crtc_state *config)
150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
154 vlv_cck_get(dev_priv);
156 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
157 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
158 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
159 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
161 /* wait at least 0.5 us after ungating before enabling VCO,
162 * allow hrtimer subsystem optimization by relaxing timing
164 usleep_range(10, 50);
166 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
168 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
171 vlv_cck_put(dev_priv);
172 DRM_ERROR("DSI PLL lock failed\n");
175 vlv_cck_put(dev_priv);
177 DRM_DEBUG_KMS("DSI PLL locked\n");
180 void vlv_dsi_pll_disable(struct intel_encoder *encoder)
182 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
187 vlv_cck_get(dev_priv);
189 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
190 tmp &= ~DSI_PLL_VCO_EN;
191 tmp |= DSI_PLL_LDO_GATE;
192 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
194 vlv_cck_put(dev_priv);
197 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
203 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
204 val = I915_READ(BXT_DSI_PLL_ENABLE);
205 enabled = (val & mask) == mask;
211 * Dividers must be programmed with valid values. As per BSEPC, for
212 * GEMINLAKE only PORT A divider values are checked while for BXT
213 * both divider values are validated. Check this here for
214 * paranoia, since BIOS is known to misconfigure PLLs in this way at
215 * times, and since accessing DSI registers with invalid dividers
216 * causes a system hang.
218 val = I915_READ(BXT_DSI_PLL_CTL);
219 if (IS_GEMINILAKE(dev_priv)) {
220 if (!(val & BXT_DSIA_16X_MASK)) {
221 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
225 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
226 DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
234 void bxt_dsi_pll_disable(struct intel_encoder *encoder)
236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
241 val = I915_READ(BXT_DSI_PLL_ENABLE);
242 val &= ~BXT_DSI_PLL_DO_ENABLE;
243 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
246 * PLL lock should deassert within 200us.
247 * Wait up to 1ms before timing out.
249 if (intel_wait_for_register(&dev_priv->uncore,
254 DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
257 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
258 struct intel_crtc_state *config)
260 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
261 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
262 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
264 u32 pll_ctl, pll_div;
266 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
271 vlv_cck_get(dev_priv);
272 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
273 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
274 vlv_cck_put(dev_priv);
276 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
277 config->dsi_pll.div = pll_div;
279 /* mask out other bits and extract the P1 divisor */
280 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
281 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
284 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
285 n = 1 << n; /* register has log2(N1) */
287 /* mask out the other bits and extract the M1 divisor */
288 pll_div &= DSI_PLL_M1_DIV_MASK;
289 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
292 pll_ctl = pll_ctl >> 1;
298 DRM_ERROR("wrong P1 divisor\n");
302 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
303 if (lfsr_converts[i] == pll_div)
307 if (i == ARRAY_SIZE(lfsr_converts)) {
308 DRM_ERROR("wrong m_seed programmed\n");
314 dsi_clock = (m * refclk) / (p * n);
316 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
321 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
322 struct intel_crtc_state *config)
327 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
329 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
331 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
333 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
335 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
337 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
339 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
343 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
346 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
347 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
349 temp = I915_READ(MIPI_CTRL(port));
350 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
351 I915_WRITE(MIPI_CTRL(port), temp |
352 intel_dsi->escape_clk_div <<
353 ESCAPE_CLOCK_DIVIDER_SHIFT);
356 static void glk_dsi_program_esc_clock(struct drm_device *dev,
357 const struct intel_crtc_state *config)
359 struct drm_i915_private *dev_priv = to_i915(dev);
368 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
370 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
372 ddr_clk = dsi_rate / 2;
374 /* Variable divider value */
375 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
377 /* Calculate TXESC1 divider */
378 if (div1_value <= 10)
379 txesc1_div = div1_value;
380 else if ((div1_value > 10) && (div1_value <= 20))
381 txesc1_div = DIV_ROUND_UP(div1_value, 2);
382 else if ((div1_value > 20) && (div1_value <= 30))
383 txesc1_div = DIV_ROUND_UP(div1_value, 4);
384 else if ((div1_value > 30) && (div1_value <= 40))
385 txesc1_div = DIV_ROUND_UP(div1_value, 6);
386 else if ((div1_value > 40) && (div1_value <= 50))
387 txesc1_div = DIV_ROUND_UP(div1_value, 8);
391 /* Calculate TXESC2 divider */
392 div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
395 txesc2_div = div2_value;
399 I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
400 I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
403 /* Program BXT Mipi clocks and dividers */
404 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
405 const struct intel_crtc_state *config)
407 struct drm_i915_private *dev_priv = to_i915(dev);
415 u32 mipi_8by3_divider;
417 /* Clear old configurations */
418 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
419 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
420 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
421 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
422 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
424 /* Get the current DSI rate(actual) */
425 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
426 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
429 * tx clock should be <= 20MHz and the div value must be
430 * subtracted by 1 as per bspec
432 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
434 * rx clock should be <= 150MHz and the div value must be
435 * subtracted by 1 as per bspec
437 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
440 * rx divider value needs to be updated in the
441 * two differnt bit fields in the register hence splitting the
442 * rx divider value accordingly
444 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
445 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
447 mipi_8by3_divider = 0x2;
449 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
450 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
451 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
452 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
454 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
457 int bxt_dsi_pll_compute(struct intel_encoder *encoder,
458 struct intel_crtc_state *config)
460 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
461 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
462 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
465 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
466 intel_dsi->lane_count);
469 * From clock diagram, to get PLL ratio divider, divide double of DSI
470 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
471 * round 'up' the result
473 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
475 if (IS_BROXTON(dev_priv)) {
476 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
477 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
479 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
480 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
483 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
484 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
487 DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
490 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
491 * Spec says both have to be programmed, even if one is not getting
492 * used. Configure MIPI_CLOCK_CTL dividers in modeset
494 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
496 /* As per recommendation from hardware team,
497 * Prog PVD ratio =1 if dsi ratio <= 50
499 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
500 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
505 void bxt_dsi_pll_enable(struct intel_encoder *encoder,
506 const struct intel_crtc_state *config)
508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
509 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
515 /* Configure PLL vales */
516 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
517 POSTING_READ(BXT_DSI_PLL_CTL);
519 /* Program TX, RX, Dphy clocks */
520 if (IS_BROXTON(dev_priv)) {
521 for_each_dsi_port(port, intel_dsi->ports)
522 bxt_dsi_program_clocks(encoder->base.dev, port, config);
524 glk_dsi_program_esc_clock(encoder->base.dev, config);
528 val = I915_READ(BXT_DSI_PLL_ENABLE);
529 val |= BXT_DSI_PLL_DO_ENABLE;
530 I915_WRITE(BXT_DSI_PLL_ENABLE, val);
532 /* Timeout and fail if PLL not locked */
533 if (intel_wait_for_register(&dev_priv->uncore,
538 DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
542 DRM_DEBUG_KMS("DSI PLL locked\n");
545 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
548 struct drm_device *dev = encoder->base.dev;
549 struct drm_i915_private *dev_priv = to_i915(dev);
551 /* Clear old configurations */
552 if (IS_BROXTON(dev_priv)) {
553 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
554 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
555 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
556 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
557 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
558 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
560 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
561 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
562 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
564 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
565 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
566 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
568 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);