drivers/gpu/drm/i915/display/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_mipi_dsi.h>
  32
  33 #include "i915_drv.h"
  34 #include "intel_atomic.h"
  35 #include "intel_connector.h"
  36 #include "intel_display_types.h"
  37 #include "intel_dsi.h"
  38 #include "intel_fifo_underrun.h"
  39 #include "intel_panel.h"
  40 #include "intel_sideband.h"
  41 #include "skl_scaler.h"
  42
  43 /* return pixels in terms of txbyteclkhs */
  44 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  45                        u16 burst_mode_ratio)
  46 {
  47         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  48                                          8 * 100), lane_count);
  49 }
  50
  51 /* return pixels equvalent to txbyteclkhs */
  52 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  53                         u16 burst_mode_ratio)
  54 {
  55         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  56                                                 (bpp * burst_mode_ratio));
  57 }
  58
  59 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  60 {
  61         /* It just so happens the VBT matches register contents. */
  62         switch (fmt) {
  63         case VID_MODE_FORMAT_RGB888:
  64                 return MIPI_DSI_FMT_RGB888;
  65         case VID_MODE_FORMAT_RGB666:
  66                 return MIPI_DSI_FMT_RGB666;
  67         case VID_MODE_FORMAT_RGB666_PACKED:
  68                 return MIPI_DSI_FMT_RGB666_PACKED;
  69         case VID_MODE_FORMAT_RGB565:
  70                 return MIPI_DSI_FMT_RGB565;
  71         default:
  72                 MISSING_CASE(fmt);
  73                 return MIPI_DSI_FMT_RGB666;
  74         }
  75 }
  76
  77 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  78 {
  79         struct drm_encoder *encoder = &intel_dsi->base.base;
  80         struct drm_device *dev = encoder->dev;
  81         struct drm_i915_private *dev_priv = to_i915(dev);
  82         u32 mask;
  83
  84         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  85                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  86
  87         if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
  88                                   mask, 100))
  89                 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
  90 }
  91
  92 static void write_data(struct drm_i915_private *dev_priv,
  93                        i915_reg_t reg,
  94                        const u8 *data, u32 len)
  95 {
  96         u32 i, j;
  97
  98         for (i = 0; i < len; i += 4) {
  99                 u32 val = 0;
 100
 101                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 102                         val |= *data++ << 8 * j;
 103
 104                 intel_de_write(dev_priv, reg, val);
 105         }
 106 }
 107
 108 static void read_data(struct drm_i915_private *dev_priv,
 109                       i915_reg_t reg,
 110                       u8 *data, u32 len)
 111 {
 112         u32 i, j;
 113
 114         for (i = 0; i < len; i += 4) {
 115                 u32 val = intel_de_read(dev_priv, reg);
 116
 117                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 118                         *data++ = val >> 8 * j;
 119         }
 120 }
 121
 122 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 123                                        const struct mipi_dsi_msg *msg)
 124 {
 125         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 126         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 127         struct drm_i915_private *dev_priv = to_i915(dev);
 128         enum port port = intel_dsi_host->port;
 129         struct mipi_dsi_packet packet;
 130         ssize_t ret;
 131         const u8 *header, *data;
 132         i915_reg_t data_reg, ctrl_reg;
 133         u32 data_mask, ctrl_mask;
 134
 135         ret = mipi_dsi_create_packet(&packet, msg);
 136         if (ret < 0)
 137                 return ret;
 138
 139         header = packet.header;
 140         data = packet.payload;
 141
 142         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 143                 data_reg = MIPI_LP_GEN_DATA(port);
 144                 data_mask = LP_DATA_FIFO_FULL;
 145                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 146                 ctrl_mask = LP_CTRL_FIFO_FULL;
 147         } else {
 148                 data_reg = MIPI_HS_GEN_DATA(port);
 149                 data_mask = HS_DATA_FIFO_FULL;
 150                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 151                 ctrl_mask = HS_CTRL_FIFO_FULL;
 152         }
 153
 154         /* note: this is never true for reads */
 155         if (packet.payload_length) {
 156                 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 157                                             data_mask, 50))
 158                         drm_err(&dev_priv->drm,
 159                                 "Timeout waiting for HS/LP DATA FIFO !full\n");
 160
 161                 write_data(dev_priv, data_reg, packet.payload,
 162                            packet.payload_length);
 163         }
 164
 165         if (msg->rx_len) {
 166                 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
 167                                GEN_READ_DATA_AVAIL);
 168         }
 169
 170         if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 171                                     ctrl_mask, 50)) {
 172                 drm_err(&dev_priv->drm,
 173                         "Timeout waiting for HS/LP CTRL FIFO !full\n");
 174         }
 175
 176         intel_de_write(dev_priv, ctrl_reg,
 177                        header[2] << 16 | header[1] << 8 | header[0]);
 178
 179         /* ->rx_len is set only for reads */
 180         if (msg->rx_len) {
 181                 data_mask = GEN_READ_DATA_AVAIL;
 182                 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
 183                                           data_mask, 50))
 184                         drm_err(&dev_priv->drm,
 185                                 "Timeout waiting for read data.\n");
 186
 187                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 188         }
 189
 190         /* XXX: fix for reads and writes */
 191         return 4 + packet.payload_length;
 192 }
 193
 194 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 195                                  struct mipi_dsi_device *dsi)
 196 {
 197         return 0;
 198 }
 199
 200 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 201                                  struct mipi_dsi_device *dsi)
 202 {
 203         return 0;
 204 }
 205
 206 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 207         .attach = intel_dsi_host_attach,
 208         .detach = intel_dsi_host_detach,
 209         .transfer = intel_dsi_host_transfer,
 210 };
 211
 212 /*
 213  * send a video mode command
 214  *
 215  * XXX: commands with data in MIPI_DPI_DATA?
 216  */
 217 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 218                         enum port port)
 219 {
 220         struct drm_encoder *encoder = &intel_dsi->base.base;
 221         struct drm_device *dev = encoder->dev;
 222         struct drm_i915_private *dev_priv = to_i915(dev);
 223         u32 mask;
 224
 225         /* XXX: pipe, hs */
 226         if (hs)
 227                 cmd &= ~DPI_LP_MODE;
 228         else
 229                 cmd |= DPI_LP_MODE;
 230
 231         /* clear bit */
 232         intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 233
 234         /* XXX: old code skips write if control unchanged */
 235         if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
 236                 drm_dbg_kms(&dev_priv->drm,
 237                             "Same special packet %02x twice in a row.\n", cmd);
 238
 239         intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
 240
 241         mask = SPL_PKT_SENT_INTERRUPT;
 242         if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
 243                 drm_err(&dev_priv->drm,
 244                         "Video mode command 0x%08x send failed.\n", cmd);
 245
 246         return 0;
 247 }
 248
 249 static void band_gap_reset(struct drm_i915_private *dev_priv)
 250 {
 251         vlv_flisdsi_get(dev_priv);
 252
 253         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 254         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 255         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 256         udelay(150);
 257         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 258         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 259
 260         vlv_flisdsi_put(dev_priv);
 261 }
 262
 263 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 264                                     struct intel_crtc_state *pipe_config,
 265                                     struct drm_connector_state *conn_state)
 266 {
 267         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 268         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 269                                                    base);
 270         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 271         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 272         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 273         int ret;
 274
 275         drm_dbg_kms(&dev_priv->drm, "\n");
 276         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 277
 278         if (fixed_mode) {
 279                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 280
 281                 if (HAS_GMCH(dev_priv))
 282                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
 283                 else
 284                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
 285                 if (ret)
 286                         return ret;
 287         }
 288
 289         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 290                 return -EINVAL;
 291
 292         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 293         adjusted_mode->flags = 0;
 294
 295         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 296                 pipe_config->pipe_bpp = 24;
 297         else
 298                 pipe_config->pipe_bpp = 18;
 299
 300         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 301                 /* Enable Frame time stamp based scanline reporting */
 302                 pipe_config->mode_flags |=
 303                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 304
 305                 /* Dual link goes to DSI transcoder A. */
 306                 if (intel_dsi->ports == BIT(PORT_C))
 307                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 308                 else
 309                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 310
 311                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 312                 if (ret)
 313                         return -EINVAL;
 314         } else {
 315                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 316                 if (ret)
 317                         return -EINVAL;
 318         }
 319
 320         pipe_config->clock_set = true;
 321
 322         return 0;
 323 }
 324
 325 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 326 {
 327         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 328         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 329         enum port port;
 330         u32 tmp;
 331         bool cold_boot = false;
 332
 333         /* Set the MIPI mode
 334          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 335          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 336          */
 337         for_each_dsi_port(port, intel_dsi->ports) {
 338                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 339                 intel_de_write(dev_priv, MIPI_CTRL(port),
 340                                tmp | GLK_MIPIIO_ENABLE);
 341         }
 342
 343         /* Put the IO into reset */
 344         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 345         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 346         intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
 347
 348         /* Program LP Wake */
 349         for_each_dsi_port(port, intel_dsi->ports) {
 350                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 351                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
 352                         tmp &= ~GLK_LP_WAKE;
 353                 else
 354                         tmp |= GLK_LP_WAKE;
 355                 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
 356         }
 357
 358         /* Wait for Pwr ACK */
 359         for_each_dsi_port(port, intel_dsi->ports) {
 360                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 361                                           GLK_MIPIIO_PORT_POWERED, 20))
 362                         drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
 363         }
 364
 365         /* Check for cold boot scenario */
 366         for_each_dsi_port(port, intel_dsi->ports) {
 367                 cold_boot |=
 368                         !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
 369         }
 370
 371         return cold_boot;
 372 }
 373
 374 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 375 {
 376         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 377         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 378         enum port port;
 379         u32 val;
 380
 381         /* Wait for MIPI PHY status bit to set */
 382         for_each_dsi_port(port, intel_dsi->ports) {
 383                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 384                                           GLK_PHY_STATUS_PORT_READY, 20))
 385                         drm_err(&dev_priv->drm, "PHY is not ON\n");
 386         }
 387
 388         /* Get IO out of reset */
 389         val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 390         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
 391                        val | GLK_MIPIIO_RESET_RELEASED);
 392
 393         /* Get IO out of Low power state*/
 394         for_each_dsi_port(port, intel_dsi->ports) {
 395                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 396                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 397                         val &= ~ULPS_STATE_MASK;
 398                         val |= DEVICE_READY;
 399                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 400                         usleep_range(10, 15);
 401                 } else {
 402                         /* Enter ULPS */
 403                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 404                         val &= ~ULPS_STATE_MASK;
 405                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 406                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 407
 408                         /* Wait for ULPS active */
 409                         if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 410                                                     GLK_ULPS_NOT_ACTIVE, 20))
 411                                 drm_err(&dev_priv->drm, "ULPS not active\n");
 412
 413                         /* Exit ULPS */
 414                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 415                         val &= ~ULPS_STATE_MASK;
 416                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 417                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 418
 419                         /* Enter Normal Mode */
 420                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 421                         val &= ~ULPS_STATE_MASK;
 422                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 423                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 424
 425                         val = intel_de_read(dev_priv, MIPI_CTRL(port));
 426                         val &= ~GLK_LP_WAKE;
 427                         intel_de_write(dev_priv, MIPI_CTRL(port), val);
 428                 }
 429         }
 430
 431         /* Wait for Stop state */
 432         for_each_dsi_port(port, intel_dsi->ports) {
 433                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 434                                           GLK_DATA_LANE_STOP_STATE, 20))
 435                         drm_err(&dev_priv->drm,
 436                                 "Date lane not in STOP state\n");
 437         }
 438
 439         /* Wait for AFE LATCH */
 440         for_each_dsi_port(port, intel_dsi->ports) {
 441                 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
 442                                           AFE_LATCHOUT, 20))
 443                         drm_err(&dev_priv->drm,
 444                                 "D-PHY not entering LP-11 state\n");
 445         }
 446 }
 447
 448 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 449 {
 450         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 451         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 452         enum port port;
 453         u32 val;
 454
 455         drm_dbg_kms(&dev_priv->drm, "\n");
 456
 457         /* Enable MIPI PHY transparent latch */
 458         for_each_dsi_port(port, intel_dsi->ports) {
 459                 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
 460                 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port),
 461                                val | LP_OUTPUT_HOLD);
 462                 usleep_range(2000, 2500);
 463         }
 464
 465         /* Clear ULPS and set device ready */
 466         for_each_dsi_port(port, intel_dsi->ports) {
 467                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 468                 val &= ~ULPS_STATE_MASK;
 469                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 470                 usleep_range(2000, 2500);
 471                 val |= DEVICE_READY;
 472                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 473         }
 474 }
 475
 476 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 477 {
 478         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 479         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 480         enum port port;
 481         u32 val;
 482
 483         drm_dbg_kms(&dev_priv->drm, "\n");
 484
 485         vlv_flisdsi_get(dev_priv);
 486         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 487          * needed everytime after power gate */
 488         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 489         vlv_flisdsi_put(dev_priv);
 490
 491         /* bandgap reset is needed after everytime we do power gate */
 492         band_gap_reset(dev_priv);
 493
 494         for_each_dsi_port(port, intel_dsi->ports) {
 495
 496                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 497                                ULPS_STATE_ENTER);
 498                 usleep_range(2500, 3000);
 499
 500                 /* Enable MIPI PHY transparent latch
 501                  * Common bit for both MIPI Port A & MIPI Port C
 502                  * No similar bit in MIPI Port C reg
 503                  */
 504                 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A));
 505                 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A),
 506                                val | LP_OUTPUT_HOLD);
 507                 usleep_range(1000, 1500);
 508
 509                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 510                                ULPS_STATE_EXIT);
 511                 usleep_range(2500, 3000);
 512
 513                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 514                                DEVICE_READY);
 515                 usleep_range(2500, 3000);
 516         }
 517 }
 518
 519 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 520 {
 521         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 522
 523         if (IS_GEMINILAKE(dev_priv))
 524                 glk_dsi_device_ready(encoder);
 525         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 526                 bxt_dsi_device_ready(encoder);
 527         else
 528                 vlv_dsi_device_ready(encoder);
 529 }
 530
 531 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 532 {
 533         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 534         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 535         enum port port;
 536         u32 val;
 537
 538         /* Enter ULPS */
 539         for_each_dsi_port(port, intel_dsi->ports) {
 540                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 541                 val &= ~ULPS_STATE_MASK;
 542                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 543                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 544         }
 545
 546         /* Wait for MIPI PHY status bit to unset */
 547         for_each_dsi_port(port, intel_dsi->ports) {
 548                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 549                                             GLK_PHY_STATUS_PORT_READY, 20))
 550                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 551         }
 552
 553         /* Wait for Pwr ACK bit to unset */
 554         for_each_dsi_port(port, intel_dsi->ports) {
 555                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 556                                             GLK_MIPIIO_PORT_POWERED, 20))
 557                         drm_err(&dev_priv->drm,
 558                                 "MIPI IO Port is not powergated\n");
 559         }
 560 }
 561
 562 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 563 {
 564         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 565         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 566         enum port port;
 567         u32 tmp;
 568
 569         /* Put the IO into reset */
 570         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 571         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 572         intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
 573
 574         /* Wait for MIPI PHY status bit to unset */
 575         for_each_dsi_port(port, intel_dsi->ports) {
 576                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 577                                             GLK_PHY_STATUS_PORT_READY, 20))
 578                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 579         }
 580
 581         /* Clear MIPI mode */
 582         for_each_dsi_port(port, intel_dsi->ports) {
 583                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 584                 tmp &= ~GLK_MIPIIO_ENABLE;
 585                 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
 586         }
 587 }
 588
 589 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 590 {
 591         glk_dsi_enter_low_power_mode(encoder);
 592         glk_dsi_disable_mipi_io(encoder);
 593 }
 594
 595 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 596 {
 597         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 598         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 599         enum port port;
 600
 601         drm_dbg_kms(&dev_priv->drm, "\n");
 602         for_each_dsi_port(port, intel_dsi->ports) {
 603                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 604                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 605                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 606                 u32 val;
 607
 608                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 609                                DEVICE_READY | ULPS_STATE_ENTER);
 610                 usleep_range(2000, 2500);
 611
 612                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 613                                DEVICE_READY | ULPS_STATE_EXIT);
 614                 usleep_range(2000, 2500);
 615
 616                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 617                                DEVICE_READY | ULPS_STATE_ENTER);
 618                 usleep_range(2000, 2500);
 619
 620                 /*
 621                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 622                  * Port A only. MIPI Port C has no similar bit for checking.
 623                  */
 624                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
 625                     intel_de_wait_for_clear(dev_priv, port_ctrl,
 626                                             AFE_LATCHOUT, 30))
 627                         drm_err(&dev_priv->drm, "DSI LP not going Low\n");
 628
 629                 /* Disable MIPI PHY transparent latch */
 630                 val = intel_de_read(dev_priv, port_ctrl);
 631                 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD);
 632                 usleep_range(1000, 1500);
 633
 634                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
 635                 usleep_range(2000, 2500);
 636         }
 637 }
 638
 639 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 640                                   const struct intel_crtc_state *crtc_state)
 641 {
 642         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 643         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 644         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 645         enum port port;
 646
 647         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 648                 u32 temp;
 649                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 650                         for_each_dsi_port(port, intel_dsi->ports) {
 651                                 temp = intel_de_read(dev_priv,
 652                                                      MIPI_CTRL(port));
 653                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 654                                         intel_dsi->pixel_overlap <<
 655                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 656                                 intel_de_write(dev_priv, MIPI_CTRL(port),
 657                                                temp);
 658                         }
 659                 } else {
 660                         temp = intel_de_read(dev_priv, VLV_CHICKEN_3);
 661                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 662                                         intel_dsi->pixel_overlap <<
 663                                         PIXEL_OVERLAP_CNT_SHIFT;
 664                         intel_de_write(dev_priv, VLV_CHICKEN_3, temp);
 665                 }
 666         }
 667
 668         for_each_dsi_port(port, intel_dsi->ports) {
 669                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 670                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 671                 u32 temp;
 672
 673                 temp = intel_de_read(dev_priv, port_ctrl);
 674
 675                 temp &= ~LANE_CONFIGURATION_MASK;
 676                 temp &= ~DUAL_LINK_MODE_MASK;
 677
 678                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 679                         temp |= (intel_dsi->dual_link - 1)
 680                                                 << DUAL_LINK_MODE_SHIFT;
 681                         if (IS_BROXTON(dev_priv))
 682                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 683                         else
 684                                 temp |= crtc->pipe ?
 685                                         LANE_CONFIGURATION_DUAL_LINK_B :
 686                                         LANE_CONFIGURATION_DUAL_LINK_A;
 687                 }
 688
 689                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 690                         temp |= DITHERING_ENABLE;
 691
 692                 /* assert ip_tg_enable signal */
 693                 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
 694                 intel_de_posting_read(dev_priv, port_ctrl);
 695         }
 696 }
 697
 698 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 699 {
 700         struct drm_device *dev = encoder->base.dev;
 701         struct drm_i915_private *dev_priv = to_i915(dev);
 702         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 703         enum port port;
 704
 705         for_each_dsi_port(port, intel_dsi->ports) {
 706                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 707                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 708                 u32 temp;
 709
 710                 /* de-assert ip_tg_enable signal */
 711                 temp = intel_de_read(dev_priv, port_ctrl);
 712                 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE);
 713                 intel_de_posting_read(dev_priv, port_ctrl);
 714         }
 715 }
 716
 717 static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
 718 {
 719         ktime_t panel_power_on_time;
 720         s64 panel_power_off_duration;
 721
 722         panel_power_on_time = ktime_get_boottime();
 723         panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
 724                                                   intel_dsi->panel_power_off_time);
 725
 726         if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
 727                 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration);
 728 }
 729
 730 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 731                               const struct intel_crtc_state *pipe_config);
 732 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 733
 734 /*
 735  * Panel enable/disable sequences from the VBT spec.
 736  *
 737  * Note the spec has AssertReset / DeassertReset swapped from their
 738  * usual naming. We use the normal names to avoid confusion (so below
 739  * they are swapped compared to the spec).
 740  *
 741  * Steps starting with MIPI refer to VBT sequences, note that for v2
 742  * VBTs several steps which have a VBT in v2 are expected to be handled
 743  * directly by the driver, by directly driving gpios for example.
 744  *
 745  * v2 video mode seq         v3 video mode seq         command mode seq
 746  * - power on                - MIPIPanelPowerOn        - power on
 747  * - wait t1+t2                                        - wait t1+t2
 748  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 749  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 750  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 751  *                                                     - MIPITearOn
 752  *                                                     - MIPIDisplayOn
 753  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 754  * - MIPIDisplayOn           - MIPIDisplayOn
 755  * - wait t5                                           - wait t5
 756  * - backlight on            - MIPIBacklightOn         - backlight on
 757  * ...                       ...                       ... issue mem cmds ...
 758  * - backlight off           - MIPIBacklightOff        - backlight off
 759  * - wait t6                                           - wait t6
 760  * - MIPIDisplayOff
 761  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 762  *                                                     - MIPITearOff
 763  *                           - MIPIDisplayOff          - MIPIDisplayOff
 764  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 765  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 766  * - wait t3                                           - wait t3
 767  * - power off               - MIPIPanelPowerOff       - power off
 768  * - wait t4                                           - wait t4
 769  */
 770
 771 /*
 772  * DSI port enable has to be done before pipe and plane enable, so we do it in
 773  * the pre_enable hook instead of the enable hook.
 774  */
 775 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 776                                  struct intel_encoder *encoder,
 777                                  const struct intel_crtc_state *pipe_config,
 778                                  const struct drm_connector_state *conn_state)
 779 {
 780         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 781         struct drm_crtc *crtc = pipe_config->uapi.crtc;
 782         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 784         enum pipe pipe = intel_crtc->pipe;
 785         enum port port;
 786         u32 val;
 787         bool glk_cold_boot = false;
 788
 789         drm_dbg_kms(&dev_priv->drm, "\n");
 790
 791         intel_dsi_wait_panel_power_cycle(intel_dsi);
 792
 793         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 794
 795         /*
 796          * The BIOS may leave the PLL in a wonky state where it doesn't
 797          * lock. It needs to be fully powered down to fix it.
 798          */
 799         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 800                 bxt_dsi_pll_disable(encoder);
 801                 bxt_dsi_pll_enable(encoder, pipe_config);
 802         } else {
 803                 vlv_dsi_pll_disable(encoder);
 804                 vlv_dsi_pll_enable(encoder, pipe_config);
 805         }
 806
 807         if (IS_BROXTON(dev_priv)) {
 808                 /* Add MIPI IO reset programming for modeset */
 809                 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
 810                 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
 811                                val | MIPIO_RST_CTRL);
 812
 813                 /* Power up DSI regulator */
 814                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 815                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 816         }
 817
 818         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 819                 u32 val;
 820
 821                 /* Disable DPOunit clock gating, can stall pipe */
 822                 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
 823                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 824                 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 825         }
 826
 827         if (!IS_GEMINILAKE(dev_priv))
 828                 intel_dsi_prepare(encoder, pipe_config);
 829
 830         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 831
 832         /*
 833          * Give the panel time to power-on and then deassert its reset.
 834          * Depending on the VBT MIPI sequences version the deassert-seq
 835          * may contain the necessary delay, intel_dsi_msleep() will skip
 836          * the delay in that case. If there is no deassert-seq, then an
 837          * unconditional msleep is used to give the panel time to power-on.
 838          */
 839         if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
 840                 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 841                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 842         } else {
 843                 msleep(intel_dsi->panel_on_delay);
 844         }
 845
 846         if (IS_GEMINILAKE(dev_priv)) {
 847                 glk_cold_boot = glk_dsi_enable_io(encoder);
 848
 849                 /* Prepare port in cold boot(s3/s4) scenario */
 850                 if (glk_cold_boot)
 851                         intel_dsi_prepare(encoder, pipe_config);
 852         }
 853
 854         /* Put device in ready state (LP-11) */
 855         intel_dsi_device_ready(encoder);
 856
 857         /* Prepare port in normal boot scenario */
 858         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 859                 intel_dsi_prepare(encoder, pipe_config);
 860
 861         /* Send initialization commands in LP mode */
 862         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 863
 864         /* Enable port in pre-enable phase itself because as per hw team
 865          * recommendation, port should be enabled befor plane & pipe */
 866         if (is_cmd_mode(intel_dsi)) {
 867                 for_each_dsi_port(port, intel_dsi->ports)
 868                         intel_de_write(dev_priv,
 869                                        MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 870                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 871                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 872         } else {
 873                 msleep(20); /* XXX */
 874                 for_each_dsi_port(port, intel_dsi->ports)
 875                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 876                 intel_dsi_msleep(intel_dsi, 100);
 877
 878                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 879
 880                 intel_dsi_port_enable(encoder, pipe_config);
 881         }
 882
 883         intel_panel_enable_backlight(pipe_config, conn_state);
 884         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 885 }
 886
 887 static void bxt_dsi_enable(struct intel_atomic_state *state,
 888                            struct intel_encoder *encoder,
 889                            const struct intel_crtc_state *crtc_state,
 890                            const struct drm_connector_state *conn_state)
 891 {
 892         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
 893
 894         intel_crtc_vblank_on(crtc_state);
 895 }
 896
 897 /*
 898  * DSI port disable has to be done after pipe and plane disable, so we do it in
 899  * the post_disable hook.
 900  */
 901 static void intel_dsi_disable(struct intel_atomic_state *state,
 902                               struct intel_encoder *encoder,
 903                               const struct intel_crtc_state *old_crtc_state,
 904                               const struct drm_connector_state *old_conn_state)
 905 {
 906         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 907         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 908         enum port port;
 909
 910         drm_dbg_kms(&i915->drm, "\n");
 911
 912         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 913         intel_panel_disable_backlight(old_conn_state);
 914
 915         /*
 916          * According to the spec we should send SHUTDOWN before
 917          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 918          * has shown that the v3 sequence works for v2 VBTs too
 919          */
 920         if (is_vid_mode(intel_dsi)) {
 921                 /* Send Shutdown command to the panel in LP mode */
 922                 for_each_dsi_port(port, intel_dsi->ports)
 923                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 924                 msleep(10);
 925         }
 926 }
 927
 928 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 929 {
 930         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 931
 932         if (IS_GEMINILAKE(dev_priv))
 933                 glk_dsi_clear_device_ready(encoder);
 934         else
 935                 vlv_dsi_clear_device_ready(encoder);
 936 }
 937
 938 static void intel_dsi_post_disable(struct intel_atomic_state *state,
 939                                    struct intel_encoder *encoder,
 940                                    const struct intel_crtc_state *old_crtc_state,
 941                                    const struct drm_connector_state *old_conn_state)
 942 {
 943         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 944         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 945         enum port port;
 946         u32 val;
 947
 948         drm_dbg_kms(&dev_priv->drm, "\n");
 949
 950         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 951                 intel_crtc_vblank_off(old_crtc_state);
 952
 953                 skl_scaler_disable(old_crtc_state);
 954         }
 955
 956         if (is_vid_mode(intel_dsi)) {
 957                 for_each_dsi_port(port, intel_dsi->ports)
 958                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 959
 960                 intel_dsi_port_disable(encoder);
 961                 usleep_range(2000, 5000);
 962         }
 963
 964         intel_dsi_unprepare(encoder);
 965
 966         /*
 967          * if disable packets are sent before sending shutdown packet then in
 968          * some next enable sequence send turn on packet error is observed
 969          */
 970         if (is_cmd_mode(intel_dsi))
 971                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 972         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 973
 974         /* Transition to LP-00 */
 975         intel_dsi_clear_device_ready(encoder);
 976
 977         if (IS_BROXTON(dev_priv)) {
 978                 /* Power down DSI regulator to save power */
 979                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 980                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
 981                                HS_IO_CTRL_SELECT);
 982
 983                 /* Add MIPI IO reset programming for modeset */
 984                 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
 985                 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
 986                                val & ~MIPIO_RST_CTRL);
 987         }
 988
 989         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 990                 bxt_dsi_pll_disable(encoder);
 991         } else {
 992                 u32 val;
 993
 994                 vlv_dsi_pll_disable(encoder);
 995
 996                 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
 997                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 998                 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 999         }
1000
1001         /* Assert reset */
1002         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1003
1004         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
1005         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1006
1007         intel_dsi->panel_power_off_time = ktime_get_boottime();
1008 }
1009
1010 static void intel_dsi_shutdown(struct intel_encoder *encoder)
1011 {
1012         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1013
1014         intel_dsi_wait_panel_power_cycle(intel_dsi);
1015 }
1016
1017 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1018                                    enum pipe *pipe)
1019 {
1020         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1021         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1022         intel_wakeref_t wakeref;
1023         enum port port;
1024         bool active = false;
1025
1026         drm_dbg_kms(&dev_priv->drm, "\n");
1027
1028         wakeref = intel_display_power_get_if_enabled(dev_priv,
1029                                                      encoder->power_domain);
1030         if (!wakeref)
1031                 return false;
1032
1033         /*
1034          * On Broxton the PLL needs to be enabled with a valid divider
1035          * configuration, otherwise accessing DSI registers will hang the
1036          * machine. See BSpec North Display Engine registers/MIPI[BXT].
1037          */
1038         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1039             !bxt_dsi_pll_is_enabled(dev_priv))
1040                 goto out_put_power;
1041
1042         /* XXX: this only works for one DSI output */
1043         for_each_dsi_port(port, intel_dsi->ports) {
1044                 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
1045                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1046                 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
1047
1048                 /*
1049                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1050                  * bit in port C control register does not get set. As a
1051                  * workaround, check pipe B conf instead.
1052                  */
1053                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1054                     port == PORT_C)
1055                         enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1056
1057                 /* Try command mode if video mode not enabled */
1058                 if (!enabled) {
1059                         u32 tmp = intel_de_read(dev_priv,
1060                                                 MIPI_DSI_FUNC_PRG(port));
1061                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1062                 }
1063
1064                 if (!enabled)
1065                         continue;
1066
1067                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
1068                         continue;
1069
1070                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1071                         u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1072                         tmp &= BXT_PIPE_SELECT_MASK;
1073                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1074
1075                         if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
1076                                 continue;
1077
1078                         *pipe = tmp;
1079                 } else {
1080                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1081                 }
1082
1083                 active = true;
1084                 break;
1085         }
1086
1087 out_put_power:
1088         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1089
1090         return active;
1091 }
1092
1093 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1094                                     struct intel_crtc_state *pipe_config)
1095 {
1096         struct drm_device *dev = encoder->base.dev;
1097         struct drm_i915_private *dev_priv = to_i915(dev);
1098         struct drm_display_mode *adjusted_mode =
1099                                         &pipe_config->hw.adjusted_mode;
1100         struct drm_display_mode *adjusted_mode_sw;
1101         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1102         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1103         unsigned int lane_count = intel_dsi->lane_count;
1104         unsigned int bpp, fmt;
1105         enum port port;
1106         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1107         u16 hfp_sw, hsync_sw, hbp_sw;
1108         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1109                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1110
1111         /* FIXME: hw readout should not depend on SW state */
1112         adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1113
1114         /*
1115          * Atleast one port is active as encoder->get_config called only if
1116          * encoder->get_hw_state() returns true.
1117          */
1118         for_each_dsi_port(port, intel_dsi->ports) {
1119                 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1120                         break;
1121         }
1122
1123         fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1124         bpp = mipi_dsi_pixel_format_to_bpp(
1125                         pixel_format_from_register_bits(fmt));
1126
1127         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1128
1129         /* Enable Frame time stamo based scanline reporting */
1130         pipe_config->mode_flags |=
1131                 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1132
1133         /* In terms of pixels */
1134         adjusted_mode->crtc_hdisplay =
1135                                 intel_de_read(dev_priv,
1136                                               BXT_MIPI_TRANS_HACTIVE(port));
1137         adjusted_mode->crtc_vdisplay =
1138                                 intel_de_read(dev_priv,
1139                                               BXT_MIPI_TRANS_VACTIVE(port));
1140         adjusted_mode->crtc_vtotal =
1141                                 intel_de_read(dev_priv,
1142                                               BXT_MIPI_TRANS_VTOTAL(port));
1143
1144         hactive = adjusted_mode->crtc_hdisplay;
1145         hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1146
1147         /*
1148          * Meaningful for video mode non-burst sync pulse mode only,
1149          * can be zero for non-burst sync events and burst modes
1150          */
1151         hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1152         hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1153
1154         /* harizontal values are in terms of high speed byte clock */
1155         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1156                                                 intel_dsi->burst_mode_ratio);
1157         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1158                                                 intel_dsi->burst_mode_ratio);
1159         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1160                                                 intel_dsi->burst_mode_ratio);
1161
1162         if (intel_dsi->dual_link) {
1163                 hfp *= 2;
1164                 hsync *= 2;
1165                 hbp *= 2;
1166         }
1167
1168         /* vertical values are in terms of lines */
1169         vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1170         vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1171         vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port));
1172
1173         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1174         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1175         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1176         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1177         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1178
1179         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1180         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1181         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1182         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1183
1184         /*
1185          * In BXT DSI there is no regs programmed with few horizontal timings
1186          * in Pixels but txbyteclkhs.. So retrieval process adds some
1187          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1188          * Actually here for the given adjusted_mode, we are calculating the
1189          * value programmed to the port and then back to the horizontal timing
1190          * param in pixels. This is the expected value, including roundup errors
1191          * And if that is same as retrieved value from port, then
1192          * (HW state) adjusted_mode's horizontal timings are corrected to
1193          * match with SW state to nullify the errors.
1194          */
1195         /* Calculating the value programmed to the Port register */
1196         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1197                                         adjusted_mode_sw->crtc_hdisplay;
1198         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1199                                         adjusted_mode_sw->crtc_hsync_start;
1200         hbp_sw = adjusted_mode_sw->crtc_htotal -
1201                                         adjusted_mode_sw->crtc_hsync_end;
1202
1203         if (intel_dsi->dual_link) {
1204                 hfp_sw /= 2;
1205                 hsync_sw /= 2;
1206                 hbp_sw /= 2;
1207         }
1208
1209         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1210                                                 intel_dsi->burst_mode_ratio);
1211         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1212                             intel_dsi->burst_mode_ratio);
1213         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1214                                                 intel_dsi->burst_mode_ratio);
1215
1216         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1217         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1218                                                 intel_dsi->burst_mode_ratio);
1219         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1220                                                 intel_dsi->burst_mode_ratio);
1221         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1222                                                 intel_dsi->burst_mode_ratio);
1223
1224         if (intel_dsi->dual_link) {
1225                 hfp_sw *= 2;
1226                 hsync_sw *= 2;
1227                 hbp_sw *= 2;
1228         }
1229
1230         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1231                                                         hsync_sw + hbp_sw;
1232         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1233         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1234         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1235         crtc_hblank_end_sw = crtc_htotal_sw;
1236
1237         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1238                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1239
1240         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1241                 adjusted_mode->crtc_hsync_start =
1242                                         adjusted_mode_sw->crtc_hsync_start;
1243
1244         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1245                 adjusted_mode->crtc_hsync_end =
1246                                         adjusted_mode_sw->crtc_hsync_end;
1247
1248         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1249                 adjusted_mode->crtc_hblank_start =
1250                                         adjusted_mode_sw->crtc_hblank_start;
1251
1252         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1253                 adjusted_mode->crtc_hblank_end =
1254                                         adjusted_mode_sw->crtc_hblank_end;
1255 }
1256
1257 static void intel_dsi_get_config(struct intel_encoder *encoder,
1258                                  struct intel_crtc_state *pipe_config)
1259 {
1260         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1261         u32 pclk;
1262         drm_dbg_kms(&dev_priv->drm, "\n");
1263
1264         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1265
1266         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1267                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1268                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1269         } else {
1270                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1271         }
1272
1273         if (pclk) {
1274                 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1275                 pipe_config->port_clock = pclk;
1276         }
1277 }
1278
1279 /* return txclkesc cycles in terms of divider and duration in us */
1280 static u16 txclkesc(u32 divider, unsigned int us)
1281 {
1282         switch (divider) {
1283         case ESCAPE_CLOCK_DIVIDER_1:
1284         default:
1285                 return 20 * us;
1286         case ESCAPE_CLOCK_DIVIDER_2:
1287                 return 10 * us;
1288         case ESCAPE_CLOCK_DIVIDER_4:
1289                 return 5 * us;
1290         }
1291 }
1292
1293 static void set_dsi_timings(struct drm_encoder *encoder,
1294                             const struct drm_display_mode *adjusted_mode)
1295 {
1296         struct drm_device *dev = encoder->dev;
1297         struct drm_i915_private *dev_priv = to_i915(dev);
1298         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1299         enum port port;
1300         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1301         unsigned int lane_count = intel_dsi->lane_count;
1302
1303         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1304
1305         hactive = adjusted_mode->crtc_hdisplay;
1306         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1307         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1308         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1309
1310         if (intel_dsi->dual_link) {
1311                 hactive /= 2;
1312                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1313                         hactive += intel_dsi->pixel_overlap;
1314                 hfp /= 2;
1315                 hsync /= 2;
1316                 hbp /= 2;
1317         }
1318
1319         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1320         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1321         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1322
1323         /* horizontal values are in terms of high speed byte clock */
1324         hactive = txbyteclkhs(hactive, bpp, lane_count,
1325                               intel_dsi->burst_mode_ratio);
1326         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1327         hsync = txbyteclkhs(hsync, bpp, lane_count,
1328                             intel_dsi->burst_mode_ratio);
1329         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1330
1331         for_each_dsi_port(port, intel_dsi->ports) {
1332                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1333                         /*
1334                          * Program hdisplay and vdisplay on MIPI transcoder.
1335                          * This is different from calculated hactive and
1336                          * vactive, as they are calculated per channel basis,
1337                          * whereas these values should be based on resolution.
1338                          */
1339                         intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1340                                        adjusted_mode->crtc_hdisplay);
1341                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1342                                        adjusted_mode->crtc_vdisplay);
1343                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1344                                        adjusted_mode->crtc_vtotal);
1345                 }
1346
1347                 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1348                                hactive);
1349                 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1350
1351                 /* meaningful for video mode non-burst sync pulse mode only,
1352                  * can be zero for non-burst sync events and burst modes */
1353                 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1354                                hsync);
1355                 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1356
1357                 /* vertical values are in terms of lines */
1358                 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1359                 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1360                                vsync);
1361                 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1362         }
1363 }
1364
1365 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1366 {
1367         switch (fmt) {
1368         case MIPI_DSI_FMT_RGB888:
1369                 return VID_MODE_FORMAT_RGB888;
1370         case MIPI_DSI_FMT_RGB666:
1371                 return VID_MODE_FORMAT_RGB666;
1372         case MIPI_DSI_FMT_RGB666_PACKED:
1373                 return VID_MODE_FORMAT_RGB666_PACKED;
1374         case MIPI_DSI_FMT_RGB565:
1375                 return VID_MODE_FORMAT_RGB565;
1376         default:
1377                 MISSING_CASE(fmt);
1378                 return VID_MODE_FORMAT_RGB666;
1379         }
1380 }
1381
1382 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1383                               const struct intel_crtc_state *pipe_config)
1384 {
1385         struct drm_encoder *encoder = &intel_encoder->base;
1386         struct drm_device *dev = encoder->dev;
1387         struct drm_i915_private *dev_priv = to_i915(dev);
1388         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
1389         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1390         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1391         enum port port;
1392         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1393         u32 val, tmp;
1394         u16 mode_hdisplay;
1395
1396         drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe));
1397
1398         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1399
1400         if (intel_dsi->dual_link) {
1401                 mode_hdisplay /= 2;
1402                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1403                         mode_hdisplay += intel_dsi->pixel_overlap;
1404         }
1405
1406         for_each_dsi_port(port, intel_dsi->ports) {
1407                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1408                         /*
1409                          * escape clock divider, 20MHz, shared for A and C.
1410                          * device ready must be off when doing this! txclkesc?
1411                          */
1412                         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1413                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1414                         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1415                                        tmp | ESCAPE_CLOCK_DIVIDER_1);
1416
1417                         /* read request priority is per pipe */
1418                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1419                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1420                         intel_de_write(dev_priv, MIPI_CTRL(port),
1421                                        tmp | READ_REQUEST_PRIORITY_HIGH);
1422                 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1423                         enum pipe pipe = intel_crtc->pipe;
1424
1425                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1426                         tmp &= ~BXT_PIPE_SELECT_MASK;
1427
1428                         tmp |= BXT_PIPE_SELECT(pipe);
1429                         intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
1430                 }
1431
1432                 /* XXX: why here, why like this? handling in irq handler?! */
1433                 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1434                 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1435
1436                 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1437                                intel_dsi->dphy_reg);
1438
1439                 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1440                                adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1441         }
1442
1443         set_dsi_timings(encoder, adjusted_mode);
1444
1445         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1446         if (is_cmd_mode(intel_dsi)) {
1447                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1448                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1449         } else {
1450                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1451                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1452         }
1453
1454         tmp = 0;
1455         if (intel_dsi->eotp_pkt == 0)
1456                 tmp |= EOT_DISABLE;
1457         if (intel_dsi->clock_stop)
1458                 tmp |= CLOCKSTOP;
1459
1460         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1461                 tmp |= BXT_DPHY_DEFEATURE_EN;
1462                 if (!is_cmd_mode(intel_dsi))
1463                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1464         }
1465
1466         for_each_dsi_port(port, intel_dsi->ports) {
1467                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1468
1469                 /* timeouts for recovery. one frame IIUC. if counter expires,
1470                  * EOT and stop state. */
1471
1472                 /*
1473                  * In burst mode, value greater than one DPI line Time in byte
1474                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1475                  * said value is recommended.
1476                  *
1477                  * In non-burst mode, Value greater than one DPI frame time in
1478                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1479                  * said value is recommended.
1480                  *
1481                  * In DBI only mode, value greater than one DBI frame time in
1482                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1483                  * said value is recommended.
1484                  */
1485
1486                 if (is_vid_mode(intel_dsi) &&
1487                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1488                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1489                                        txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1490                 } else {
1491                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1492                                        txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1493                 }
1494                 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1495                                intel_dsi->lp_rx_timeout);
1496                 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1497                                intel_dsi->turn_arnd_val);
1498                 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1499                                intel_dsi->rst_timer_val);
1500
1501                 /* dphy stuff */
1502
1503                 /* in terms of low power clock */
1504                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1505                                txclkesc(intel_dsi->escape_clk_div, 100));
1506
1507                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1508                     !intel_dsi->dual_link) {
1509                         /*
1510                          * BXT spec says write MIPI_INIT_COUNT for
1511                          * both the ports, even if only one is
1512                          * getting used. So write the other port
1513                          * if not in dual link mode.
1514                          */
1515                         intel_de_write(dev_priv,
1516                                        MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1517                                        intel_dsi->init_count);
1518                 }
1519
1520                 /* recovery disables */
1521                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1522
1523                 /* in terms of low power clock */
1524                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1525                                intel_dsi->init_count);
1526
1527                 /* in terms of txbyteclkhs. actual high to low switch +
1528                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1529                  *
1530                  * XXX: write MIPI_STOP_STATE_STALL?
1531                  */
1532                 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1533                                intel_dsi->hs_to_lp_count);
1534
1535                 /* XXX: low power clock equivalence in terms of byte clock.
1536                  * the number of byte clocks occupied in one low power clock.
1537                  * based on txbyteclkhs and txclkesc.
1538                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1539                  * ) / 105.???
1540                  */
1541                 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1542                                intel_dsi->lp_byte_clk);
1543
1544                 if (IS_GEMINILAKE(dev_priv)) {
1545                         intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1546                                        intel_dsi->lp_byte_clk);
1547                         /* Shadow of DPHY reg */
1548                         intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1549                                        intel_dsi->dphy_reg);
1550                 }
1551
1552                 /* the bw essential for transmitting 16 long packets containing
1553                  * 252 bytes meant for dcs write memory command is programmed in
1554                  * this register in terms of byte clocks. based on dsi transfer
1555                  * rate and the number of lanes configured the time taken to
1556                  * transmit 16 long packets in a dsi stream varies. */
1557                 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1558                                intel_dsi->bw_timer);
1559
1560                 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1561                                intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1562
1563                 if (is_vid_mode(intel_dsi))
1564                         /* Some panels might have resolution which is not a
1565                          * multiple of 64 like 1366 x 768. Enable RANDOM
1566                          * resolution support for such panels by default */
1567                         intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port),
1568                                        intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION);
1569         }
1570 }
1571
1572 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1573 {
1574         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1575         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1576         enum port port;
1577         u32 val;
1578
1579         if (IS_GEMINILAKE(dev_priv))
1580                 return;
1581
1582         for_each_dsi_port(port, intel_dsi->ports) {
1583                 /* Panel commands can be sent when clock is in LP11 */
1584                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1585
1586                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1587                         bxt_dsi_reset_clocks(encoder, port);
1588                 else
1589                         vlv_dsi_reset_clocks(encoder, port);
1590                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1591
1592                 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port));
1593                 val &= ~VID_MODE_FORMAT_MASK;
1594                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1595
1596                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1597         }
1598 }
1599
1600 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1601 {
1602         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1603
1604         intel_dsi_vbt_gpio_cleanup(intel_dsi);
1605         intel_encoder_destroy(encoder);
1606 }
1607
1608 static const struct drm_encoder_funcs intel_dsi_funcs = {
1609         .destroy = intel_dsi_encoder_destroy,
1610 };
1611
1612 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1613         .get_modes = intel_dsi_get_modes,
1614         .mode_valid = intel_dsi_mode_valid,
1615         .atomic_check = intel_digital_connector_atomic_check,
1616 };
1617
1618 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1619         .detect = intel_panel_detect,
1620         .late_register = intel_connector_register,
1621         .early_unregister = intel_connector_unregister,
1622         .destroy = intel_connector_destroy,
1623         .fill_modes = drm_helper_probe_single_connector_modes,
1624         .atomic_get_property = intel_digital_connector_atomic_get_property,
1625         .atomic_set_property = intel_digital_connector_atomic_set_property,
1626         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1627         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1628 };
1629
1630 static void vlv_dsi_add_properties(struct intel_connector *connector)
1631 {
1632         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1633
1634         if (connector->panel.fixed_mode) {
1635                 u32 allowed_scalers;
1636
1637                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1638                 if (!HAS_GMCH(dev_priv))
1639                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1640
1641                 drm_connector_attach_scaling_mode_property(&connector->base,
1642                                                                 allowed_scalers);
1643
1644                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1645
1646                 drm_connector_set_panel_orientation_with_quirk(
1647                                 &connector->base,
1648                                 intel_dsi_get_panel_orientation(connector),
1649                                 connector->panel.fixed_mode->hdisplay,
1650                                 connector->panel.fixed_mode->vdisplay);
1651         }
1652 }
1653
1654 #define NS_KHZ_RATIO            1000000
1655
1656 #define PREPARE_CNT_MAX         0x3F
1657 #define EXIT_ZERO_CNT_MAX       0x3F
1658 #define CLK_ZERO_CNT_MAX        0xFF
1659 #define TRAIL_CNT_MAX           0x1F
1660
1661 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1662 {
1663         struct drm_device *dev = intel_dsi->base.base.dev;
1664         struct drm_i915_private *dev_priv = to_i915(dev);
1665         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1666         u32 tlpx_ns, extra_byte_count, tlpx_ui;
1667         u32 ui_num, ui_den;
1668         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1669         u32 ths_prepare_ns, tclk_trail_ns;
1670         u32 tclk_prepare_clkzero, ths_prepare_hszero;
1671         u32 lp_to_hs_switch, hs_to_lp_switch;
1672         u32 mul;
1673
1674         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1675
1676         switch (intel_dsi->lane_count) {
1677         case 1:
1678         case 2:
1679                 extra_byte_count = 2;
1680                 break;
1681         case 3:
1682                 extra_byte_count = 4;
1683                 break;
1684         case 4:
1685         default:
1686                 extra_byte_count = 3;
1687                 break;
1688         }
1689
1690         /* in Kbps */
1691         ui_num = NS_KHZ_RATIO;
1692         ui_den = intel_dsi_bitrate(intel_dsi);
1693
1694         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1695         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1696
1697         /*
1698          * B060
1699          * LP byte clock = TLPX/ (8UI)
1700          */
1701         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1702
1703         /* DDR clock period = 2 * UI
1704          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1705          * UI(nsec) = 10^6 / bitrate
1706          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1707          * DDR clock count  = ns_value / DDR clock period
1708          *
1709          * For GEMINILAKE dphy_param_reg will be programmed in terms of
1710          * HS byte clock count for other platform in HS ddr clock count
1711          */
1712         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1713         ths_prepare_ns = max(mipi_config->ths_prepare,
1714                              mipi_config->tclk_prepare);
1715
1716         /* prepare count */
1717         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1718
1719         if (prepare_cnt > PREPARE_CNT_MAX) {
1720                 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1721                             prepare_cnt);
1722                 prepare_cnt = PREPARE_CNT_MAX;
1723         }
1724
1725         /* exit zero count */
1726         exit_zero_cnt = DIV_ROUND_UP(
1727                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1728                                 ui_num * mul
1729                                 );
1730
1731         /*
1732          * Exit zero is unified val ths_zero and ths_exit
1733          * minimum value for ths_exit = 110ns
1734          * min (exit_zero_cnt * 2) = 110/UI
1735          * exit_zero_cnt = 55/UI
1736          */
1737         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1738                 exit_zero_cnt += 1;
1739
1740         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1741                 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1742                             exit_zero_cnt);
1743                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1744         }
1745
1746         /* clk zero count */
1747         clk_zero_cnt = DIV_ROUND_UP(
1748                                 (tclk_prepare_clkzero - ths_prepare_ns)
1749                                 * ui_den, ui_num * mul);
1750
1751         if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1752                 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1753                             clk_zero_cnt);
1754                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1755         }
1756
1757         /* trail count */
1758         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1759         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1760
1761         if (trail_cnt > TRAIL_CNT_MAX) {
1762                 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1763                             trail_cnt);
1764                 trail_cnt = TRAIL_CNT_MAX;
1765         }
1766
1767         /* B080 */
1768         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1769                                                 clk_zero_cnt << 8 | prepare_cnt;
1770
1771         /*
1772          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1773          *                                      mul + 10UI + Extra Byte Count
1774          *
1775          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1776          * Extra Byte Count is calculated according to number of lanes.
1777          * High Low Switch Count is the Max of LP to HS and
1778          * HS to LP switch count
1779          *
1780          */
1781         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1782
1783         /* B044 */
1784         /* FIXME:
1785          * The comment above does not match with the code */
1786         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1787                                                 exit_zero_cnt * mul + 10, 8);
1788
1789         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1790
1791         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1792         intel_dsi->hs_to_lp_count += extra_byte_count;
1793
1794         /* B088 */
1795         /* LP -> HS for clock lanes
1796          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1797          *                                              extra byte count
1798          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1799          *                                      2(in UI) + extra byte count
1800          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1801          *                                      8 + extra byte count
1802          */
1803         intel_dsi->clk_lp_to_hs_count =
1804                 DIV_ROUND_UP(
1805                         4 * tlpx_ui + prepare_cnt * 2 +
1806                         clk_zero_cnt * 2,
1807                         8);
1808
1809         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1810
1811         /* HS->LP for Clock Lanes
1812          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1813          *                                              Extra byte count
1814          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1815          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1816          *                                              Extra byte count
1817          */
1818         intel_dsi->clk_hs_to_lp_count =
1819                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1820                         8);
1821         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1822
1823         intel_dsi_log_params(intel_dsi);
1824 }
1825
1826 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1827 {
1828         struct drm_device *dev = &dev_priv->drm;
1829         struct intel_dsi *intel_dsi;
1830         struct intel_encoder *intel_encoder;
1831         struct drm_encoder *encoder;
1832         struct intel_connector *intel_connector;
1833         struct drm_connector *connector;
1834         struct drm_display_mode *current_mode, *fixed_mode;
1835         enum port port;
1836         enum pipe pipe;
1837
1838         drm_dbg_kms(&dev_priv->drm, "\n");
1839
1840         /* There is no detection method for MIPI so rely on VBT */
1841         if (!intel_bios_is_dsi_present(dev_priv, &port))
1842                 return;
1843
1844         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1845                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1846         else
1847                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1848
1849         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1850         if (!intel_dsi)
1851                 return;
1852
1853         intel_connector = intel_connector_alloc();
1854         if (!intel_connector) {
1855                 kfree(intel_dsi);
1856                 return;
1857         }
1858
1859         intel_encoder = &intel_dsi->base;
1860         encoder = &intel_encoder->base;
1861         intel_dsi->attached_connector = intel_connector;
1862
1863         connector = &intel_connector->base;
1864
1865         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1866                          "DSI %c", port_name(port));
1867
1868         intel_encoder->compute_config = intel_dsi_compute_config;
1869         intel_encoder->pre_enable = intel_dsi_pre_enable;
1870         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1871                 intel_encoder->enable = bxt_dsi_enable;
1872         intel_encoder->disable = intel_dsi_disable;
1873         intel_encoder->post_disable = intel_dsi_post_disable;
1874         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1875         intel_encoder->get_config = intel_dsi_get_config;
1876         intel_encoder->update_pipe = intel_panel_update_backlight;
1877         intel_encoder->shutdown = intel_dsi_shutdown;
1878
1879         intel_connector->get_hw_state = intel_connector_get_hw_state;
1880
1881         intel_encoder->port = port;
1882         intel_encoder->type = INTEL_OUTPUT_DSI;
1883         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1884         intel_encoder->cloneable = 0;
1885
1886         /*
1887          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1888          * port C. BXT isn't limited like this.
1889          */
1890         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1891                 intel_encoder->pipe_mask = ~0;
1892         else if (port == PORT_A)
1893                 intel_encoder->pipe_mask = BIT(PIPE_A);
1894         else
1895                 intel_encoder->pipe_mask = BIT(PIPE_B);
1896
1897         intel_dsi->panel_power_off_time = ktime_get_boottime();
1898
1899         if (dev_priv->vbt.dsi.config->dual_link)
1900                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1901         else
1902                 intel_dsi->ports = BIT(port);
1903
1904         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1905         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1906
1907         /* Create a DSI host (and a device) for each port. */
1908         for_each_dsi_port(port, intel_dsi->ports) {
1909                 struct intel_dsi_host *host;
1910
1911                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1912                                            port);
1913                 if (!host)
1914                         goto err;
1915
1916                 intel_dsi->dsi_hosts[port] = host;
1917         }
1918
1919         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1920                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1921                 goto err;
1922         }
1923
1924         /* Use clock read-back from current hw-state for fastboot */
1925         current_mode = intel_encoder_current_mode(intel_encoder);
1926         if (current_mode) {
1927                 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1928                             intel_dsi->pclk, current_mode->clock);
1929                 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1930                                             current_mode->clock)) {
1931                         drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1932                         intel_dsi->pclk = current_mode->clock;
1933                 }
1934
1935                 kfree(current_mode);
1936         }
1937
1938         vlv_dphy_param_init(intel_dsi);
1939
1940         intel_dsi_vbt_gpio_init(intel_dsi,
1941                                 intel_dsi_get_hw_state(intel_encoder, &pipe));
1942
1943         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1944                            DRM_MODE_CONNECTOR_DSI);
1945
1946         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1947
1948         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1949         connector->interlace_allowed = false;
1950         connector->doublescan_allowed = false;
1951
1952         intel_connector_attach_encoder(intel_connector, intel_encoder);
1953
1954         mutex_lock(&dev->mode_config.mutex);
1955         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1956         mutex_unlock(&dev->mode_config.mutex);
1957
1958         if (!fixed_mode) {
1959                 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1960                 goto err_cleanup_connector;
1961         }
1962
1963         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1964         intel_panel_setup_backlight(connector, INVALID_PIPE);
1965
1966         vlv_dsi_add_properties(intel_connector);
1967
1968         return;
1969
1970 err_cleanup_connector:
1971         drm_connector_cleanup(&intel_connector->base);
1972 err:
1973         drm_encoder_cleanup(&intel_encoder->base);
1974         kfree(intel_dsi);
1975         kfree(intel_connector);
1976 }