drivers/gpu/drm/i915/display/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_mipi_dsi.h>
  32
  33 #include "i915_drv.h"
  34 #include "intel_atomic.h"
  35 #include "intel_connector.h"
  36 #include "intel_display_types.h"
  37 #include "intel_dsi.h"
  38 #include "intel_fifo_underrun.h"
  39 #include "intel_panel.h"
  40 #include "intel_sideband.h"
  41
  42 /* return pixels in terms of txbyteclkhs */
  43 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  44                        u16 burst_mode_ratio)
  45 {
  46         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  47                                          8 * 100), lane_count);
  48 }
  49
  50 /* return pixels equvalent to txbyteclkhs */
  51 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  52                         u16 burst_mode_ratio)
  53 {
  54         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  55                                                 (bpp * burst_mode_ratio));
  56 }
  57
  58 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  59 {
  60         /* It just so happens the VBT matches register contents. */
  61         switch (fmt) {
  62         case VID_MODE_FORMAT_RGB888:
  63                 return MIPI_DSI_FMT_RGB888;
  64         case VID_MODE_FORMAT_RGB666:
  65                 return MIPI_DSI_FMT_RGB666;
  66         case VID_MODE_FORMAT_RGB666_PACKED:
  67                 return MIPI_DSI_FMT_RGB666_PACKED;
  68         case VID_MODE_FORMAT_RGB565:
  69                 return MIPI_DSI_FMT_RGB565;
  70         default:
  71                 MISSING_CASE(fmt);
  72                 return MIPI_DSI_FMT_RGB666;
  73         }
  74 }
  75
  76 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  77 {
  78         struct drm_encoder *encoder = &intel_dsi->base.base;
  79         struct drm_device *dev = encoder->dev;
  80         struct drm_i915_private *dev_priv = to_i915(dev);
  81         u32 mask;
  82
  83         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  84                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  85
  86         if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
  87                                   mask, 100))
  88                 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
  89 }
  90
  91 static void write_data(struct drm_i915_private *dev_priv,
  92                        i915_reg_t reg,
  93                        const u8 *data, u32 len)
  94 {
  95         u32 i, j;
  96
  97         for (i = 0; i < len; i += 4) {
  98                 u32 val = 0;
  99
 100                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 101                         val |= *data++ << 8 * j;
 102
 103                 intel_de_write(dev_priv, reg, val);
 104         }
 105 }
 106
 107 static void read_data(struct drm_i915_private *dev_priv,
 108                       i915_reg_t reg,
 109                       u8 *data, u32 len)
 110 {
 111         u32 i, j;
 112
 113         for (i = 0; i < len; i += 4) {
 114                 u32 val = intel_de_read(dev_priv, reg);
 115
 116                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 117                         *data++ = val >> 8 * j;
 118         }
 119 }
 120
 121 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 122                                        const struct mipi_dsi_msg *msg)
 123 {
 124         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 125         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 126         struct drm_i915_private *dev_priv = to_i915(dev);
 127         enum port port = intel_dsi_host->port;
 128         struct mipi_dsi_packet packet;
 129         ssize_t ret;
 130         const u8 *header, *data;
 131         i915_reg_t data_reg, ctrl_reg;
 132         u32 data_mask, ctrl_mask;
 133
 134         ret = mipi_dsi_create_packet(&packet, msg);
 135         if (ret < 0)
 136                 return ret;
 137
 138         header = packet.header;
 139         data = packet.payload;
 140
 141         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 142                 data_reg = MIPI_LP_GEN_DATA(port);
 143                 data_mask = LP_DATA_FIFO_FULL;
 144                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 145                 ctrl_mask = LP_CTRL_FIFO_FULL;
 146         } else {
 147                 data_reg = MIPI_HS_GEN_DATA(port);
 148                 data_mask = HS_DATA_FIFO_FULL;
 149                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 150                 ctrl_mask = HS_CTRL_FIFO_FULL;
 151         }
 152
 153         /* note: this is never true for reads */
 154         if (packet.payload_length) {
 155                 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 156                                             data_mask, 50))
 157                         drm_err(&dev_priv->drm,
 158                                 "Timeout waiting for HS/LP DATA FIFO !full\n");
 159
 160                 write_data(dev_priv, data_reg, packet.payload,
 161                            packet.payload_length);
 162         }
 163
 164         if (msg->rx_len) {
 165                 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
 166                                GEN_READ_DATA_AVAIL);
 167         }
 168
 169         if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 170                                     ctrl_mask, 50)) {
 171                 drm_err(&dev_priv->drm,
 172                         "Timeout waiting for HS/LP CTRL FIFO !full\n");
 173         }
 174
 175         intel_de_write(dev_priv, ctrl_reg,
 176                        header[2] << 16 | header[1] << 8 | header[0]);
 177
 178         /* ->rx_len is set only for reads */
 179         if (msg->rx_len) {
 180                 data_mask = GEN_READ_DATA_AVAIL;
 181                 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
 182                                           data_mask, 50))
 183                         drm_err(&dev_priv->drm,
 184                                 "Timeout waiting for read data.\n");
 185
 186                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 187         }
 188
 189         /* XXX: fix for reads and writes */
 190         return 4 + packet.payload_length;
 191 }
 192
 193 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 194                                  struct mipi_dsi_device *dsi)
 195 {
 196         return 0;
 197 }
 198
 199 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 200                                  struct mipi_dsi_device *dsi)
 201 {
 202         return 0;
 203 }
 204
 205 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 206         .attach = intel_dsi_host_attach,
 207         .detach = intel_dsi_host_detach,
 208         .transfer = intel_dsi_host_transfer,
 209 };
 210
 211 /*
 212  * send a video mode command
 213  *
 214  * XXX: commands with data in MIPI_DPI_DATA?
 215  */
 216 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 217                         enum port port)
 218 {
 219         struct drm_encoder *encoder = &intel_dsi->base.base;
 220         struct drm_device *dev = encoder->dev;
 221         struct drm_i915_private *dev_priv = to_i915(dev);
 222         u32 mask;
 223
 224         /* XXX: pipe, hs */
 225         if (hs)
 226                 cmd &= ~DPI_LP_MODE;
 227         else
 228                 cmd |= DPI_LP_MODE;
 229
 230         /* clear bit */
 231         intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 232
 233         /* XXX: old code skips write if control unchanged */
 234         if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
 235                 drm_dbg_kms(&dev_priv->drm,
 236                             "Same special packet %02x twice in a row.\n", cmd);
 237
 238         intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
 239
 240         mask = SPL_PKT_SENT_INTERRUPT;
 241         if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
 242                 drm_err(&dev_priv->drm,
 243                         "Video mode command 0x%08x send failed.\n", cmd);
 244
 245         return 0;
 246 }
 247
 248 static void band_gap_reset(struct drm_i915_private *dev_priv)
 249 {
 250         vlv_flisdsi_get(dev_priv);
 251
 252         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 253         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 254         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 255         udelay(150);
 256         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 257         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 258
 259         vlv_flisdsi_put(dev_priv);
 260 }
 261
 262 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 263                                     struct intel_crtc_state *pipe_config,
 264                                     struct drm_connector_state *conn_state)
 265 {
 266         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 267         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 268                                                    base);
 269         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 270         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 271         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 272         int ret;
 273
 274         drm_dbg_kms(&dev_priv->drm, "\n");
 275         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 276
 277         if (fixed_mode) {
 278                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 279
 280                 if (HAS_GMCH(dev_priv))
 281                         intel_gmch_panel_fitting(pipe_config, conn_state);
 282                 else
 283                         intel_pch_panel_fitting(pipe_config, conn_state);
 284         }
 285
 286         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 287                 return -EINVAL;
 288
 289         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 290         adjusted_mode->flags = 0;
 291
 292         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 293                 pipe_config->pipe_bpp = 24;
 294         else
 295                 pipe_config->pipe_bpp = 18;
 296
 297         if (IS_GEN9_LP(dev_priv)) {
 298                 /* Enable Frame time stamp based scanline reporting */
 299                 adjusted_mode->private_flags |=
 300                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 301
 302                 /* Dual link goes to DSI transcoder A. */
 303                 if (intel_dsi->ports == BIT(PORT_C))
 304                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 305                 else
 306                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 307
 308                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 309                 if (ret)
 310                         return -EINVAL;
 311         } else {
 312                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 313                 if (ret)
 314                         return -EINVAL;
 315         }
 316
 317         pipe_config->clock_set = true;
 318
 319         return 0;
 320 }
 321
 322 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 323 {
 324         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 325         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 326         enum port port;
 327         u32 tmp;
 328         bool cold_boot = false;
 329
 330         /* Set the MIPI mode
 331          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 332          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 333          */
 334         for_each_dsi_port(port, intel_dsi->ports) {
 335                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 336                 intel_de_write(dev_priv, MIPI_CTRL(port),
 337                                tmp | GLK_MIPIIO_ENABLE);
 338         }
 339
 340         /* Put the IO into reset */
 341         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 342         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 343         intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
 344
 345         /* Program LP Wake */
 346         for_each_dsi_port(port, intel_dsi->ports) {
 347                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 348                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
 349                         tmp &= ~GLK_LP_WAKE;
 350                 else
 351                         tmp |= GLK_LP_WAKE;
 352                 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
 353         }
 354
 355         /* Wait for Pwr ACK */
 356         for_each_dsi_port(port, intel_dsi->ports) {
 357                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 358                                           GLK_MIPIIO_PORT_POWERED, 20))
 359                         drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
 360         }
 361
 362         /* Check for cold boot scenario */
 363         for_each_dsi_port(port, intel_dsi->ports) {
 364                 cold_boot |=
 365                         !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
 366         }
 367
 368         return cold_boot;
 369 }
 370
 371 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 372 {
 373         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 374         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 375         enum port port;
 376         u32 val;
 377
 378         /* Wait for MIPI PHY status bit to set */
 379         for_each_dsi_port(port, intel_dsi->ports) {
 380                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 381                                           GLK_PHY_STATUS_PORT_READY, 20))
 382                         drm_err(&dev_priv->drm, "PHY is not ON\n");
 383         }
 384
 385         /* Get IO out of reset */
 386         val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 387         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
 388                        val | GLK_MIPIIO_RESET_RELEASED);
 389
 390         /* Get IO out of Low power state*/
 391         for_each_dsi_port(port, intel_dsi->ports) {
 392                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 393                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 394                         val &= ~ULPS_STATE_MASK;
 395                         val |= DEVICE_READY;
 396                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 397                         usleep_range(10, 15);
 398                 } else {
 399                         /* Enter ULPS */
 400                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 401                         val &= ~ULPS_STATE_MASK;
 402                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 403                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 404
 405                         /* Wait for ULPS active */
 406                         if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 407                                                     GLK_ULPS_NOT_ACTIVE, 20))
 408                                 drm_err(&dev_priv->drm, "ULPS not active\n");
 409
 410                         /* Exit ULPS */
 411                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 412                         val &= ~ULPS_STATE_MASK;
 413                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 414                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 415
 416                         /* Enter Normal Mode */
 417                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 418                         val &= ~ULPS_STATE_MASK;
 419                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 420                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 421
 422                         val = intel_de_read(dev_priv, MIPI_CTRL(port));
 423                         val &= ~GLK_LP_WAKE;
 424                         intel_de_write(dev_priv, MIPI_CTRL(port), val);
 425                 }
 426         }
 427
 428         /* Wait for Stop state */
 429         for_each_dsi_port(port, intel_dsi->ports) {
 430                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 431                                           GLK_DATA_LANE_STOP_STATE, 20))
 432                         drm_err(&dev_priv->drm,
 433                                 "Date lane not in STOP state\n");
 434         }
 435
 436         /* Wait for AFE LATCH */
 437         for_each_dsi_port(port, intel_dsi->ports) {
 438                 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
 439                                           AFE_LATCHOUT, 20))
 440                         drm_err(&dev_priv->drm,
 441                                 "D-PHY not entering LP-11 state\n");
 442         }
 443 }
 444
 445 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 446 {
 447         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 448         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 449         enum port port;
 450         u32 val;
 451
 452         drm_dbg_kms(&dev_priv->drm, "\n");
 453
 454         /* Enable MIPI PHY transparent latch */
 455         for_each_dsi_port(port, intel_dsi->ports) {
 456                 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
 457                 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port),
 458                                val | LP_OUTPUT_HOLD);
 459                 usleep_range(2000, 2500);
 460         }
 461
 462         /* Clear ULPS and set device ready */
 463         for_each_dsi_port(port, intel_dsi->ports) {
 464                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 465                 val &= ~ULPS_STATE_MASK;
 466                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 467                 usleep_range(2000, 2500);
 468                 val |= DEVICE_READY;
 469                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 470         }
 471 }
 472
 473 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 474 {
 475         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 476         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 477         enum port port;
 478         u32 val;
 479
 480         drm_dbg_kms(&dev_priv->drm, "\n");
 481
 482         vlv_flisdsi_get(dev_priv);
 483         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 484          * needed everytime after power gate */
 485         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 486         vlv_flisdsi_put(dev_priv);
 487
 488         /* bandgap reset is needed after everytime we do power gate */
 489         band_gap_reset(dev_priv);
 490
 491         for_each_dsi_port(port, intel_dsi->ports) {
 492
 493                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 494                                ULPS_STATE_ENTER);
 495                 usleep_range(2500, 3000);
 496
 497                 /* Enable MIPI PHY transparent latch
 498                  * Common bit for both MIPI Port A & MIPI Port C
 499                  * No similar bit in MIPI Port C reg
 500                  */
 501                 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A));
 502                 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A),
 503                                val | LP_OUTPUT_HOLD);
 504                 usleep_range(1000, 1500);
 505
 506                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 507                                ULPS_STATE_EXIT);
 508                 usleep_range(2500, 3000);
 509
 510                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 511                                DEVICE_READY);
 512                 usleep_range(2500, 3000);
 513         }
 514 }
 515
 516 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 517 {
 518         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 519
 520         if (IS_GEMINILAKE(dev_priv))
 521                 glk_dsi_device_ready(encoder);
 522         else if (IS_GEN9_LP(dev_priv))
 523                 bxt_dsi_device_ready(encoder);
 524         else
 525                 vlv_dsi_device_ready(encoder);
 526 }
 527
 528 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 529 {
 530         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 531         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 532         enum port port;
 533         u32 val;
 534
 535         /* Enter ULPS */
 536         for_each_dsi_port(port, intel_dsi->ports) {
 537                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 538                 val &= ~ULPS_STATE_MASK;
 539                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 540                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 541         }
 542
 543         /* Wait for MIPI PHY status bit to unset */
 544         for_each_dsi_port(port, intel_dsi->ports) {
 545                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 546                                             GLK_PHY_STATUS_PORT_READY, 20))
 547                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 548         }
 549
 550         /* Wait for Pwr ACK bit to unset */
 551         for_each_dsi_port(port, intel_dsi->ports) {
 552                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 553                                             GLK_MIPIIO_PORT_POWERED, 20))
 554                         drm_err(&dev_priv->drm,
 555                                 "MIPI IO Port is not powergated\n");
 556         }
 557 }
 558
 559 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 560 {
 561         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 562         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 563         enum port port;
 564         u32 tmp;
 565
 566         /* Put the IO into reset */
 567         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 568         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 569         intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
 570
 571         /* Wait for MIPI PHY status bit to unset */
 572         for_each_dsi_port(port, intel_dsi->ports) {
 573                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 574                                             GLK_PHY_STATUS_PORT_READY, 20))
 575                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 576         }
 577
 578         /* Clear MIPI mode */
 579         for_each_dsi_port(port, intel_dsi->ports) {
 580                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 581                 tmp &= ~GLK_MIPIIO_ENABLE;
 582                 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
 583         }
 584 }
 585
 586 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 587 {
 588         glk_dsi_enter_low_power_mode(encoder);
 589         glk_dsi_disable_mipi_io(encoder);
 590 }
 591
 592 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 593 {
 594         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 595         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 596         enum port port;
 597
 598         drm_dbg_kms(&dev_priv->drm, "\n");
 599         for_each_dsi_port(port, intel_dsi->ports) {
 600                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 601                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 602                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 603                 u32 val;
 604
 605                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 606                                DEVICE_READY | ULPS_STATE_ENTER);
 607                 usleep_range(2000, 2500);
 608
 609                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 610                                DEVICE_READY | ULPS_STATE_EXIT);
 611                 usleep_range(2000, 2500);
 612
 613                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 614                                DEVICE_READY | ULPS_STATE_ENTER);
 615                 usleep_range(2000, 2500);
 616
 617                 /*
 618                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 619                  * Port A only. MIPI Port C has no similar bit for checking.
 620                  */
 621                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 622                     intel_de_wait_for_clear(dev_priv, port_ctrl,
 623                                             AFE_LATCHOUT, 30))
 624                         drm_err(&dev_priv->drm, "DSI LP not going Low\n");
 625
 626                 /* Disable MIPI PHY transparent latch */
 627                 val = intel_de_read(dev_priv, port_ctrl);
 628                 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD);
 629                 usleep_range(1000, 1500);
 630
 631                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
 632                 usleep_range(2000, 2500);
 633         }
 634 }
 635
 636 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 637                                   const struct intel_crtc_state *crtc_state)
 638 {
 639         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 640         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 641         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 642         enum port port;
 643
 644         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 645                 u32 temp;
 646                 if (IS_GEN9_LP(dev_priv)) {
 647                         for_each_dsi_port(port, intel_dsi->ports) {
 648                                 temp = intel_de_read(dev_priv,
 649                                                      MIPI_CTRL(port));
 650                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 651                                         intel_dsi->pixel_overlap <<
 652                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 653                                 intel_de_write(dev_priv, MIPI_CTRL(port),
 654                                                temp);
 655                         }
 656                 } else {
 657                         temp = intel_de_read(dev_priv, VLV_CHICKEN_3);
 658                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 659                                         intel_dsi->pixel_overlap <<
 660                                         PIXEL_OVERLAP_CNT_SHIFT;
 661                         intel_de_write(dev_priv, VLV_CHICKEN_3, temp);
 662                 }
 663         }
 664
 665         for_each_dsi_port(port, intel_dsi->ports) {
 666                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 667                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 668                 u32 temp;
 669
 670                 temp = intel_de_read(dev_priv, port_ctrl);
 671
 672                 temp &= ~LANE_CONFIGURATION_MASK;
 673                 temp &= ~DUAL_LINK_MODE_MASK;
 674
 675                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 676                         temp |= (intel_dsi->dual_link - 1)
 677                                                 << DUAL_LINK_MODE_SHIFT;
 678                         if (IS_BROXTON(dev_priv))
 679                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 680                         else
 681                                 temp |= crtc->pipe ?
 682                                         LANE_CONFIGURATION_DUAL_LINK_B :
 683                                         LANE_CONFIGURATION_DUAL_LINK_A;
 684                 }
 685
 686                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 687                         temp |= DITHERING_ENABLE;
 688
 689                 /* assert ip_tg_enable signal */
 690                 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
 691                 intel_de_posting_read(dev_priv, port_ctrl);
 692         }
 693 }
 694
 695 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 696 {
 697         struct drm_device *dev = encoder->base.dev;
 698         struct drm_i915_private *dev_priv = to_i915(dev);
 699         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 700         enum port port;
 701
 702         for_each_dsi_port(port, intel_dsi->ports) {
 703                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 704                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 705                 u32 temp;
 706
 707                 /* de-assert ip_tg_enable signal */
 708                 temp = intel_de_read(dev_priv, port_ctrl);
 709                 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE);
 710                 intel_de_posting_read(dev_priv, port_ctrl);
 711         }
 712 }
 713
 714 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 715                               const struct intel_crtc_state *pipe_config);
 716 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 717
 718 /*
 719  * Panel enable/disable sequences from the VBT spec.
 720  *
 721  * Note the spec has AssertReset / DeassertReset swapped from their
 722  * usual naming. We use the normal names to avoid confusion (so below
 723  * they are swapped compared to the spec).
 724  *
 725  * Steps starting with MIPI refer to VBT sequences, note that for v2
 726  * VBTs several steps which have a VBT in v2 are expected to be handled
 727  * directly by the driver, by directly driving gpios for example.
 728  *
 729  * v2 video mode seq         v3 video mode seq         command mode seq
 730  * - power on                - MIPIPanelPowerOn        - power on
 731  * - wait t1+t2                                        - wait t1+t2
 732  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 733  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 734  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 735  *                                                     - MIPITearOn
 736  *                                                     - MIPIDisplayOn
 737  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 738  * - MIPIDisplayOn           - MIPIDisplayOn
 739  * - wait t5                                           - wait t5
 740  * - backlight on            - MIPIBacklightOn         - backlight on
 741  * ...                       ...                       ... issue mem cmds ...
 742  * - backlight off           - MIPIBacklightOff        - backlight off
 743  * - wait t6                                           - wait t6
 744  * - MIPIDisplayOff
 745  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 746  *                                                     - MIPITearOff
 747  *                           - MIPIDisplayOff          - MIPIDisplayOff
 748  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 749  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 750  * - wait t3                                           - wait t3
 751  * - power off               - MIPIPanelPowerOff       - power off
 752  * - wait t4                                           - wait t4
 753  */
 754
 755 /*
 756  * DSI port enable has to be done before pipe and plane enable, so we do it in
 757  * the pre_enable hook instead of the enable hook.
 758  */
 759 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 760                                  struct intel_encoder *encoder,
 761                                  const struct intel_crtc_state *pipe_config,
 762                                  const struct drm_connector_state *conn_state)
 763 {
 764         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 765         struct drm_crtc *crtc = pipe_config->uapi.crtc;
 766         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 768         enum pipe pipe = intel_crtc->pipe;
 769         enum port port;
 770         u32 val;
 771         bool glk_cold_boot = false;
 772
 773         drm_dbg_kms(&dev_priv->drm, "\n");
 774
 775         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 776
 777         /*
 778          * The BIOS may leave the PLL in a wonky state where it doesn't
 779          * lock. It needs to be fully powered down to fix it.
 780          */
 781         if (IS_GEN9_LP(dev_priv)) {
 782                 bxt_dsi_pll_disable(encoder);
 783                 bxt_dsi_pll_enable(encoder, pipe_config);
 784         } else {
 785                 vlv_dsi_pll_disable(encoder);
 786                 vlv_dsi_pll_enable(encoder, pipe_config);
 787         }
 788
 789         if (IS_BROXTON(dev_priv)) {
 790                 /* Add MIPI IO reset programming for modeset */
 791                 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
 792                 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
 793                                val | MIPIO_RST_CTRL);
 794
 795                 /* Power up DSI regulator */
 796                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 797                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 798         }
 799
 800         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 801                 u32 val;
 802
 803                 /* Disable DPOunit clock gating, can stall pipe */
 804                 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
 805                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 806                 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 807         }
 808
 809         if (!IS_GEMINILAKE(dev_priv))
 810                 intel_dsi_prepare(encoder, pipe_config);
 811
 812         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 813         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 814
 815         /* Deassert reset */
 816         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 817
 818         if (IS_GEMINILAKE(dev_priv)) {
 819                 glk_cold_boot = glk_dsi_enable_io(encoder);
 820
 821                 /* Prepare port in cold boot(s3/s4) scenario */
 822                 if (glk_cold_boot)
 823                         intel_dsi_prepare(encoder, pipe_config);
 824         }
 825
 826         /* Put device in ready state (LP-11) */
 827         intel_dsi_device_ready(encoder);
 828
 829         /* Prepare port in normal boot scenario */
 830         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 831                 intel_dsi_prepare(encoder, pipe_config);
 832
 833         /* Send initialization commands in LP mode */
 834         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 835
 836         /* Enable port in pre-enable phase itself because as per hw team
 837          * recommendation, port should be enabled befor plane & pipe */
 838         if (is_cmd_mode(intel_dsi)) {
 839                 for_each_dsi_port(port, intel_dsi->ports)
 840                         intel_de_write(dev_priv,
 841                                        MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 842                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 843                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 844         } else {
 845                 msleep(20); /* XXX */
 846                 for_each_dsi_port(port, intel_dsi->ports)
 847                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 848                 intel_dsi_msleep(intel_dsi, 100);
 849
 850                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 851
 852                 intel_dsi_port_enable(encoder, pipe_config);
 853         }
 854
 855         intel_panel_enable_backlight(pipe_config, conn_state);
 856         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 857 }
 858
 859 static void bxt_dsi_enable(struct intel_atomic_state *state,
 860                            struct intel_encoder *encoder,
 861                            const struct intel_crtc_state *crtc_state,
 862                            const struct drm_connector_state *conn_state)
 863 {
 864         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
 865
 866         intel_crtc_vblank_on(crtc_state);
 867 }
 868
 869 /*
 870  * DSI port disable has to be done after pipe and plane disable, so we do it in
 871  * the post_disable hook.
 872  */
 873 static void intel_dsi_disable(struct intel_atomic_state *state,
 874                               struct intel_encoder *encoder,
 875                               const struct intel_crtc_state *old_crtc_state,
 876                               const struct drm_connector_state *old_conn_state)
 877 {
 878         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 879         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 880         enum port port;
 881
 882         drm_dbg_kms(&i915->drm, "\n");
 883
 884         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 885         intel_panel_disable_backlight(old_conn_state);
 886
 887         /*
 888          * According to the spec we should send SHUTDOWN before
 889          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 890          * has shown that the v3 sequence works for v2 VBTs too
 891          */
 892         if (is_vid_mode(intel_dsi)) {
 893                 /* Send Shutdown command to the panel in LP mode */
 894                 for_each_dsi_port(port, intel_dsi->ports)
 895                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 896                 msleep(10);
 897         }
 898 }
 899
 900 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 901 {
 902         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 903
 904         if (IS_GEMINILAKE(dev_priv))
 905                 glk_dsi_clear_device_ready(encoder);
 906         else
 907                 vlv_dsi_clear_device_ready(encoder);
 908 }
 909
 910 static void intel_dsi_post_disable(struct intel_atomic_state *state,
 911                                    struct intel_encoder *encoder,
 912                                    const struct intel_crtc_state *old_crtc_state,
 913                                    const struct drm_connector_state *old_conn_state)
 914 {
 915         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 916         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 917         enum port port;
 918         u32 val;
 919
 920         drm_dbg_kms(&dev_priv->drm, "\n");
 921
 922         if (IS_GEN9_LP(dev_priv)) {
 923                 intel_crtc_vblank_off(old_crtc_state);
 924
 925                 skl_scaler_disable(old_crtc_state);
 926         }
 927
 928         if (is_vid_mode(intel_dsi)) {
 929                 for_each_dsi_port(port, intel_dsi->ports)
 930                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 931
 932                 intel_dsi_port_disable(encoder);
 933                 usleep_range(2000, 5000);
 934         }
 935
 936         intel_dsi_unprepare(encoder);
 937
 938         /*
 939          * if disable packets are sent before sending shutdown packet then in
 940          * some next enable sequence send turn on packet error is observed
 941          */
 942         if (is_cmd_mode(intel_dsi))
 943                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 944         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 945
 946         /* Transition to LP-00 */
 947         intel_dsi_clear_device_ready(encoder);
 948
 949         if (IS_BROXTON(dev_priv)) {
 950                 /* Power down DSI regulator to save power */
 951                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 952                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
 953                                HS_IO_CTRL_SELECT);
 954
 955                 /* Add MIPI IO reset programming for modeset */
 956                 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
 957                 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
 958                                val & ~MIPIO_RST_CTRL);
 959         }
 960
 961         if (IS_GEN9_LP(dev_priv)) {
 962                 bxt_dsi_pll_disable(encoder);
 963         } else {
 964                 u32 val;
 965
 966                 vlv_dsi_pll_disable(encoder);
 967
 968                 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
 969                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 970                 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 971         }
 972
 973         /* Assert reset */
 974         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 975
 976         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 977         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 978
 979         /*
 980          * FIXME As we do with eDP, just make a note of the time here
 981          * and perform the wait before the next panel power on.
 982          */
 983         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
 984 }
 985
 986 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 987                                    enum pipe *pipe)
 988 {
 989         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 990         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 991         intel_wakeref_t wakeref;
 992         enum port port;
 993         bool active = false;
 994
 995         drm_dbg_kms(&dev_priv->drm, "\n");
 996
 997         wakeref = intel_display_power_get_if_enabled(dev_priv,
 998                                                      encoder->power_domain);
 999         if (!wakeref)
1000                 return false;
1001
1002         /*
1003          * On Broxton the PLL needs to be enabled with a valid divider
1004          * configuration, otherwise accessing DSI registers will hang the
1005          * machine. See BSpec North Display Engine registers/MIPI[BXT].
1006          */
1007         if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
1008                 goto out_put_power;
1009
1010         /* XXX: this only works for one DSI output */
1011         for_each_dsi_port(port, intel_dsi->ports) {
1012                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
1013                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1014                 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
1015
1016                 /*
1017                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1018                  * bit in port C control register does not get set. As a
1019                  * workaround, check pipe B conf instead.
1020                  */
1021                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1022                     port == PORT_C)
1023                         enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1024
1025                 /* Try command mode if video mode not enabled */
1026                 if (!enabled) {
1027                         u32 tmp = intel_de_read(dev_priv,
1028                                                 MIPI_DSI_FUNC_PRG(port));
1029                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1030                 }
1031
1032                 if (!enabled)
1033                         continue;
1034
1035                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
1036                         continue;
1037
1038                 if (IS_GEN9_LP(dev_priv)) {
1039                         u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1040                         tmp &= BXT_PIPE_SELECT_MASK;
1041                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1042
1043                         if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
1044                                 continue;
1045
1046                         *pipe = tmp;
1047                 } else {
1048                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1049                 }
1050
1051                 active = true;
1052                 break;
1053         }
1054
1055 out_put_power:
1056         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1057
1058         return active;
1059 }
1060
1061 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1062                                     struct intel_crtc_state *pipe_config)
1063 {
1064         struct drm_device *dev = encoder->base.dev;
1065         struct drm_i915_private *dev_priv = to_i915(dev);
1066         struct drm_display_mode *adjusted_mode =
1067                                         &pipe_config->hw.adjusted_mode;
1068         struct drm_display_mode *adjusted_mode_sw;
1069         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1070         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1071         unsigned int lane_count = intel_dsi->lane_count;
1072         unsigned int bpp, fmt;
1073         enum port port;
1074         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1075         u16 hfp_sw, hsync_sw, hbp_sw;
1076         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1077                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1078
1079         /* FIXME: hw readout should not depend on SW state */
1080         adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1081
1082         /*
1083          * Atleast one port is active as encoder->get_config called only if
1084          * encoder->get_hw_state() returns true.
1085          */
1086         for_each_dsi_port(port, intel_dsi->ports) {
1087                 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1088                         break;
1089         }
1090
1091         fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1092         bpp = mipi_dsi_pixel_format_to_bpp(
1093                         pixel_format_from_register_bits(fmt));
1094
1095         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1096
1097         /* Enable Frame time stamo based scanline reporting */
1098         adjusted_mode->private_flags |=
1099                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1100
1101         /* In terms of pixels */
1102         adjusted_mode->crtc_hdisplay =
1103                                 intel_de_read(dev_priv,
1104                                               BXT_MIPI_TRANS_HACTIVE(port));
1105         adjusted_mode->crtc_vdisplay =
1106                                 intel_de_read(dev_priv,
1107                                               BXT_MIPI_TRANS_VACTIVE(port));
1108         adjusted_mode->crtc_vtotal =
1109                                 intel_de_read(dev_priv,
1110                                               BXT_MIPI_TRANS_VTOTAL(port));
1111
1112         hactive = adjusted_mode->crtc_hdisplay;
1113         hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1114
1115         /*
1116          * Meaningful for video mode non-burst sync pulse mode only,
1117          * can be zero for non-burst sync events and burst modes
1118          */
1119         hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1120         hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1121
1122         /* harizontal values are in terms of high speed byte clock */
1123         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1124                                                 intel_dsi->burst_mode_ratio);
1125         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1126                                                 intel_dsi->burst_mode_ratio);
1127         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1128                                                 intel_dsi->burst_mode_ratio);
1129
1130         if (intel_dsi->dual_link) {
1131                 hfp *= 2;
1132                 hsync *= 2;
1133                 hbp *= 2;
1134         }
1135
1136         /* vertical values are in terms of lines */
1137         vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1138         vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1139         vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port));
1140
1141         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1142         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1143         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1144         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1145         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1146
1147         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1148         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1149         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1150         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1151
1152         /*
1153          * In BXT DSI there is no regs programmed with few horizontal timings
1154          * in Pixels but txbyteclkhs.. So retrieval process adds some
1155          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1156          * Actually here for the given adjusted_mode, we are calculating the
1157          * value programmed to the port and then back to the horizontal timing
1158          * param in pixels. This is the expected value, including roundup errors
1159          * And if that is same as retrieved value from port, then
1160          * (HW state) adjusted_mode's horizontal timings are corrected to
1161          * match with SW state to nullify the errors.
1162          */
1163         /* Calculating the value programmed to the Port register */
1164         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1165                                         adjusted_mode_sw->crtc_hdisplay;
1166         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1167                                         adjusted_mode_sw->crtc_hsync_start;
1168         hbp_sw = adjusted_mode_sw->crtc_htotal -
1169                                         adjusted_mode_sw->crtc_hsync_end;
1170
1171         if (intel_dsi->dual_link) {
1172                 hfp_sw /= 2;
1173                 hsync_sw /= 2;
1174                 hbp_sw /= 2;
1175         }
1176
1177         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1178                                                 intel_dsi->burst_mode_ratio);
1179         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1180                             intel_dsi->burst_mode_ratio);
1181         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1182                                                 intel_dsi->burst_mode_ratio);
1183
1184         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1185         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1186                                                 intel_dsi->burst_mode_ratio);
1187         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1188                                                 intel_dsi->burst_mode_ratio);
1189         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1190                                                 intel_dsi->burst_mode_ratio);
1191
1192         if (intel_dsi->dual_link) {
1193                 hfp_sw *= 2;
1194                 hsync_sw *= 2;
1195                 hbp_sw *= 2;
1196         }
1197
1198         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1199                                                         hsync_sw + hbp_sw;
1200         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1201         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1202         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1203         crtc_hblank_end_sw = crtc_htotal_sw;
1204
1205         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1206                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1207
1208         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1209                 adjusted_mode->crtc_hsync_start =
1210                                         adjusted_mode_sw->crtc_hsync_start;
1211
1212         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1213                 adjusted_mode->crtc_hsync_end =
1214                                         adjusted_mode_sw->crtc_hsync_end;
1215
1216         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1217                 adjusted_mode->crtc_hblank_start =
1218                                         adjusted_mode_sw->crtc_hblank_start;
1219
1220         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1221                 adjusted_mode->crtc_hblank_end =
1222                                         adjusted_mode_sw->crtc_hblank_end;
1223 }
1224
1225 static void intel_dsi_get_config(struct intel_encoder *encoder,
1226                                  struct intel_crtc_state *pipe_config)
1227 {
1228         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1229         u32 pclk;
1230         drm_dbg_kms(&dev_priv->drm, "\n");
1231
1232         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1233
1234         if (IS_GEN9_LP(dev_priv)) {
1235                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1236                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1237         } else {
1238                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1239         }
1240
1241         if (pclk) {
1242                 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1243                 pipe_config->port_clock = pclk;
1244         }
1245 }
1246
1247 /* return txclkesc cycles in terms of divider and duration in us */
1248 static u16 txclkesc(u32 divider, unsigned int us)
1249 {
1250         switch (divider) {
1251         case ESCAPE_CLOCK_DIVIDER_1:
1252         default:
1253                 return 20 * us;
1254         case ESCAPE_CLOCK_DIVIDER_2:
1255                 return 10 * us;
1256         case ESCAPE_CLOCK_DIVIDER_4:
1257                 return 5 * us;
1258         }
1259 }
1260
1261 static void set_dsi_timings(struct drm_encoder *encoder,
1262                             const struct drm_display_mode *adjusted_mode)
1263 {
1264         struct drm_device *dev = encoder->dev;
1265         struct drm_i915_private *dev_priv = to_i915(dev);
1266         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1267         enum port port;
1268         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1269         unsigned int lane_count = intel_dsi->lane_count;
1270
1271         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1272
1273         hactive = adjusted_mode->crtc_hdisplay;
1274         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1275         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1276         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1277
1278         if (intel_dsi->dual_link) {
1279                 hactive /= 2;
1280                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1281                         hactive += intel_dsi->pixel_overlap;
1282                 hfp /= 2;
1283                 hsync /= 2;
1284                 hbp /= 2;
1285         }
1286
1287         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1288         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1289         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1290
1291         /* horizontal values are in terms of high speed byte clock */
1292         hactive = txbyteclkhs(hactive, bpp, lane_count,
1293                               intel_dsi->burst_mode_ratio);
1294         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1295         hsync = txbyteclkhs(hsync, bpp, lane_count,
1296                             intel_dsi->burst_mode_ratio);
1297         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1298
1299         for_each_dsi_port(port, intel_dsi->ports) {
1300                 if (IS_GEN9_LP(dev_priv)) {
1301                         /*
1302                          * Program hdisplay and vdisplay on MIPI transcoder.
1303                          * This is different from calculated hactive and
1304                          * vactive, as they are calculated per channel basis,
1305                          * whereas these values should be based on resolution.
1306                          */
1307                         intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1308                                        adjusted_mode->crtc_hdisplay);
1309                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1310                                        adjusted_mode->crtc_vdisplay);
1311                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1312                                        adjusted_mode->crtc_vtotal);
1313                 }
1314
1315                 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1316                                hactive);
1317                 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1318
1319                 /* meaningful for video mode non-burst sync pulse mode only,
1320                  * can be zero for non-burst sync events and burst modes */
1321                 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1322                                hsync);
1323                 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1324
1325                 /* vertical values are in terms of lines */
1326                 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1327                 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1328                                vsync);
1329                 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1330         }
1331 }
1332
1333 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1334 {
1335         switch (fmt) {
1336         case MIPI_DSI_FMT_RGB888:
1337                 return VID_MODE_FORMAT_RGB888;
1338         case MIPI_DSI_FMT_RGB666:
1339                 return VID_MODE_FORMAT_RGB666;
1340         case MIPI_DSI_FMT_RGB666_PACKED:
1341                 return VID_MODE_FORMAT_RGB666_PACKED;
1342         case MIPI_DSI_FMT_RGB565:
1343                 return VID_MODE_FORMAT_RGB565;
1344         default:
1345                 MISSING_CASE(fmt);
1346                 return VID_MODE_FORMAT_RGB666;
1347         }
1348 }
1349
1350 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1351                               const struct intel_crtc_state *pipe_config)
1352 {
1353         struct drm_encoder *encoder = &intel_encoder->base;
1354         struct drm_device *dev = encoder->dev;
1355         struct drm_i915_private *dev_priv = to_i915(dev);
1356         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
1357         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1358         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1359         enum port port;
1360         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1361         u32 val, tmp;
1362         u16 mode_hdisplay;
1363
1364         drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe));
1365
1366         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1367
1368         if (intel_dsi->dual_link) {
1369                 mode_hdisplay /= 2;
1370                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1371                         mode_hdisplay += intel_dsi->pixel_overlap;
1372         }
1373
1374         for_each_dsi_port(port, intel_dsi->ports) {
1375                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1376                         /*
1377                          * escape clock divider, 20MHz, shared for A and C.
1378                          * device ready must be off when doing this! txclkesc?
1379                          */
1380                         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1381                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1382                         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1383                                        tmp | ESCAPE_CLOCK_DIVIDER_1);
1384
1385                         /* read request priority is per pipe */
1386                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1387                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1388                         intel_de_write(dev_priv, MIPI_CTRL(port),
1389                                        tmp | READ_REQUEST_PRIORITY_HIGH);
1390                 } else if (IS_GEN9_LP(dev_priv)) {
1391                         enum pipe pipe = intel_crtc->pipe;
1392
1393                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1394                         tmp &= ~BXT_PIPE_SELECT_MASK;
1395
1396                         tmp |= BXT_PIPE_SELECT(pipe);
1397                         intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
1398                 }
1399
1400                 /* XXX: why here, why like this? handling in irq handler?! */
1401                 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1402                 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1403
1404                 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1405                                intel_dsi->dphy_reg);
1406
1407                 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1408                                adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1409         }
1410
1411         set_dsi_timings(encoder, adjusted_mode);
1412
1413         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1414         if (is_cmd_mode(intel_dsi)) {
1415                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1416                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1417         } else {
1418                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1419                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1420         }
1421
1422         tmp = 0;
1423         if (intel_dsi->eotp_pkt == 0)
1424                 tmp |= EOT_DISABLE;
1425         if (intel_dsi->clock_stop)
1426                 tmp |= CLOCKSTOP;
1427
1428         if (IS_GEN9_LP(dev_priv)) {
1429                 tmp |= BXT_DPHY_DEFEATURE_EN;
1430                 if (!is_cmd_mode(intel_dsi))
1431                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1432         }
1433
1434         for_each_dsi_port(port, intel_dsi->ports) {
1435                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1436
1437                 /* timeouts for recovery. one frame IIUC. if counter expires,
1438                  * EOT and stop state. */
1439
1440                 /*
1441                  * In burst mode, value greater than one DPI line Time in byte
1442                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1443                  * said value is recommended.
1444                  *
1445                  * In non-burst mode, Value greater than one DPI frame time in
1446                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1447                  * said value is recommended.
1448                  *
1449                  * In DBI only mode, value greater than one DBI frame time in
1450                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1451                  * said value is recommended.
1452                  */
1453
1454                 if (is_vid_mode(intel_dsi) &&
1455                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1456                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1457                                        txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1458                 } else {
1459                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1460                                        txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1461                 }
1462                 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1463                                intel_dsi->lp_rx_timeout);
1464                 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1465                                intel_dsi->turn_arnd_val);
1466                 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1467                                intel_dsi->rst_timer_val);
1468
1469                 /* dphy stuff */
1470
1471                 /* in terms of low power clock */
1472                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1473                                txclkesc(intel_dsi->escape_clk_div, 100));
1474
1475                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1476                         /*
1477                          * BXT spec says write MIPI_INIT_COUNT for
1478                          * both the ports, even if only one is
1479                          * getting used. So write the other port
1480                          * if not in dual link mode.
1481                          */
1482                         intel_de_write(dev_priv,
1483                                        MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1484                                        intel_dsi->init_count);
1485                 }
1486
1487                 /* recovery disables */
1488                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1489
1490                 /* in terms of low power clock */
1491                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1492                                intel_dsi->init_count);
1493
1494                 /* in terms of txbyteclkhs. actual high to low switch +
1495                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1496                  *
1497                  * XXX: write MIPI_STOP_STATE_STALL?
1498                  */
1499                 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1500                                intel_dsi->hs_to_lp_count);
1501
1502                 /* XXX: low power clock equivalence in terms of byte clock.
1503                  * the number of byte clocks occupied in one low power clock.
1504                  * based on txbyteclkhs and txclkesc.
1505                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1506                  * ) / 105.???
1507                  */
1508                 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1509                                intel_dsi->lp_byte_clk);
1510
1511                 if (IS_GEMINILAKE(dev_priv)) {
1512                         intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1513                                        intel_dsi->lp_byte_clk);
1514                         /* Shadow of DPHY reg */
1515                         intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1516                                        intel_dsi->dphy_reg);
1517                 }
1518
1519                 /* the bw essential for transmitting 16 long packets containing
1520                  * 252 bytes meant for dcs write memory command is programmed in
1521                  * this register in terms of byte clocks. based on dsi transfer
1522                  * rate and the number of lanes configured the time taken to
1523                  * transmit 16 long packets in a dsi stream varies. */
1524                 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1525                                intel_dsi->bw_timer);
1526
1527                 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1528                                intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1529
1530                 if (is_vid_mode(intel_dsi))
1531                         /* Some panels might have resolution which is not a
1532                          * multiple of 64 like 1366 x 768. Enable RANDOM
1533                          * resolution support for such panels by default */
1534                         intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port),
1535                                        intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION);
1536         }
1537 }
1538
1539 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1540 {
1541         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1542         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1543         enum port port;
1544         u32 val;
1545
1546         if (IS_GEMINILAKE(dev_priv))
1547                 return;
1548
1549         for_each_dsi_port(port, intel_dsi->ports) {
1550                 /* Panel commands can be sent when clock is in LP11 */
1551                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1552
1553                 if (IS_GEN9_LP(dev_priv))
1554                         bxt_dsi_reset_clocks(encoder, port);
1555                 else
1556                         vlv_dsi_reset_clocks(encoder, port);
1557                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1558
1559                 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port));
1560                 val &= ~VID_MODE_FORMAT_MASK;
1561                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1562
1563                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1564         }
1565 }
1566
1567 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1568 {
1569         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1570
1571         intel_dsi_vbt_gpio_cleanup(intel_dsi);
1572         intel_encoder_destroy(encoder);
1573 }
1574
1575 static const struct drm_encoder_funcs intel_dsi_funcs = {
1576         .destroy = intel_dsi_encoder_destroy,
1577 };
1578
1579 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1580         .get_modes = intel_dsi_get_modes,
1581         .mode_valid = intel_dsi_mode_valid,
1582         .atomic_check = intel_digital_connector_atomic_check,
1583 };
1584
1585 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1586         .late_register = intel_connector_register,
1587         .early_unregister = intel_connector_unregister,
1588         .destroy = intel_connector_destroy,
1589         .fill_modes = drm_helper_probe_single_connector_modes,
1590         .atomic_get_property = intel_digital_connector_atomic_get_property,
1591         .atomic_set_property = intel_digital_connector_atomic_set_property,
1592         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1593         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1594 };
1595
1596 static void vlv_dsi_add_properties(struct intel_connector *connector)
1597 {
1598         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1599
1600         if (connector->panel.fixed_mode) {
1601                 u32 allowed_scalers;
1602
1603                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1604                 if (!HAS_GMCH(dev_priv))
1605                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1606
1607                 drm_connector_attach_scaling_mode_property(&connector->base,
1608                                                                 allowed_scalers);
1609
1610                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1611
1612                 drm_connector_set_panel_orientation_with_quirk(
1613                                 &connector->base,
1614                                 intel_dsi_get_panel_orientation(connector),
1615                                 connector->panel.fixed_mode->hdisplay,
1616                                 connector->panel.fixed_mode->vdisplay);
1617         }
1618 }
1619
1620 #define NS_KHZ_RATIO            1000000
1621
1622 #define PREPARE_CNT_MAX         0x3F
1623 #define EXIT_ZERO_CNT_MAX       0x3F
1624 #define CLK_ZERO_CNT_MAX        0xFF
1625 #define TRAIL_CNT_MAX           0x1F
1626
1627 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1628 {
1629         struct drm_device *dev = intel_dsi->base.base.dev;
1630         struct drm_i915_private *dev_priv = to_i915(dev);
1631         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1632         u32 tlpx_ns, extra_byte_count, tlpx_ui;
1633         u32 ui_num, ui_den;
1634         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1635         u32 ths_prepare_ns, tclk_trail_ns;
1636         u32 tclk_prepare_clkzero, ths_prepare_hszero;
1637         u32 lp_to_hs_switch, hs_to_lp_switch;
1638         u32 mul;
1639
1640         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1641
1642         switch (intel_dsi->lane_count) {
1643         case 1:
1644         case 2:
1645                 extra_byte_count = 2;
1646                 break;
1647         case 3:
1648                 extra_byte_count = 4;
1649                 break;
1650         case 4:
1651         default:
1652                 extra_byte_count = 3;
1653                 break;
1654         }
1655
1656         /* in Kbps */
1657         ui_num = NS_KHZ_RATIO;
1658         ui_den = intel_dsi_bitrate(intel_dsi);
1659
1660         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1661         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1662
1663         /*
1664          * B060
1665          * LP byte clock = TLPX/ (8UI)
1666          */
1667         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1668
1669         /* DDR clock period = 2 * UI
1670          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1671          * UI(nsec) = 10^6 / bitrate
1672          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1673          * DDR clock count  = ns_value / DDR clock period
1674          *
1675          * For GEMINILAKE dphy_param_reg will be programmed in terms of
1676          * HS byte clock count for other platform in HS ddr clock count
1677          */
1678         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1679         ths_prepare_ns = max(mipi_config->ths_prepare,
1680                              mipi_config->tclk_prepare);
1681
1682         /* prepare count */
1683         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1684
1685         if (prepare_cnt > PREPARE_CNT_MAX) {
1686                 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1687                             prepare_cnt);
1688                 prepare_cnt = PREPARE_CNT_MAX;
1689         }
1690
1691         /* exit zero count */
1692         exit_zero_cnt = DIV_ROUND_UP(
1693                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1694                                 ui_num * mul
1695                                 );
1696
1697         /*
1698          * Exit zero is unified val ths_zero and ths_exit
1699          * minimum value for ths_exit = 110ns
1700          * min (exit_zero_cnt * 2) = 110/UI
1701          * exit_zero_cnt = 55/UI
1702          */
1703         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1704                 exit_zero_cnt += 1;
1705
1706         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1707                 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1708                             exit_zero_cnt);
1709                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1710         }
1711
1712         /* clk zero count */
1713         clk_zero_cnt = DIV_ROUND_UP(
1714                                 (tclk_prepare_clkzero - ths_prepare_ns)
1715                                 * ui_den, ui_num * mul);
1716
1717         if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1718                 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1719                             clk_zero_cnt);
1720                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1721         }
1722
1723         /* trail count */
1724         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1725         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1726
1727         if (trail_cnt > TRAIL_CNT_MAX) {
1728                 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1729                             trail_cnt);
1730                 trail_cnt = TRAIL_CNT_MAX;
1731         }
1732
1733         /* B080 */
1734         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1735                                                 clk_zero_cnt << 8 | prepare_cnt;
1736
1737         /*
1738          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1739          *                                      mul + 10UI + Extra Byte Count
1740          *
1741          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1742          * Extra Byte Count is calculated according to number of lanes.
1743          * High Low Switch Count is the Max of LP to HS and
1744          * HS to LP switch count
1745          *
1746          */
1747         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1748
1749         /* B044 */
1750         /* FIXME:
1751          * The comment above does not match with the code */
1752         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1753                                                 exit_zero_cnt * mul + 10, 8);
1754
1755         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1756
1757         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1758         intel_dsi->hs_to_lp_count += extra_byte_count;
1759
1760         /* B088 */
1761         /* LP -> HS for clock lanes
1762          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1763          *                                              extra byte count
1764          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1765          *                                      2(in UI) + extra byte count
1766          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1767          *                                      8 + extra byte count
1768          */
1769         intel_dsi->clk_lp_to_hs_count =
1770                 DIV_ROUND_UP(
1771                         4 * tlpx_ui + prepare_cnt * 2 +
1772                         clk_zero_cnt * 2,
1773                         8);
1774
1775         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1776
1777         /* HS->LP for Clock Lanes
1778          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1779          *                                              Extra byte count
1780          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1781          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1782          *                                              Extra byte count
1783          */
1784         intel_dsi->clk_hs_to_lp_count =
1785                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1786                         8);
1787         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1788
1789         intel_dsi_log_params(intel_dsi);
1790 }
1791
1792 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1793 {
1794         struct drm_device *dev = &dev_priv->drm;
1795         struct intel_dsi *intel_dsi;
1796         struct intel_encoder *intel_encoder;
1797         struct drm_encoder *encoder;
1798         struct intel_connector *intel_connector;
1799         struct drm_connector *connector;
1800         struct drm_display_mode *current_mode, *fixed_mode;
1801         enum port port;
1802         enum pipe pipe;
1803
1804         drm_dbg_kms(&dev_priv->drm, "\n");
1805
1806         /* There is no detection method for MIPI so rely on VBT */
1807         if (!intel_bios_is_dsi_present(dev_priv, &port))
1808                 return;
1809
1810         if (IS_GEN9_LP(dev_priv))
1811                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1812         else
1813                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1814
1815         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1816         if (!intel_dsi)
1817                 return;
1818
1819         intel_connector = intel_connector_alloc();
1820         if (!intel_connector) {
1821                 kfree(intel_dsi);
1822                 return;
1823         }
1824
1825         intel_encoder = &intel_dsi->base;
1826         encoder = &intel_encoder->base;
1827         intel_dsi->attached_connector = intel_connector;
1828
1829         connector = &intel_connector->base;
1830
1831         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1832                          "DSI %c", port_name(port));
1833
1834         intel_encoder->compute_config = intel_dsi_compute_config;
1835         intel_encoder->pre_enable = intel_dsi_pre_enable;
1836         if (IS_GEN9_LP(dev_priv))
1837                 intel_encoder->enable = bxt_dsi_enable;
1838         intel_encoder->disable = intel_dsi_disable;
1839         intel_encoder->post_disable = intel_dsi_post_disable;
1840         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1841         intel_encoder->get_config = intel_dsi_get_config;
1842         intel_encoder->update_pipe = intel_panel_update_backlight;
1843
1844         intel_connector->get_hw_state = intel_connector_get_hw_state;
1845
1846         intel_encoder->port = port;
1847         intel_encoder->type = INTEL_OUTPUT_DSI;
1848         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1849         intel_encoder->cloneable = 0;
1850
1851         /*
1852          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1853          * port C. BXT isn't limited like this.
1854          */
1855         if (IS_GEN9_LP(dev_priv))
1856                 intel_encoder->pipe_mask = ~0;
1857         else if (port == PORT_A)
1858                 intel_encoder->pipe_mask = BIT(PIPE_A);
1859         else
1860                 intel_encoder->pipe_mask = BIT(PIPE_B);
1861
1862         if (dev_priv->vbt.dsi.config->dual_link)
1863                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1864         else
1865                 intel_dsi->ports = BIT(port);
1866
1867         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1868         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1869
1870         /* Create a DSI host (and a device) for each port. */
1871         for_each_dsi_port(port, intel_dsi->ports) {
1872                 struct intel_dsi_host *host;
1873
1874                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1875                                            port);
1876                 if (!host)
1877                         goto err;
1878
1879                 intel_dsi->dsi_hosts[port] = host;
1880         }
1881
1882         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1883                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1884                 goto err;
1885         }
1886
1887         /* Use clock read-back from current hw-state for fastboot */
1888         current_mode = intel_encoder_current_mode(intel_encoder);
1889         if (current_mode) {
1890                 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1891                             intel_dsi->pclk, current_mode->clock);
1892                 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1893                                             current_mode->clock)) {
1894                         drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1895                         intel_dsi->pclk = current_mode->clock;
1896                 }
1897
1898                 kfree(current_mode);
1899         }
1900
1901         vlv_dphy_param_init(intel_dsi);
1902
1903         intel_dsi_vbt_gpio_init(intel_dsi,
1904                                 intel_dsi_get_hw_state(intel_encoder, &pipe));
1905
1906         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1907                            DRM_MODE_CONNECTOR_DSI);
1908
1909         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1910
1911         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1912         connector->interlace_allowed = false;
1913         connector->doublescan_allowed = false;
1914
1915         intel_connector_attach_encoder(intel_connector, intel_encoder);
1916
1917         mutex_lock(&dev->mode_config.mutex);
1918         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1919         mutex_unlock(&dev->mode_config.mutex);
1920
1921         if (!fixed_mode) {
1922                 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1923                 goto err_cleanup_connector;
1924         }
1925
1926         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1927         intel_panel_setup_backlight(connector, INVALID_PIPE);
1928
1929         vlv_dsi_add_properties(intel_connector);
1930
1931         return;
1932
1933 err_cleanup_connector:
1934         drm_connector_cleanup(&intel_connector->base);
1935 err:
1936         drm_encoder_cleanup(&intel_encoder->base);
1937         kfree(intel_dsi);
1938         kfree(intel_connector);
1939 }