drivers/gpu/drm/i915/display/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_mipi_dsi.h>
  32
  33 #include "i915_drv.h"
  34 #include "intel_atomic.h"
  35 #include "intel_connector.h"
  36 #include "intel_crtc.h"
  37 #include "intel_de.h"
  38 #include "intel_display_types.h"
  39 #include "intel_dsi.h"
  40 #include "intel_fifo_underrun.h"
  41 #include "intel_panel.h"
  42 #include "intel_sideband.h"
  43 #include "skl_scaler.h"
  44
  45 /* return pixels in terms of txbyteclkhs */
  46 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  47                        u16 burst_mode_ratio)
  48 {
  49         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  50                                          8 * 100), lane_count);
  51 }
  52
  53 /* return pixels equvalent to txbyteclkhs */
  54 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  55                         u16 burst_mode_ratio)
  56 {
  57         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  58                                                 (bpp * burst_mode_ratio));
  59 }
  60
  61 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  62 {
  63         /* It just so happens the VBT matches register contents. */
  64         switch (fmt) {
  65         case VID_MODE_FORMAT_RGB888:
  66                 return MIPI_DSI_FMT_RGB888;
  67         case VID_MODE_FORMAT_RGB666:
  68                 return MIPI_DSI_FMT_RGB666;
  69         case VID_MODE_FORMAT_RGB666_PACKED:
  70                 return MIPI_DSI_FMT_RGB666_PACKED;
  71         case VID_MODE_FORMAT_RGB565:
  72                 return MIPI_DSI_FMT_RGB565;
  73         default:
  74                 MISSING_CASE(fmt);
  75                 return MIPI_DSI_FMT_RGB666;
  76         }
  77 }
  78
  79 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  80 {
  81         struct drm_encoder *encoder = &intel_dsi->base.base;
  82         struct drm_device *dev = encoder->dev;
  83         struct drm_i915_private *dev_priv = to_i915(dev);
  84         u32 mask;
  85
  86         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  87                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  88
  89         if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
  90                                   mask, 100))
  91                 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
  92 }
  93
  94 static void write_data(struct drm_i915_private *dev_priv,
  95                        i915_reg_t reg,
  96                        const u8 *data, u32 len)
  97 {
  98         u32 i, j;
  99
 100         for (i = 0; i < len; i += 4) {
 101                 u32 val = 0;
 102
 103                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 104                         val |= *data++ << 8 * j;
 105
 106                 intel_de_write(dev_priv, reg, val);
 107         }
 108 }
 109
 110 static void read_data(struct drm_i915_private *dev_priv,
 111                       i915_reg_t reg,
 112                       u8 *data, u32 len)
 113 {
 114         u32 i, j;
 115
 116         for (i = 0; i < len; i += 4) {
 117                 u32 val = intel_de_read(dev_priv, reg);
 118
 119                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 120                         *data++ = val >> 8 * j;
 121         }
 122 }
 123
 124 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 125                                        const struct mipi_dsi_msg *msg)
 126 {
 127         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 128         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 129         struct drm_i915_private *dev_priv = to_i915(dev);
 130         enum port port = intel_dsi_host->port;
 131         struct mipi_dsi_packet packet;
 132         ssize_t ret;
 133         const u8 *header, *data;
 134         i915_reg_t data_reg, ctrl_reg;
 135         u32 data_mask, ctrl_mask;
 136
 137         ret = mipi_dsi_create_packet(&packet, msg);
 138         if (ret < 0)
 139                 return ret;
 140
 141         header = packet.header;
 142         data = packet.payload;
 143
 144         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 145                 data_reg = MIPI_LP_GEN_DATA(port);
 146                 data_mask = LP_DATA_FIFO_FULL;
 147                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 148                 ctrl_mask = LP_CTRL_FIFO_FULL;
 149         } else {
 150                 data_reg = MIPI_HS_GEN_DATA(port);
 151                 data_mask = HS_DATA_FIFO_FULL;
 152                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 153                 ctrl_mask = HS_CTRL_FIFO_FULL;
 154         }
 155
 156         /* note: this is never true for reads */
 157         if (packet.payload_length) {
 158                 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 159                                             data_mask, 50))
 160                         drm_err(&dev_priv->drm,
 161                                 "Timeout waiting for HS/LP DATA FIFO !full\n");
 162
 163                 write_data(dev_priv, data_reg, packet.payload,
 164                            packet.payload_length);
 165         }
 166
 167         if (msg->rx_len) {
 168                 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
 169                                GEN_READ_DATA_AVAIL);
 170         }
 171
 172         if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 173                                     ctrl_mask, 50)) {
 174                 drm_err(&dev_priv->drm,
 175                         "Timeout waiting for HS/LP CTRL FIFO !full\n");
 176         }
 177
 178         intel_de_write(dev_priv, ctrl_reg,
 179                        header[2] << 16 | header[1] << 8 | header[0]);
 180
 181         /* ->rx_len is set only for reads */
 182         if (msg->rx_len) {
 183                 data_mask = GEN_READ_DATA_AVAIL;
 184                 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
 185                                           data_mask, 50))
 186                         drm_err(&dev_priv->drm,
 187                                 "Timeout waiting for read data.\n");
 188
 189                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 190         }
 191
 192         /* XXX: fix for reads and writes */
 193         return 4 + packet.payload_length;
 194 }
 195
 196 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 197                                  struct mipi_dsi_device *dsi)
 198 {
 199         return 0;
 200 }
 201
 202 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 203                                  struct mipi_dsi_device *dsi)
 204 {
 205         return 0;
 206 }
 207
 208 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 209         .attach = intel_dsi_host_attach,
 210         .detach = intel_dsi_host_detach,
 211         .transfer = intel_dsi_host_transfer,
 212 };
 213
 214 /*
 215  * send a video mode command
 216  *
 217  * XXX: commands with data in MIPI_DPI_DATA?
 218  */
 219 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 220                         enum port port)
 221 {
 222         struct drm_encoder *encoder = &intel_dsi->base.base;
 223         struct drm_device *dev = encoder->dev;
 224         struct drm_i915_private *dev_priv = to_i915(dev);
 225         u32 mask;
 226
 227         /* XXX: pipe, hs */
 228         if (hs)
 229                 cmd &= ~DPI_LP_MODE;
 230         else
 231                 cmd |= DPI_LP_MODE;
 232
 233         /* clear bit */
 234         intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 235
 236         /* XXX: old code skips write if control unchanged */
 237         if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
 238                 drm_dbg_kms(&dev_priv->drm,
 239                             "Same special packet %02x twice in a row.\n", cmd);
 240
 241         intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
 242
 243         mask = SPL_PKT_SENT_INTERRUPT;
 244         if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
 245                 drm_err(&dev_priv->drm,
 246                         "Video mode command 0x%08x send failed.\n", cmd);
 247
 248         return 0;
 249 }
 250
 251 static void band_gap_reset(struct drm_i915_private *dev_priv)
 252 {
 253         vlv_flisdsi_get(dev_priv);
 254
 255         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 256         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 257         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 258         udelay(150);
 259         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 260         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 261
 262         vlv_flisdsi_put(dev_priv);
 263 }
 264
 265 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 266                                     struct intel_crtc_state *pipe_config,
 267                                     struct drm_connector_state *conn_state)
 268 {
 269         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 270         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 271                                                    base);
 272         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 273         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 274         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 275         int ret;
 276
 277         drm_dbg_kms(&dev_priv->drm, "\n");
 278         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 279
 280         if (fixed_mode) {
 281                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 282
 283                 if (HAS_GMCH(dev_priv))
 284                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
 285                 else
 286                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
 287                 if (ret)
 288                         return ret;
 289         }
 290
 291         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 292                 return -EINVAL;
 293
 294         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 295         adjusted_mode->flags = 0;
 296
 297         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 298                 pipe_config->pipe_bpp = 24;
 299         else
 300                 pipe_config->pipe_bpp = 18;
 301
 302         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 303                 /* Enable Frame time stamp based scanline reporting */
 304                 pipe_config->mode_flags |=
 305                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 306
 307                 /* Dual link goes to DSI transcoder A. */
 308                 if (intel_dsi->ports == BIT(PORT_C))
 309                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 310                 else
 311                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 312
 313                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 314                 if (ret)
 315                         return -EINVAL;
 316         } else {
 317                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 318                 if (ret)
 319                         return -EINVAL;
 320         }
 321
 322         pipe_config->clock_set = true;
 323
 324         return 0;
 325 }
 326
 327 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 328 {
 329         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 330         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 331         enum port port;
 332         u32 tmp;
 333         bool cold_boot = false;
 334
 335         /* Set the MIPI mode
 336          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 337          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 338          */
 339         for_each_dsi_port(port, intel_dsi->ports) {
 340                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 341                 intel_de_write(dev_priv, MIPI_CTRL(port),
 342                                tmp | GLK_MIPIIO_ENABLE);
 343         }
 344
 345         /* Put the IO into reset */
 346         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 347         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 348         intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
 349
 350         /* Program LP Wake */
 351         for_each_dsi_port(port, intel_dsi->ports) {
 352                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 353                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
 354                         tmp &= ~GLK_LP_WAKE;
 355                 else
 356                         tmp |= GLK_LP_WAKE;
 357                 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
 358         }
 359
 360         /* Wait for Pwr ACK */
 361         for_each_dsi_port(port, intel_dsi->ports) {
 362                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 363                                           GLK_MIPIIO_PORT_POWERED, 20))
 364                         drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
 365         }
 366
 367         /* Check for cold boot scenario */
 368         for_each_dsi_port(port, intel_dsi->ports) {
 369                 cold_boot |=
 370                         !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
 371         }
 372
 373         return cold_boot;
 374 }
 375
 376 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 377 {
 378         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 379         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 380         enum port port;
 381         u32 val;
 382
 383         /* Wait for MIPI PHY status bit to set */
 384         for_each_dsi_port(port, intel_dsi->ports) {
 385                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 386                                           GLK_PHY_STATUS_PORT_READY, 20))
 387                         drm_err(&dev_priv->drm, "PHY is not ON\n");
 388         }
 389
 390         /* Get IO out of reset */
 391         val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 392         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
 393                        val | GLK_MIPIIO_RESET_RELEASED);
 394
 395         /* Get IO out of Low power state*/
 396         for_each_dsi_port(port, intel_dsi->ports) {
 397                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 398                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 399                         val &= ~ULPS_STATE_MASK;
 400                         val |= DEVICE_READY;
 401                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 402                         usleep_range(10, 15);
 403                 } else {
 404                         /* Enter ULPS */
 405                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 406                         val &= ~ULPS_STATE_MASK;
 407                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 408                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 409
 410                         /* Wait for ULPS active */
 411                         if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 412                                                     GLK_ULPS_NOT_ACTIVE, 20))
 413                                 drm_err(&dev_priv->drm, "ULPS not active\n");
 414
 415                         /* Exit ULPS */
 416                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 417                         val &= ~ULPS_STATE_MASK;
 418                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 419                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 420
 421                         /* Enter Normal Mode */
 422                         val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 423                         val &= ~ULPS_STATE_MASK;
 424                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 425                         intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 426
 427                         val = intel_de_read(dev_priv, MIPI_CTRL(port));
 428                         val &= ~GLK_LP_WAKE;
 429                         intel_de_write(dev_priv, MIPI_CTRL(port), val);
 430                 }
 431         }
 432
 433         /* Wait for Stop state */
 434         for_each_dsi_port(port, intel_dsi->ports) {
 435                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 436                                           GLK_DATA_LANE_STOP_STATE, 20))
 437                         drm_err(&dev_priv->drm,
 438                                 "Date lane not in STOP state\n");
 439         }
 440
 441         /* Wait for AFE LATCH */
 442         for_each_dsi_port(port, intel_dsi->ports) {
 443                 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
 444                                           AFE_LATCHOUT, 20))
 445                         drm_err(&dev_priv->drm,
 446                                 "D-PHY not entering LP-11 state\n");
 447         }
 448 }
 449
 450 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 451 {
 452         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 453         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 454         enum port port;
 455         u32 val;
 456
 457         drm_dbg_kms(&dev_priv->drm, "\n");
 458
 459         /* Enable MIPI PHY transparent latch */
 460         for_each_dsi_port(port, intel_dsi->ports) {
 461                 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
 462                 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port),
 463                                val | LP_OUTPUT_HOLD);
 464                 usleep_range(2000, 2500);
 465         }
 466
 467         /* Clear ULPS and set device ready */
 468         for_each_dsi_port(port, intel_dsi->ports) {
 469                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 470                 val &= ~ULPS_STATE_MASK;
 471                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 472                 usleep_range(2000, 2500);
 473                 val |= DEVICE_READY;
 474                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 475         }
 476 }
 477
 478 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 479 {
 480         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 481         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 482         enum port port;
 483         u32 val;
 484
 485         drm_dbg_kms(&dev_priv->drm, "\n");
 486
 487         vlv_flisdsi_get(dev_priv);
 488         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 489          * needed everytime after power gate */
 490         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 491         vlv_flisdsi_put(dev_priv);
 492
 493         /* bandgap reset is needed after everytime we do power gate */
 494         band_gap_reset(dev_priv);
 495
 496         for_each_dsi_port(port, intel_dsi->ports) {
 497
 498                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 499                                ULPS_STATE_ENTER);
 500                 usleep_range(2500, 3000);
 501
 502                 /* Enable MIPI PHY transparent latch
 503                  * Common bit for both MIPI Port A & MIPI Port C
 504                  * No similar bit in MIPI Port C reg
 505                  */
 506                 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A));
 507                 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A),
 508                                val | LP_OUTPUT_HOLD);
 509                 usleep_range(1000, 1500);
 510
 511                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 512                                ULPS_STATE_EXIT);
 513                 usleep_range(2500, 3000);
 514
 515                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 516                                DEVICE_READY);
 517                 usleep_range(2500, 3000);
 518         }
 519 }
 520
 521 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 522 {
 523         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 524
 525         if (IS_GEMINILAKE(dev_priv))
 526                 glk_dsi_device_ready(encoder);
 527         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 528                 bxt_dsi_device_ready(encoder);
 529         else
 530                 vlv_dsi_device_ready(encoder);
 531 }
 532
 533 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 534 {
 535         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 536         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 537         enum port port;
 538         u32 val;
 539
 540         /* Enter ULPS */
 541         for_each_dsi_port(port, intel_dsi->ports) {
 542                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 543                 val &= ~ULPS_STATE_MASK;
 544                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 545                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 546         }
 547
 548         /* Wait for MIPI PHY status bit to unset */
 549         for_each_dsi_port(port, intel_dsi->ports) {
 550                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 551                                             GLK_PHY_STATUS_PORT_READY, 20))
 552                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 553         }
 554
 555         /* Wait for Pwr ACK bit to unset */
 556         for_each_dsi_port(port, intel_dsi->ports) {
 557                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 558                                             GLK_MIPIIO_PORT_POWERED, 20))
 559                         drm_err(&dev_priv->drm,
 560                                 "MIPI IO Port is not powergated\n");
 561         }
 562 }
 563
 564 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 565 {
 566         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 567         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 568         enum port port;
 569         u32 tmp;
 570
 571         /* Put the IO into reset */
 572         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
 573         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 574         intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
 575
 576         /* Wait for MIPI PHY status bit to unset */
 577         for_each_dsi_port(port, intel_dsi->ports) {
 578                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 579                                             GLK_PHY_STATUS_PORT_READY, 20))
 580                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 581         }
 582
 583         /* Clear MIPI mode */
 584         for_each_dsi_port(port, intel_dsi->ports) {
 585                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 586                 tmp &= ~GLK_MIPIIO_ENABLE;
 587                 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
 588         }
 589 }
 590
 591 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 592 {
 593         glk_dsi_enter_low_power_mode(encoder);
 594         glk_dsi_disable_mipi_io(encoder);
 595 }
 596
 597 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 598 {
 599         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 600         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 601         enum port port;
 602
 603         drm_dbg_kms(&dev_priv->drm, "\n");
 604         for_each_dsi_port(port, intel_dsi->ports) {
 605                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 606                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 607                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 608                 u32 val;
 609
 610                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 611                                DEVICE_READY | ULPS_STATE_ENTER);
 612                 usleep_range(2000, 2500);
 613
 614                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 615                                DEVICE_READY | ULPS_STATE_EXIT);
 616                 usleep_range(2000, 2500);
 617
 618                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 619                                DEVICE_READY | ULPS_STATE_ENTER);
 620                 usleep_range(2000, 2500);
 621
 622                 /*
 623                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 624                  * Port A only. MIPI Port C has no similar bit for checking.
 625                  */
 626                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
 627                     intel_de_wait_for_clear(dev_priv, port_ctrl,
 628                                             AFE_LATCHOUT, 30))
 629                         drm_err(&dev_priv->drm, "DSI LP not going Low\n");
 630
 631                 /* Disable MIPI PHY transparent latch */
 632                 val = intel_de_read(dev_priv, port_ctrl);
 633                 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD);
 634                 usleep_range(1000, 1500);
 635
 636                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
 637                 usleep_range(2000, 2500);
 638         }
 639 }
 640
 641 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 642                                   const struct intel_crtc_state *crtc_state)
 643 {
 644         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 645         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 646         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 647         enum port port;
 648
 649         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 650                 u32 temp;
 651                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 652                         for_each_dsi_port(port, intel_dsi->ports) {
 653                                 temp = intel_de_read(dev_priv,
 654                                                      MIPI_CTRL(port));
 655                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 656                                         intel_dsi->pixel_overlap <<
 657                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 658                                 intel_de_write(dev_priv, MIPI_CTRL(port),
 659                                                temp);
 660                         }
 661                 } else {
 662                         temp = intel_de_read(dev_priv, VLV_CHICKEN_3);
 663                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 664                                         intel_dsi->pixel_overlap <<
 665                                         PIXEL_OVERLAP_CNT_SHIFT;
 666                         intel_de_write(dev_priv, VLV_CHICKEN_3, temp);
 667                 }
 668         }
 669
 670         for_each_dsi_port(port, intel_dsi->ports) {
 671                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 672                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 673                 u32 temp;
 674
 675                 temp = intel_de_read(dev_priv, port_ctrl);
 676
 677                 temp &= ~LANE_CONFIGURATION_MASK;
 678                 temp &= ~DUAL_LINK_MODE_MASK;
 679
 680                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 681                         temp |= (intel_dsi->dual_link - 1)
 682                                                 << DUAL_LINK_MODE_SHIFT;
 683                         if (IS_BROXTON(dev_priv))
 684                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 685                         else
 686                                 temp |= crtc->pipe ?
 687                                         LANE_CONFIGURATION_DUAL_LINK_B :
 688                                         LANE_CONFIGURATION_DUAL_LINK_A;
 689                 }
 690
 691                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 692                         temp |= DITHERING_ENABLE;
 693
 694                 /* assert ip_tg_enable signal */
 695                 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
 696                 intel_de_posting_read(dev_priv, port_ctrl);
 697         }
 698 }
 699
 700 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 701 {
 702         struct drm_device *dev = encoder->base.dev;
 703         struct drm_i915_private *dev_priv = to_i915(dev);
 704         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 705         enum port port;
 706
 707         for_each_dsi_port(port, intel_dsi->ports) {
 708                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 709                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 710                 u32 temp;
 711
 712                 /* de-assert ip_tg_enable signal */
 713                 temp = intel_de_read(dev_priv, port_ctrl);
 714                 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE);
 715                 intel_de_posting_read(dev_priv, port_ctrl);
 716         }
 717 }
 718
 719 static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
 720 {
 721         ktime_t panel_power_on_time;
 722         s64 panel_power_off_duration;
 723
 724         panel_power_on_time = ktime_get_boottime();
 725         panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
 726                                                   intel_dsi->panel_power_off_time);
 727
 728         if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
 729                 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration);
 730 }
 731
 732 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 733                               const struct intel_crtc_state *pipe_config);
 734 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 735
 736 /*
 737  * Panel enable/disable sequences from the VBT spec.
 738  *
 739  * Note the spec has AssertReset / DeassertReset swapped from their
 740  * usual naming. We use the normal names to avoid confusion (so below
 741  * they are swapped compared to the spec).
 742  *
 743  * Steps starting with MIPI refer to VBT sequences, note that for v2
 744  * VBTs several steps which have a VBT in v2 are expected to be handled
 745  * directly by the driver, by directly driving gpios for example.
 746  *
 747  * v2 video mode seq         v3 video mode seq         command mode seq
 748  * - power on                - MIPIPanelPowerOn        - power on
 749  * - wait t1+t2                                        - wait t1+t2
 750  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 751  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 752  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 753  *                                                     - MIPITearOn
 754  *                                                     - MIPIDisplayOn
 755  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 756  * - MIPIDisplayOn           - MIPIDisplayOn
 757  * - wait t5                                           - wait t5
 758  * - backlight on            - MIPIBacklightOn         - backlight on
 759  * ...                       ...                       ... issue mem cmds ...
 760  * - backlight off           - MIPIBacklightOff        - backlight off
 761  * - wait t6                                           - wait t6
 762  * - MIPIDisplayOff
 763  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 764  *                                                     - MIPITearOff
 765  *                           - MIPIDisplayOff          - MIPIDisplayOff
 766  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 767  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 768  * - wait t3                                           - wait t3
 769  * - power off               - MIPIPanelPowerOff       - power off
 770  * - wait t4                                           - wait t4
 771  */
 772
 773 /*
 774  * DSI port enable has to be done before pipe and plane enable, so we do it in
 775  * the pre_enable hook instead of the enable hook.
 776  */
 777 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 778                                  struct intel_encoder *encoder,
 779                                  const struct intel_crtc_state *pipe_config,
 780                                  const struct drm_connector_state *conn_state)
 781 {
 782         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 783         struct drm_crtc *crtc = pipe_config->uapi.crtc;
 784         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 786         enum pipe pipe = intel_crtc->pipe;
 787         enum port port;
 788         u32 val;
 789         bool glk_cold_boot = false;
 790
 791         drm_dbg_kms(&dev_priv->drm, "\n");
 792
 793         intel_dsi_wait_panel_power_cycle(intel_dsi);
 794
 795         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 796
 797         /*
 798          * The BIOS may leave the PLL in a wonky state where it doesn't
 799          * lock. It needs to be fully powered down to fix it.
 800          */
 801         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 802                 bxt_dsi_pll_disable(encoder);
 803                 bxt_dsi_pll_enable(encoder, pipe_config);
 804         } else {
 805                 vlv_dsi_pll_disable(encoder);
 806                 vlv_dsi_pll_enable(encoder, pipe_config);
 807         }
 808
 809         if (IS_BROXTON(dev_priv)) {
 810                 /* Add MIPI IO reset programming for modeset */
 811                 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
 812                 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
 813                                val | MIPIO_RST_CTRL);
 814
 815                 /* Power up DSI regulator */
 816                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 817                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 818         }
 819
 820         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 821                 u32 val;
 822
 823                 /* Disable DPOunit clock gating, can stall pipe */
 824                 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
 825                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 826                 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 827         }
 828
 829         if (!IS_GEMINILAKE(dev_priv))
 830                 intel_dsi_prepare(encoder, pipe_config);
 831
 832         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 833
 834         /*
 835          * Give the panel time to power-on and then deassert its reset.
 836          * Depending on the VBT MIPI sequences version the deassert-seq
 837          * may contain the necessary delay, intel_dsi_msleep() will skip
 838          * the delay in that case. If there is no deassert-seq, then an
 839          * unconditional msleep is used to give the panel time to power-on.
 840          */
 841         if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
 842                 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 843                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 844         } else {
 845                 msleep(intel_dsi->panel_on_delay);
 846         }
 847
 848         if (IS_GEMINILAKE(dev_priv)) {
 849                 glk_cold_boot = glk_dsi_enable_io(encoder);
 850
 851                 /* Prepare port in cold boot(s3/s4) scenario */
 852                 if (glk_cold_boot)
 853                         intel_dsi_prepare(encoder, pipe_config);
 854         }
 855
 856         /* Put device in ready state (LP-11) */
 857         intel_dsi_device_ready(encoder);
 858
 859         /* Prepare port in normal boot scenario */
 860         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 861                 intel_dsi_prepare(encoder, pipe_config);
 862
 863         /* Send initialization commands in LP mode */
 864         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 865
 866         /*
 867          * Enable port in pre-enable phase itself because as per hw team
 868          * recommendation, port should be enabled before plane & pipe
 869          */
 870         if (is_cmd_mode(intel_dsi)) {
 871                 for_each_dsi_port(port, intel_dsi->ports)
 872                         intel_de_write(dev_priv,
 873                                        MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 874                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 875                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 876         } else {
 877                 msleep(20); /* XXX */
 878                 for_each_dsi_port(port, intel_dsi->ports)
 879                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 880                 intel_dsi_msleep(intel_dsi, 100);
 881
 882                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 883
 884                 intel_dsi_port_enable(encoder, pipe_config);
 885         }
 886
 887         intel_panel_enable_backlight(pipe_config, conn_state);
 888         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 889 }
 890
 891 static void bxt_dsi_enable(struct intel_atomic_state *state,
 892                            struct intel_encoder *encoder,
 893                            const struct intel_crtc_state *crtc_state,
 894                            const struct drm_connector_state *conn_state)
 895 {
 896         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
 897
 898         intel_crtc_vblank_on(crtc_state);
 899 }
 900
 901 /*
 902  * DSI port disable has to be done after pipe and plane disable, so we do it in
 903  * the post_disable hook.
 904  */
 905 static void intel_dsi_disable(struct intel_atomic_state *state,
 906                               struct intel_encoder *encoder,
 907                               const struct intel_crtc_state *old_crtc_state,
 908                               const struct drm_connector_state *old_conn_state)
 909 {
 910         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 911         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 912         enum port port;
 913
 914         drm_dbg_kms(&i915->drm, "\n");
 915
 916         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 917         intel_panel_disable_backlight(old_conn_state);
 918
 919         /*
 920          * According to the spec we should send SHUTDOWN before
 921          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 922          * has shown that the v3 sequence works for v2 VBTs too
 923          */
 924         if (is_vid_mode(intel_dsi)) {
 925                 /* Send Shutdown command to the panel in LP mode */
 926                 for_each_dsi_port(port, intel_dsi->ports)
 927                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 928                 msleep(10);
 929         }
 930 }
 931
 932 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 933 {
 934         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 935
 936         if (IS_GEMINILAKE(dev_priv))
 937                 glk_dsi_clear_device_ready(encoder);
 938         else
 939                 vlv_dsi_clear_device_ready(encoder);
 940 }
 941
 942 static void intel_dsi_post_disable(struct intel_atomic_state *state,
 943                                    struct intel_encoder *encoder,
 944                                    const struct intel_crtc_state *old_crtc_state,
 945                                    const struct drm_connector_state *old_conn_state)
 946 {
 947         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 948         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 949         enum port port;
 950         u32 val;
 951
 952         drm_dbg_kms(&dev_priv->drm, "\n");
 953
 954         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 955                 intel_crtc_vblank_off(old_crtc_state);
 956
 957                 skl_scaler_disable(old_crtc_state);
 958         }
 959
 960         if (is_vid_mode(intel_dsi)) {
 961                 for_each_dsi_port(port, intel_dsi->ports)
 962                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 963
 964                 intel_dsi_port_disable(encoder);
 965                 usleep_range(2000, 5000);
 966         }
 967
 968         intel_dsi_unprepare(encoder);
 969
 970         /*
 971          * if disable packets are sent before sending shutdown packet then in
 972          * some next enable sequence send turn on packet error is observed
 973          */
 974         if (is_cmd_mode(intel_dsi))
 975                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 976         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 977
 978         /* Transition to LP-00 */
 979         intel_dsi_clear_device_ready(encoder);
 980
 981         if (IS_BROXTON(dev_priv)) {
 982                 /* Power down DSI regulator to save power */
 983                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 984                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
 985                                HS_IO_CTRL_SELECT);
 986
 987                 /* Add MIPI IO reset programming for modeset */
 988                 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
 989                 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
 990                                val & ~MIPIO_RST_CTRL);
 991         }
 992
 993         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 994                 bxt_dsi_pll_disable(encoder);
 995         } else {
 996                 u32 val;
 997
 998                 vlv_dsi_pll_disable(encoder);
 999
1000                 val = intel_de_read(dev_priv, DSPCLK_GATE_D);
1001                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
1002                 intel_de_write(dev_priv, DSPCLK_GATE_D, val);
1003         }
1004
1005         /* Assert reset */
1006         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1007
1008         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
1009         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1010
1011         intel_dsi->panel_power_off_time = ktime_get_boottime();
1012 }
1013
1014 static void intel_dsi_shutdown(struct intel_encoder *encoder)
1015 {
1016         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1017
1018         intel_dsi_wait_panel_power_cycle(intel_dsi);
1019 }
1020
1021 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1022                                    enum pipe *pipe)
1023 {
1024         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1025         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1026         intel_wakeref_t wakeref;
1027         enum port port;
1028         bool active = false;
1029
1030         drm_dbg_kms(&dev_priv->drm, "\n");
1031
1032         wakeref = intel_display_power_get_if_enabled(dev_priv,
1033                                                      encoder->power_domain);
1034         if (!wakeref)
1035                 return false;
1036
1037         /*
1038          * On Broxton the PLL needs to be enabled with a valid divider
1039          * configuration, otherwise accessing DSI registers will hang the
1040          * machine. See BSpec North Display Engine registers/MIPI[BXT].
1041          */
1042         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1043             !bxt_dsi_pll_is_enabled(dev_priv))
1044                 goto out_put_power;
1045
1046         /* XXX: this only works for one DSI output */
1047         for_each_dsi_port(port, intel_dsi->ports) {
1048                 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
1049                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1050                 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
1051
1052                 /*
1053                  * Due to some hardware limitations on VLV/CHV, the DPI enable
1054                  * bit in port C control register does not get set. As a
1055                  * workaround, check pipe B conf instead.
1056                  */
1057                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1058                     port == PORT_C)
1059                         enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1060
1061                 /* Try command mode if video mode not enabled */
1062                 if (!enabled) {
1063                         u32 tmp = intel_de_read(dev_priv,
1064                                                 MIPI_DSI_FUNC_PRG(port));
1065                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1066                 }
1067
1068                 if (!enabled)
1069                         continue;
1070
1071                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
1072                         continue;
1073
1074                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1075                         u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1076                         tmp &= BXT_PIPE_SELECT_MASK;
1077                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1078
1079                         if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
1080                                 continue;
1081
1082                         *pipe = tmp;
1083                 } else {
1084                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1085                 }
1086
1087                 active = true;
1088                 break;
1089         }
1090
1091 out_put_power:
1092         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1093
1094         return active;
1095 }
1096
1097 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1098                                     struct intel_crtc_state *pipe_config)
1099 {
1100         struct drm_device *dev = encoder->base.dev;
1101         struct drm_i915_private *dev_priv = to_i915(dev);
1102         struct drm_display_mode *adjusted_mode =
1103                                         &pipe_config->hw.adjusted_mode;
1104         struct drm_display_mode *adjusted_mode_sw;
1105         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1106         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1107         unsigned int lane_count = intel_dsi->lane_count;
1108         unsigned int bpp, fmt;
1109         enum port port;
1110         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1111         u16 hfp_sw, hsync_sw, hbp_sw;
1112         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1113                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1114
1115         /* FIXME: hw readout should not depend on SW state */
1116         adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1117
1118         /*
1119          * Atleast one port is active as encoder->get_config called only if
1120          * encoder->get_hw_state() returns true.
1121          */
1122         for_each_dsi_port(port, intel_dsi->ports) {
1123                 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1124                         break;
1125         }
1126
1127         fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1128         bpp = mipi_dsi_pixel_format_to_bpp(
1129                         pixel_format_from_register_bits(fmt));
1130
1131         pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1132
1133         /* Enable Frame time stamo based scanline reporting */
1134         pipe_config->mode_flags |=
1135                 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1136
1137         /* In terms of pixels */
1138         adjusted_mode->crtc_hdisplay =
1139                                 intel_de_read(dev_priv,
1140                                               BXT_MIPI_TRANS_HACTIVE(port));
1141         adjusted_mode->crtc_vdisplay =
1142                                 intel_de_read(dev_priv,
1143                                               BXT_MIPI_TRANS_VACTIVE(port));
1144         adjusted_mode->crtc_vtotal =
1145                                 intel_de_read(dev_priv,
1146                                               BXT_MIPI_TRANS_VTOTAL(port));
1147
1148         hactive = adjusted_mode->crtc_hdisplay;
1149         hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1150
1151         /*
1152          * Meaningful for video mode non-burst sync pulse mode only,
1153          * can be zero for non-burst sync events and burst modes
1154          */
1155         hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1156         hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1157
1158         /* harizontal values are in terms of high speed byte clock */
1159         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1160                                                 intel_dsi->burst_mode_ratio);
1161         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1162                                                 intel_dsi->burst_mode_ratio);
1163         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1164                                                 intel_dsi->burst_mode_ratio);
1165
1166         if (intel_dsi->dual_link) {
1167                 hfp *= 2;
1168                 hsync *= 2;
1169                 hbp *= 2;
1170         }
1171
1172         /* vertical values are in terms of lines */
1173         vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1174         vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1175         vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port));
1176
1177         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1178         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1179         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1180         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1181         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1182
1183         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1184         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1185         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1186         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1187
1188         /*
1189          * In BXT DSI there is no regs programmed with few horizontal timings
1190          * in Pixels but txbyteclkhs.. So retrieval process adds some
1191          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1192          * Actually here for the given adjusted_mode, we are calculating the
1193          * value programmed to the port and then back to the horizontal timing
1194          * param in pixels. This is the expected value, including roundup errors
1195          * And if that is same as retrieved value from port, then
1196          * (HW state) adjusted_mode's horizontal timings are corrected to
1197          * match with SW state to nullify the errors.
1198          */
1199         /* Calculating the value programmed to the Port register */
1200         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1201                                         adjusted_mode_sw->crtc_hdisplay;
1202         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1203                                         adjusted_mode_sw->crtc_hsync_start;
1204         hbp_sw = adjusted_mode_sw->crtc_htotal -
1205                                         adjusted_mode_sw->crtc_hsync_end;
1206
1207         if (intel_dsi->dual_link) {
1208                 hfp_sw /= 2;
1209                 hsync_sw /= 2;
1210                 hbp_sw /= 2;
1211         }
1212
1213         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1214                                                 intel_dsi->burst_mode_ratio);
1215         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1216                             intel_dsi->burst_mode_ratio);
1217         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1218                                                 intel_dsi->burst_mode_ratio);
1219
1220         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1221         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1222                                                 intel_dsi->burst_mode_ratio);
1223         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1224                                                 intel_dsi->burst_mode_ratio);
1225         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1226                                                 intel_dsi->burst_mode_ratio);
1227
1228         if (intel_dsi->dual_link) {
1229                 hfp_sw *= 2;
1230                 hsync_sw *= 2;
1231                 hbp_sw *= 2;
1232         }
1233
1234         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1235                                                         hsync_sw + hbp_sw;
1236         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1237         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1238         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1239         crtc_hblank_end_sw = crtc_htotal_sw;
1240
1241         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1242                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1243
1244         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1245                 adjusted_mode->crtc_hsync_start =
1246                                         adjusted_mode_sw->crtc_hsync_start;
1247
1248         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1249                 adjusted_mode->crtc_hsync_end =
1250                                         adjusted_mode_sw->crtc_hsync_end;
1251
1252         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1253                 adjusted_mode->crtc_hblank_start =
1254                                         adjusted_mode_sw->crtc_hblank_start;
1255
1256         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1257                 adjusted_mode->crtc_hblank_end =
1258                                         adjusted_mode_sw->crtc_hblank_end;
1259 }
1260
1261 static void intel_dsi_get_config(struct intel_encoder *encoder,
1262                                  struct intel_crtc_state *pipe_config)
1263 {
1264         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1265         u32 pclk;
1266         drm_dbg_kms(&dev_priv->drm, "\n");
1267
1268         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1269
1270         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1271                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1272                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1273         } else {
1274                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1275         }
1276
1277         if (pclk) {
1278                 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1279                 pipe_config->port_clock = pclk;
1280         }
1281 }
1282
1283 /* return txclkesc cycles in terms of divider and duration in us */
1284 static u16 txclkesc(u32 divider, unsigned int us)
1285 {
1286         switch (divider) {
1287         case ESCAPE_CLOCK_DIVIDER_1:
1288         default:
1289                 return 20 * us;
1290         case ESCAPE_CLOCK_DIVIDER_2:
1291                 return 10 * us;
1292         case ESCAPE_CLOCK_DIVIDER_4:
1293                 return 5 * us;
1294         }
1295 }
1296
1297 static void set_dsi_timings(struct drm_encoder *encoder,
1298                             const struct drm_display_mode *adjusted_mode)
1299 {
1300         struct drm_device *dev = encoder->dev;
1301         struct drm_i915_private *dev_priv = to_i915(dev);
1302         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1303         enum port port;
1304         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1305         unsigned int lane_count = intel_dsi->lane_count;
1306
1307         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1308
1309         hactive = adjusted_mode->crtc_hdisplay;
1310         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1311         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1312         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1313
1314         if (intel_dsi->dual_link) {
1315                 hactive /= 2;
1316                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1317                         hactive += intel_dsi->pixel_overlap;
1318                 hfp /= 2;
1319                 hsync /= 2;
1320                 hbp /= 2;
1321         }
1322
1323         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1324         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1325         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1326
1327         /* horizontal values are in terms of high speed byte clock */
1328         hactive = txbyteclkhs(hactive, bpp, lane_count,
1329                               intel_dsi->burst_mode_ratio);
1330         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1331         hsync = txbyteclkhs(hsync, bpp, lane_count,
1332                             intel_dsi->burst_mode_ratio);
1333         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1334
1335         for_each_dsi_port(port, intel_dsi->ports) {
1336                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1337                         /*
1338                          * Program hdisplay and vdisplay on MIPI transcoder.
1339                          * This is different from calculated hactive and
1340                          * vactive, as they are calculated per channel basis,
1341                          * whereas these values should be based on resolution.
1342                          */
1343                         intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1344                                        adjusted_mode->crtc_hdisplay);
1345                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1346                                        adjusted_mode->crtc_vdisplay);
1347                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1348                                        adjusted_mode->crtc_vtotal);
1349                 }
1350
1351                 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1352                                hactive);
1353                 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1354
1355                 /* meaningful for video mode non-burst sync pulse mode only,
1356                  * can be zero for non-burst sync events and burst modes */
1357                 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1358                                hsync);
1359                 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1360
1361                 /* vertical values are in terms of lines */
1362                 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1363                 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1364                                vsync);
1365                 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1366         }
1367 }
1368
1369 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1370 {
1371         switch (fmt) {
1372         case MIPI_DSI_FMT_RGB888:
1373                 return VID_MODE_FORMAT_RGB888;
1374         case MIPI_DSI_FMT_RGB666:
1375                 return VID_MODE_FORMAT_RGB666;
1376         case MIPI_DSI_FMT_RGB666_PACKED:
1377                 return VID_MODE_FORMAT_RGB666_PACKED;
1378         case MIPI_DSI_FMT_RGB565:
1379                 return VID_MODE_FORMAT_RGB565;
1380         default:
1381                 MISSING_CASE(fmt);
1382                 return VID_MODE_FORMAT_RGB666;
1383         }
1384 }
1385
1386 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1387                               const struct intel_crtc_state *pipe_config)
1388 {
1389         struct drm_encoder *encoder = &intel_encoder->base;
1390         struct drm_device *dev = encoder->dev;
1391         struct drm_i915_private *dev_priv = to_i915(dev);
1392         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
1393         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1394         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1395         enum port port;
1396         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1397         u32 val, tmp;
1398         u16 mode_hdisplay;
1399
1400         drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe));
1401
1402         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1403
1404         if (intel_dsi->dual_link) {
1405                 mode_hdisplay /= 2;
1406                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1407                         mode_hdisplay += intel_dsi->pixel_overlap;
1408         }
1409
1410         for_each_dsi_port(port, intel_dsi->ports) {
1411                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1412                         /*
1413                          * escape clock divider, 20MHz, shared for A and C.
1414                          * device ready must be off when doing this! txclkesc?
1415                          */
1416                         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1417                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1418                         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1419                                        tmp | ESCAPE_CLOCK_DIVIDER_1);
1420
1421                         /* read request priority is per pipe */
1422                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1423                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1424                         intel_de_write(dev_priv, MIPI_CTRL(port),
1425                                        tmp | READ_REQUEST_PRIORITY_HIGH);
1426                 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1427                         enum pipe pipe = intel_crtc->pipe;
1428
1429                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1430                         tmp &= ~BXT_PIPE_SELECT_MASK;
1431
1432                         tmp |= BXT_PIPE_SELECT(pipe);
1433                         intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
1434                 }
1435
1436                 /* XXX: why here, why like this? handling in irq handler?! */
1437                 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1438                 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1439
1440                 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1441                                intel_dsi->dphy_reg);
1442
1443                 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1444                                adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1445         }
1446
1447         set_dsi_timings(encoder, adjusted_mode);
1448
1449         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1450         if (is_cmd_mode(intel_dsi)) {
1451                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1452                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1453         } else {
1454                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1455                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1456         }
1457
1458         tmp = 0;
1459         if (intel_dsi->eotp_pkt == 0)
1460                 tmp |= EOT_DISABLE;
1461         if (intel_dsi->clock_stop)
1462                 tmp |= CLOCKSTOP;
1463
1464         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1465                 tmp |= BXT_DPHY_DEFEATURE_EN;
1466                 if (!is_cmd_mode(intel_dsi))
1467                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1468         }
1469
1470         for_each_dsi_port(port, intel_dsi->ports) {
1471                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1472
1473                 /* timeouts for recovery. one frame IIUC. if counter expires,
1474                  * EOT and stop state. */
1475
1476                 /*
1477                  * In burst mode, value greater than one DPI line Time in byte
1478                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1479                  * said value is recommended.
1480                  *
1481                  * In non-burst mode, Value greater than one DPI frame time in
1482                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1483                  * said value is recommended.
1484                  *
1485                  * In DBI only mode, value greater than one DBI frame time in
1486                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1487                  * said value is recommended.
1488                  */
1489
1490                 if (is_vid_mode(intel_dsi) &&
1491                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1492                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1493                                        txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1494                 } else {
1495                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1496                                        txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1497                 }
1498                 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1499                                intel_dsi->lp_rx_timeout);
1500                 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1501                                intel_dsi->turn_arnd_val);
1502                 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1503                                intel_dsi->rst_timer_val);
1504
1505                 /* dphy stuff */
1506
1507                 /* in terms of low power clock */
1508                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1509                                txclkesc(intel_dsi->escape_clk_div, 100));
1510
1511                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1512                     !intel_dsi->dual_link) {
1513                         /*
1514                          * BXT spec says write MIPI_INIT_COUNT for
1515                          * both the ports, even if only one is
1516                          * getting used. So write the other port
1517                          * if not in dual link mode.
1518                          */
1519                         intel_de_write(dev_priv,
1520                                        MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1521                                        intel_dsi->init_count);
1522                 }
1523
1524                 /* recovery disables */
1525                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1526
1527                 /* in terms of low power clock */
1528                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1529                                intel_dsi->init_count);
1530
1531                 /* in terms of txbyteclkhs. actual high to low switch +
1532                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1533                  *
1534                  * XXX: write MIPI_STOP_STATE_STALL?
1535                  */
1536                 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1537                                intel_dsi->hs_to_lp_count);
1538
1539                 /* XXX: low power clock equivalence in terms of byte clock.
1540                  * the number of byte clocks occupied in one low power clock.
1541                  * based on txbyteclkhs and txclkesc.
1542                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1543                  * ) / 105.???
1544                  */
1545                 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1546                                intel_dsi->lp_byte_clk);
1547
1548                 if (IS_GEMINILAKE(dev_priv)) {
1549                         intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1550                                        intel_dsi->lp_byte_clk);
1551                         /* Shadow of DPHY reg */
1552                         intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1553                                        intel_dsi->dphy_reg);
1554                 }
1555
1556                 /* the bw essential for transmitting 16 long packets containing
1557                  * 252 bytes meant for dcs write memory command is programmed in
1558                  * this register in terms of byte clocks. based on dsi transfer
1559                  * rate and the number of lanes configured the time taken to
1560                  * transmit 16 long packets in a dsi stream varies. */
1561                 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1562                                intel_dsi->bw_timer);
1563
1564                 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1565                                intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1566
1567                 if (is_vid_mode(intel_dsi))
1568                         /* Some panels might have resolution which is not a
1569                          * multiple of 64 like 1366 x 768. Enable RANDOM
1570                          * resolution support for such panels by default */
1571                         intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port),
1572                                        intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION);
1573         }
1574 }
1575
1576 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1577 {
1578         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1579         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1580         enum port port;
1581         u32 val;
1582
1583         if (IS_GEMINILAKE(dev_priv))
1584                 return;
1585
1586         for_each_dsi_port(port, intel_dsi->ports) {
1587                 /* Panel commands can be sent when clock is in LP11 */
1588                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1589
1590                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1591                         bxt_dsi_reset_clocks(encoder, port);
1592                 else
1593                         vlv_dsi_reset_clocks(encoder, port);
1594                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1595
1596                 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port));
1597                 val &= ~VID_MODE_FORMAT_MASK;
1598                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1599
1600                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1601         }
1602 }
1603
1604 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1605 {
1606         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1607
1608         intel_dsi_vbt_gpio_cleanup(intel_dsi);
1609         intel_encoder_destroy(encoder);
1610 }
1611
1612 static const struct drm_encoder_funcs intel_dsi_funcs = {
1613         .destroy = intel_dsi_encoder_destroy,
1614 };
1615
1616 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1617         .get_modes = intel_dsi_get_modes,
1618         .mode_valid = intel_dsi_mode_valid,
1619         .atomic_check = intel_digital_connector_atomic_check,
1620 };
1621
1622 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1623         .detect = intel_panel_detect,
1624         .late_register = intel_connector_register,
1625         .early_unregister = intel_connector_unregister,
1626         .destroy = intel_connector_destroy,
1627         .fill_modes = drm_helper_probe_single_connector_modes,
1628         .atomic_get_property = intel_digital_connector_atomic_get_property,
1629         .atomic_set_property = intel_digital_connector_atomic_set_property,
1630         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1631         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1632 };
1633
1634 static void vlv_dsi_add_properties(struct intel_connector *connector)
1635 {
1636         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1637
1638         if (connector->panel.fixed_mode) {
1639                 u32 allowed_scalers;
1640
1641                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1642                 if (!HAS_GMCH(dev_priv))
1643                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1644
1645                 drm_connector_attach_scaling_mode_property(&connector->base,
1646                                                                 allowed_scalers);
1647
1648                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1649
1650                 drm_connector_set_panel_orientation_with_quirk(
1651                                 &connector->base,
1652                                 intel_dsi_get_panel_orientation(connector),
1653                                 connector->panel.fixed_mode->hdisplay,
1654                                 connector->panel.fixed_mode->vdisplay);
1655         }
1656 }
1657
1658 #define NS_KHZ_RATIO            1000000
1659
1660 #define PREPARE_CNT_MAX         0x3F
1661 #define EXIT_ZERO_CNT_MAX       0x3F
1662 #define CLK_ZERO_CNT_MAX        0xFF
1663 #define TRAIL_CNT_MAX           0x1F
1664
1665 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1666 {
1667         struct drm_device *dev = intel_dsi->base.base.dev;
1668         struct drm_i915_private *dev_priv = to_i915(dev);
1669         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1670         u32 tlpx_ns, extra_byte_count, tlpx_ui;
1671         u32 ui_num, ui_den;
1672         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1673         u32 ths_prepare_ns, tclk_trail_ns;
1674         u32 tclk_prepare_clkzero, ths_prepare_hszero;
1675         u32 lp_to_hs_switch, hs_to_lp_switch;
1676         u32 mul;
1677
1678         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1679
1680         switch (intel_dsi->lane_count) {
1681         case 1:
1682         case 2:
1683                 extra_byte_count = 2;
1684                 break;
1685         case 3:
1686                 extra_byte_count = 4;
1687                 break;
1688         case 4:
1689         default:
1690                 extra_byte_count = 3;
1691                 break;
1692         }
1693
1694         /* in Kbps */
1695         ui_num = NS_KHZ_RATIO;
1696         ui_den = intel_dsi_bitrate(intel_dsi);
1697
1698         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1699         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1700
1701         /*
1702          * B060
1703          * LP byte clock = TLPX/ (8UI)
1704          */
1705         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1706
1707         /* DDR clock period = 2 * UI
1708          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1709          * UI(nsec) = 10^6 / bitrate
1710          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1711          * DDR clock count  = ns_value / DDR clock period
1712          *
1713          * For GEMINILAKE dphy_param_reg will be programmed in terms of
1714          * HS byte clock count for other platform in HS ddr clock count
1715          */
1716         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1717         ths_prepare_ns = max(mipi_config->ths_prepare,
1718                              mipi_config->tclk_prepare);
1719
1720         /* prepare count */
1721         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1722
1723         if (prepare_cnt > PREPARE_CNT_MAX) {
1724                 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1725                             prepare_cnt);
1726                 prepare_cnt = PREPARE_CNT_MAX;
1727         }
1728
1729         /* exit zero count */
1730         exit_zero_cnt = DIV_ROUND_UP(
1731                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1732                                 ui_num * mul
1733                                 );
1734
1735         /*
1736          * Exit zero is unified val ths_zero and ths_exit
1737          * minimum value for ths_exit = 110ns
1738          * min (exit_zero_cnt * 2) = 110/UI
1739          * exit_zero_cnt = 55/UI
1740          */
1741         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1742                 exit_zero_cnt += 1;
1743
1744         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1745                 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1746                             exit_zero_cnt);
1747                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1748         }
1749
1750         /* clk zero count */
1751         clk_zero_cnt = DIV_ROUND_UP(
1752                                 (tclk_prepare_clkzero - ths_prepare_ns)
1753                                 * ui_den, ui_num * mul);
1754
1755         if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1756                 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1757                             clk_zero_cnt);
1758                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1759         }
1760
1761         /* trail count */
1762         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1763         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1764
1765         if (trail_cnt > TRAIL_CNT_MAX) {
1766                 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1767                             trail_cnt);
1768                 trail_cnt = TRAIL_CNT_MAX;
1769         }
1770
1771         /* B080 */
1772         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1773                                                 clk_zero_cnt << 8 | prepare_cnt;
1774
1775         /*
1776          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1777          *                                      mul + 10UI + Extra Byte Count
1778          *
1779          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1780          * Extra Byte Count is calculated according to number of lanes.
1781          * High Low Switch Count is the Max of LP to HS and
1782          * HS to LP switch count
1783          *
1784          */
1785         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1786
1787         /* B044 */
1788         /* FIXME:
1789          * The comment above does not match with the code */
1790         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1791                                                 exit_zero_cnt * mul + 10, 8);
1792
1793         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1794
1795         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1796         intel_dsi->hs_to_lp_count += extra_byte_count;
1797
1798         /* B088 */
1799         /* LP -> HS for clock lanes
1800          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1801          *                                              extra byte count
1802          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1803          *                                      2(in UI) + extra byte count
1804          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1805          *                                      8 + extra byte count
1806          */
1807         intel_dsi->clk_lp_to_hs_count =
1808                 DIV_ROUND_UP(
1809                         4 * tlpx_ui + prepare_cnt * 2 +
1810                         clk_zero_cnt * 2,
1811                         8);
1812
1813         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1814
1815         /* HS->LP for Clock Lanes
1816          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1817          *                                              Extra byte count
1818          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1819          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1820          *                                              Extra byte count
1821          */
1822         intel_dsi->clk_hs_to_lp_count =
1823                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1824                         8);
1825         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1826
1827         intel_dsi_log_params(intel_dsi);
1828 }
1829
1830 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1831 {
1832         struct drm_device *dev = &dev_priv->drm;
1833         struct intel_dsi *intel_dsi;
1834         struct intel_encoder *intel_encoder;
1835         struct drm_encoder *encoder;
1836         struct intel_connector *intel_connector;
1837         struct drm_connector *connector;
1838         struct drm_display_mode *current_mode, *fixed_mode;
1839         enum port port;
1840         enum pipe pipe;
1841
1842         drm_dbg_kms(&dev_priv->drm, "\n");
1843
1844         /* There is no detection method for MIPI so rely on VBT */
1845         if (!intel_bios_is_dsi_present(dev_priv, &port))
1846                 return;
1847
1848         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1849                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1850         else
1851                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1852
1853         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1854         if (!intel_dsi)
1855                 return;
1856
1857         intel_connector = intel_connector_alloc();
1858         if (!intel_connector) {
1859                 kfree(intel_dsi);
1860                 return;
1861         }
1862
1863         intel_encoder = &intel_dsi->base;
1864         encoder = &intel_encoder->base;
1865         intel_dsi->attached_connector = intel_connector;
1866
1867         connector = &intel_connector->base;
1868
1869         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1870                          "DSI %c", port_name(port));
1871
1872         intel_encoder->compute_config = intel_dsi_compute_config;
1873         intel_encoder->pre_enable = intel_dsi_pre_enable;
1874         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1875                 intel_encoder->enable = bxt_dsi_enable;
1876         intel_encoder->disable = intel_dsi_disable;
1877         intel_encoder->post_disable = intel_dsi_post_disable;
1878         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1879         intel_encoder->get_config = intel_dsi_get_config;
1880         intel_encoder->update_pipe = intel_panel_update_backlight;
1881         intel_encoder->shutdown = intel_dsi_shutdown;
1882
1883         intel_connector->get_hw_state = intel_connector_get_hw_state;
1884
1885         intel_encoder->port = port;
1886         intel_encoder->type = INTEL_OUTPUT_DSI;
1887         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1888         intel_encoder->cloneable = 0;
1889
1890         /*
1891          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1892          * port C. BXT isn't limited like this.
1893          */
1894         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1895                 intel_encoder->pipe_mask = ~0;
1896         else if (port == PORT_A)
1897                 intel_encoder->pipe_mask = BIT(PIPE_A);
1898         else
1899                 intel_encoder->pipe_mask = BIT(PIPE_B);
1900
1901         intel_dsi->panel_power_off_time = ktime_get_boottime();
1902
1903         if (dev_priv->vbt.dsi.config->dual_link)
1904                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1905         else
1906                 intel_dsi->ports = BIT(port);
1907
1908         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1909         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1910
1911         /* Create a DSI host (and a device) for each port. */
1912         for_each_dsi_port(port, intel_dsi->ports) {
1913                 struct intel_dsi_host *host;
1914
1915                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1916                                            port);
1917                 if (!host)
1918                         goto err;
1919
1920                 intel_dsi->dsi_hosts[port] = host;
1921         }
1922
1923         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1924                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1925                 goto err;
1926         }
1927
1928         /* Use clock read-back from current hw-state for fastboot */
1929         current_mode = intel_encoder_current_mode(intel_encoder);
1930         if (current_mode) {
1931                 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1932                             intel_dsi->pclk, current_mode->clock);
1933                 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1934                                             current_mode->clock)) {
1935                         drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1936                         intel_dsi->pclk = current_mode->clock;
1937                 }
1938
1939                 kfree(current_mode);
1940         }
1941
1942         vlv_dphy_param_init(intel_dsi);
1943
1944         intel_dsi_vbt_gpio_init(intel_dsi,
1945                                 intel_dsi_get_hw_state(intel_encoder, &pipe));
1946
1947         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1948                            DRM_MODE_CONNECTOR_DSI);
1949
1950         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1951
1952         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1953         connector->interlace_allowed = false;
1954         connector->doublescan_allowed = false;
1955
1956         intel_connector_attach_encoder(intel_connector, intel_encoder);
1957
1958         mutex_lock(&dev->mode_config.mutex);
1959         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1960         mutex_unlock(&dev->mode_config.mutex);
1961
1962         if (!fixed_mode) {
1963                 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1964                 goto err_cleanup_connector;
1965         }
1966
1967         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1968         intel_panel_setup_backlight(connector, INVALID_PIPE);
1969
1970         vlv_dsi_add_properties(intel_connector);
1971
1972         return;
1973
1974 err_cleanup_connector:
1975         drm_connector_cleanup(&intel_connector->base);
1976 err:
1977         drm_encoder_cleanup(&intel_encoder->base);
1978         kfree(intel_dsi);
1979         kfree(intel_connector);
1980 }