drivers/gpu/drm/i915/display/skl_universal_plane.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <drm/drm_atomic_helper.h>
   7 #include <drm/drm_damage_helper.h>
   8 #include <drm/drm_fourcc.h>
   9 #include <drm/drm_plane_helper.h>
  10
  11 #include "i915_drv.h"
  12 #include "intel_atomic_plane.h"
  13 #include "intel_de.h"
  14 #include "intel_display_types.h"
  15 #include "intel_fb.h"
  16 #include "intel_pm.h"
  17 #include "intel_psr.h"
  18 #include "intel_sprite.h"
  19 #include "skl_scaler.h"
  20 #include "skl_universal_plane.h"
  21 #include "pxp/intel_pxp.h"
  22
  23 static const u32 skl_plane_formats[] = {
  24         DRM_FORMAT_C8,
  25         DRM_FORMAT_RGB565,
  26         DRM_FORMAT_XRGB8888,
  27         DRM_FORMAT_XBGR8888,
  28         DRM_FORMAT_ARGB8888,
  29         DRM_FORMAT_ABGR8888,
  30         DRM_FORMAT_XRGB2101010,
  31         DRM_FORMAT_XBGR2101010,
  32         DRM_FORMAT_XRGB16161616F,
  33         DRM_FORMAT_XBGR16161616F,
  34         DRM_FORMAT_YUYV,
  35         DRM_FORMAT_YVYU,
  36         DRM_FORMAT_UYVY,
  37         DRM_FORMAT_VYUY,
  38         DRM_FORMAT_XYUV8888,
  39 };
  40
  41 static const u32 skl_planar_formats[] = {
  42         DRM_FORMAT_C8,
  43         DRM_FORMAT_RGB565,
  44         DRM_FORMAT_XRGB8888,
  45         DRM_FORMAT_XBGR8888,
  46         DRM_FORMAT_ARGB8888,
  47         DRM_FORMAT_ABGR8888,
  48         DRM_FORMAT_XRGB2101010,
  49         DRM_FORMAT_XBGR2101010,
  50         DRM_FORMAT_XRGB16161616F,
  51         DRM_FORMAT_XBGR16161616F,
  52         DRM_FORMAT_YUYV,
  53         DRM_FORMAT_YVYU,
  54         DRM_FORMAT_UYVY,
  55         DRM_FORMAT_VYUY,
  56         DRM_FORMAT_NV12,
  57         DRM_FORMAT_XYUV8888,
  58 };
  59
  60 static const u32 glk_planar_formats[] = {
  61         DRM_FORMAT_C8,
  62         DRM_FORMAT_RGB565,
  63         DRM_FORMAT_XRGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ARGB8888,
  66         DRM_FORMAT_ABGR8888,
  67         DRM_FORMAT_XRGB2101010,
  68         DRM_FORMAT_XBGR2101010,
  69         DRM_FORMAT_XRGB16161616F,
  70         DRM_FORMAT_XBGR16161616F,
  71         DRM_FORMAT_YUYV,
  72         DRM_FORMAT_YVYU,
  73         DRM_FORMAT_UYVY,
  74         DRM_FORMAT_VYUY,
  75         DRM_FORMAT_NV12,
  76         DRM_FORMAT_XYUV8888,
  77         DRM_FORMAT_P010,
  78         DRM_FORMAT_P012,
  79         DRM_FORMAT_P016,
  80 };
  81
  82 static const u32 icl_sdr_y_plane_formats[] = {
  83         DRM_FORMAT_C8,
  84         DRM_FORMAT_RGB565,
  85         DRM_FORMAT_XRGB8888,
  86         DRM_FORMAT_XBGR8888,
  87         DRM_FORMAT_ARGB8888,
  88         DRM_FORMAT_ABGR8888,
  89         DRM_FORMAT_XRGB2101010,
  90         DRM_FORMAT_XBGR2101010,
  91         DRM_FORMAT_ARGB2101010,
  92         DRM_FORMAT_ABGR2101010,
  93         DRM_FORMAT_YUYV,
  94         DRM_FORMAT_YVYU,
  95         DRM_FORMAT_UYVY,
  96         DRM_FORMAT_VYUY,
  97         DRM_FORMAT_Y210,
  98         DRM_FORMAT_Y212,
  99         DRM_FORMAT_Y216,
 100         DRM_FORMAT_XYUV8888,
 101         DRM_FORMAT_XVYU2101010,
 102         DRM_FORMAT_XVYU12_16161616,
 103         DRM_FORMAT_XVYU16161616,
 104 };
 105
 106 static const u32 icl_sdr_uv_plane_formats[] = {
 107         DRM_FORMAT_C8,
 108         DRM_FORMAT_RGB565,
 109         DRM_FORMAT_XRGB8888,
 110         DRM_FORMAT_XBGR8888,
 111         DRM_FORMAT_ARGB8888,
 112         DRM_FORMAT_ABGR8888,
 113         DRM_FORMAT_XRGB2101010,
 114         DRM_FORMAT_XBGR2101010,
 115         DRM_FORMAT_ARGB2101010,
 116         DRM_FORMAT_ABGR2101010,
 117         DRM_FORMAT_YUYV,
 118         DRM_FORMAT_YVYU,
 119         DRM_FORMAT_UYVY,
 120         DRM_FORMAT_VYUY,
 121         DRM_FORMAT_NV12,
 122         DRM_FORMAT_P010,
 123         DRM_FORMAT_P012,
 124         DRM_FORMAT_P016,
 125         DRM_FORMAT_Y210,
 126         DRM_FORMAT_Y212,
 127         DRM_FORMAT_Y216,
 128         DRM_FORMAT_XYUV8888,
 129         DRM_FORMAT_XVYU2101010,
 130         DRM_FORMAT_XVYU12_16161616,
 131         DRM_FORMAT_XVYU16161616,
 132 };
 133
 134 static const u32 icl_hdr_plane_formats[] = {
 135         DRM_FORMAT_C8,
 136         DRM_FORMAT_RGB565,
 137         DRM_FORMAT_XRGB8888,
 138         DRM_FORMAT_XBGR8888,
 139         DRM_FORMAT_ARGB8888,
 140         DRM_FORMAT_ABGR8888,
 141         DRM_FORMAT_XRGB2101010,
 142         DRM_FORMAT_XBGR2101010,
 143         DRM_FORMAT_ARGB2101010,
 144         DRM_FORMAT_ABGR2101010,
 145         DRM_FORMAT_XRGB16161616F,
 146         DRM_FORMAT_XBGR16161616F,
 147         DRM_FORMAT_ARGB16161616F,
 148         DRM_FORMAT_ABGR16161616F,
 149         DRM_FORMAT_YUYV,
 150         DRM_FORMAT_YVYU,
 151         DRM_FORMAT_UYVY,
 152         DRM_FORMAT_VYUY,
 153         DRM_FORMAT_NV12,
 154         DRM_FORMAT_P010,
 155         DRM_FORMAT_P012,
 156         DRM_FORMAT_P016,
 157         DRM_FORMAT_Y210,
 158         DRM_FORMAT_Y212,
 159         DRM_FORMAT_Y216,
 160         DRM_FORMAT_XYUV8888,
 161         DRM_FORMAT_XVYU2101010,
 162         DRM_FORMAT_XVYU12_16161616,
 163         DRM_FORMAT_XVYU16161616,
 164 };
 165
 166 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 167 {
 168         switch (format) {
 169         case PLANE_CTL_FORMAT_RGB_565:
 170                 return DRM_FORMAT_RGB565;
 171         case PLANE_CTL_FORMAT_NV12:
 172                 return DRM_FORMAT_NV12;
 173         case PLANE_CTL_FORMAT_XYUV:
 174                 return DRM_FORMAT_XYUV8888;
 175         case PLANE_CTL_FORMAT_P010:
 176                 return DRM_FORMAT_P010;
 177         case PLANE_CTL_FORMAT_P012:
 178                 return DRM_FORMAT_P012;
 179         case PLANE_CTL_FORMAT_P016:
 180                 return DRM_FORMAT_P016;
 181         case PLANE_CTL_FORMAT_Y210:
 182                 return DRM_FORMAT_Y210;
 183         case PLANE_CTL_FORMAT_Y212:
 184                 return DRM_FORMAT_Y212;
 185         case PLANE_CTL_FORMAT_Y216:
 186                 return DRM_FORMAT_Y216;
 187         case PLANE_CTL_FORMAT_Y410:
 188                 return DRM_FORMAT_XVYU2101010;
 189         case PLANE_CTL_FORMAT_Y412:
 190                 return DRM_FORMAT_XVYU12_16161616;
 191         case PLANE_CTL_FORMAT_Y416:
 192                 return DRM_FORMAT_XVYU16161616;
 193         default:
 194         case PLANE_CTL_FORMAT_XRGB_8888:
 195                 if (rgb_order) {
 196                         if (alpha)
 197                                 return DRM_FORMAT_ABGR8888;
 198                         else
 199                                 return DRM_FORMAT_XBGR8888;
 200                 } else {
 201                         if (alpha)
 202                                 return DRM_FORMAT_ARGB8888;
 203                         else
 204                                 return DRM_FORMAT_XRGB8888;
 205                 }
 206         case PLANE_CTL_FORMAT_XRGB_2101010:
 207                 if (rgb_order) {
 208                         if (alpha)
 209                                 return DRM_FORMAT_ABGR2101010;
 210                         else
 211                                 return DRM_FORMAT_XBGR2101010;
 212                 } else {
 213                         if (alpha)
 214                                 return DRM_FORMAT_ARGB2101010;
 215                         else
 216                                 return DRM_FORMAT_XRGB2101010;
 217                 }
 218         case PLANE_CTL_FORMAT_XRGB_16161616F:
 219                 if (rgb_order) {
 220                         if (alpha)
 221                                 return DRM_FORMAT_ABGR16161616F;
 222                         else
 223                                 return DRM_FORMAT_XBGR16161616F;
 224                 } else {
 225                         if (alpha)
 226                                 return DRM_FORMAT_ARGB16161616F;
 227                         else
 228                                 return DRM_FORMAT_XRGB16161616F;
 229                 }
 230         }
 231 }
 232
 233 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 234 {
 235         if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
 236                 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
 237         else
 238                 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
 239 }
 240
 241 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
 242                          enum plane_id plane_id)
 243 {
 244         return DISPLAY_VER(dev_priv) >= 11 &&
 245                 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
 246 }
 247
 248 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
 249 {
 250         return DISPLAY_VER(dev_priv) >= 11 &&
 251                 icl_hdr_plane_mask() & BIT(plane_id);
 252 }
 253
 254 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 255                                const struct intel_plane_state *plane_state)
 256 {
 257         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 258
 259         /* two pixels per clock */
 260         return DIV_ROUND_UP(pixel_rate, 2);
 261 }
 262
 263 static void
 264 glk_plane_ratio(const struct intel_plane_state *plane_state,
 265                 unsigned int *num, unsigned int *den)
 266 {
 267         const struct drm_framebuffer *fb = plane_state->hw.fb;
 268
 269         if (fb->format->cpp[0] == 8) {
 270                 *num = 10;
 271                 *den = 8;
 272         } else {
 273                 *num = 1;
 274                 *den = 1;
 275         }
 276 }
 277
 278 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 279                                const struct intel_plane_state *plane_state)
 280 {
 281         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 282         unsigned int num, den;
 283
 284         glk_plane_ratio(plane_state, &num, &den);
 285
 286         /* two pixels per clock */
 287         return DIV_ROUND_UP(pixel_rate * num, 2 * den);
 288 }
 289
 290 static void
 291 skl_plane_ratio(const struct intel_plane_state *plane_state,
 292                 unsigned int *num, unsigned int *den)
 293 {
 294         const struct drm_framebuffer *fb = plane_state->hw.fb;
 295
 296         if (fb->format->cpp[0] == 8) {
 297                 *num = 9;
 298                 *den = 8;
 299         } else {
 300                 *num = 1;
 301                 *den = 1;
 302         }
 303 }
 304
 305 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 306                                const struct intel_plane_state *plane_state)
 307 {
 308         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 309         unsigned int num, den;
 310
 311         skl_plane_ratio(plane_state, &num, &den);
 312
 313         return DIV_ROUND_UP(pixel_rate * num, den);
 314 }
 315
 316 static int skl_plane_max_width(const struct drm_framebuffer *fb,
 317                                int color_plane,
 318                                unsigned int rotation)
 319 {
 320         int cpp = fb->format->cpp[color_plane];
 321
 322         switch (fb->modifier) {
 323         case DRM_FORMAT_MOD_LINEAR:
 324         case I915_FORMAT_MOD_X_TILED:
 325                 /*
 326                  * Validated limit is 4k, but has 5k should
 327                  * work apart from the following features:
 328                  * - Ytile (already limited to 4k)
 329                  * - FP16 (already limited to 4k)
 330                  * - render compression (already limited to 4k)
 331                  * - KVMR sprite and cursor (don't care)
 332                  * - horizontal panning (TODO verify this)
 333                  * - pipe and plane scaling (TODO verify this)
 334                  */
 335                 if (cpp == 8)
 336                         return 4096;
 337                 else
 338                         return 5120;
 339         case I915_FORMAT_MOD_Y_TILED_CCS:
 340         case I915_FORMAT_MOD_Yf_TILED_CCS:
 341         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 342                 /* FIXME AUX plane? */
 343         case I915_FORMAT_MOD_Y_TILED:
 344         case I915_FORMAT_MOD_Yf_TILED:
 345                 if (cpp == 8)
 346                         return 2048;
 347                 else
 348                         return 4096;
 349         default:
 350                 MISSING_CASE(fb->modifier);
 351                 return 2048;
 352         }
 353 }
 354
 355 static int glk_plane_max_width(const struct drm_framebuffer *fb,
 356                                int color_plane,
 357                                unsigned int rotation)
 358 {
 359         int cpp = fb->format->cpp[color_plane];
 360
 361         switch (fb->modifier) {
 362         case DRM_FORMAT_MOD_LINEAR:
 363         case I915_FORMAT_MOD_X_TILED:
 364                 if (cpp == 8)
 365                         return 4096;
 366                 else
 367                         return 5120;
 368         case I915_FORMAT_MOD_Y_TILED_CCS:
 369         case I915_FORMAT_MOD_Yf_TILED_CCS:
 370                 /* FIXME AUX plane? */
 371         case I915_FORMAT_MOD_Y_TILED:
 372         case I915_FORMAT_MOD_Yf_TILED:
 373                 if (cpp == 8)
 374                         return 2048;
 375                 else
 376                         return 5120;
 377         default:
 378                 MISSING_CASE(fb->modifier);
 379                 return 2048;
 380         }
 381 }
 382
 383 static int icl_plane_min_width(const struct drm_framebuffer *fb,
 384                                int color_plane,
 385                                unsigned int rotation)
 386 {
 387         /* Wa_14011264657, Wa_14011050563: gen11+ */
 388         switch (fb->format->format) {
 389         case DRM_FORMAT_C8:
 390                 return 18;
 391         case DRM_FORMAT_RGB565:
 392                 return 10;
 393         case DRM_FORMAT_XRGB8888:
 394         case DRM_FORMAT_XBGR8888:
 395         case DRM_FORMAT_ARGB8888:
 396         case DRM_FORMAT_ABGR8888:
 397         case DRM_FORMAT_XRGB2101010:
 398         case DRM_FORMAT_XBGR2101010:
 399         case DRM_FORMAT_ARGB2101010:
 400         case DRM_FORMAT_ABGR2101010:
 401         case DRM_FORMAT_XVYU2101010:
 402         case DRM_FORMAT_Y212:
 403         case DRM_FORMAT_Y216:
 404                 return 6;
 405         case DRM_FORMAT_NV12:
 406                 return 20;
 407         case DRM_FORMAT_P010:
 408         case DRM_FORMAT_P012:
 409         case DRM_FORMAT_P016:
 410                 return 12;
 411         case DRM_FORMAT_XRGB16161616F:
 412         case DRM_FORMAT_XBGR16161616F:
 413         case DRM_FORMAT_ARGB16161616F:
 414         case DRM_FORMAT_ABGR16161616F:
 415         case DRM_FORMAT_XVYU12_16161616:
 416         case DRM_FORMAT_XVYU16161616:
 417                 return 4;
 418         default:
 419                 return 1;
 420         }
 421 }
 422
 423 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
 424                                    int color_plane,
 425                                    unsigned int rotation)
 426 {
 427         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 428                 return 4096;
 429         else
 430                 return 5120;
 431 }
 432
 433 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
 434                                    int color_plane,
 435                                    unsigned int rotation)
 436 {
 437         return 5120;
 438 }
 439
 440 static int skl_plane_max_height(const struct drm_framebuffer *fb,
 441                                 int color_plane,
 442                                 unsigned int rotation)
 443 {
 444         return 4096;
 445 }
 446
 447 static int icl_plane_max_height(const struct drm_framebuffer *fb,
 448                                 int color_plane,
 449                                 unsigned int rotation)
 450 {
 451         return 4320;
 452 }
 453
 454 static unsigned int
 455 skl_plane_max_stride(struct intel_plane *plane,
 456                      u32 pixel_format, u64 modifier,
 457                      unsigned int rotation)
 458 {
 459         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 460         const struct drm_format_info *info = drm_format_info(pixel_format);
 461         int cpp = info->cpp[0];
 462         int max_horizontal_pixels = 8192;
 463         int max_stride_bytes;
 464
 465         if (DISPLAY_VER(i915) >= 13) {
 466                 /*
 467                  * The stride in bytes must not exceed of the size
 468                  * of 128K bytes. For pixel formats of 64bpp will allow
 469                  * for a 16K pixel surface.
 470                  */
 471                 max_stride_bytes = 131072;
 472                 if (cpp == 8)
 473                         max_horizontal_pixels = 16384;
 474                 else
 475                         max_horizontal_pixels = 65536;
 476         } else {
 477                 /*
 478                  * "The stride in bytes must not exceed the
 479                  * of the size of 8K pixels and 32K bytes."
 480                  */
 481                 max_stride_bytes = 32768;
 482         }
 483
 484         if (drm_rotation_90_or_270(rotation))
 485                 return min(max_horizontal_pixels, max_stride_bytes / cpp);
 486         else
 487                 return min(max_horizontal_pixels * cpp, max_stride_bytes);
 488 }
 489
 490
 491 /* Preoffset values for YUV to RGB Conversion */
 492 #define PREOFF_YUV_TO_RGB_HI            0x1800
 493 #define PREOFF_YUV_TO_RGB_ME            0x0000
 494 #define PREOFF_YUV_TO_RGB_LO            0x1800
 495
 496 #define  ROFF(x)          (((x) & 0xffff) << 16)
 497 #define  GOFF(x)          (((x) & 0xffff) << 0)
 498 #define  BOFF(x)          (((x) & 0xffff) << 16)
 499
 500 /*
 501  * Programs the input color space conversion stage for ICL HDR planes.
 502  * Note that it is assumed that this stage always happens after YUV
 503  * range correction. Thus, the input to this stage is assumed to be
 504  * in full-range YCbCr.
 505  */
 506 static void
 507 icl_program_input_csc(struct intel_plane *plane,
 508                       const struct intel_crtc_state *crtc_state,
 509                       const struct intel_plane_state *plane_state)
 510 {
 511         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 512         enum pipe pipe = plane->pipe;
 513         enum plane_id plane_id = plane->id;
 514
 515         static const u16 input_csc_matrix[][9] = {
 516                 /*
 517                  * BT.601 full range YCbCr -> full range RGB
 518                  * The matrix required is :
 519                  * [1.000, 0.000, 1.371,
 520                  *  1.000, -0.336, -0.698,
 521                  *  1.000, 1.732, 0.0000]
 522                  */
 523                 [DRM_COLOR_YCBCR_BT601] = {
 524                         0x7AF8, 0x7800, 0x0,
 525                         0x8B28, 0x7800, 0x9AC0,
 526                         0x0, 0x7800, 0x7DD8,
 527                 },
 528                 /*
 529                  * BT.709 full range YCbCr -> full range RGB
 530                  * The matrix required is :
 531                  * [1.000, 0.000, 1.574,
 532                  *  1.000, -0.187, -0.468,
 533                  *  1.000, 1.855, 0.0000]
 534                  */
 535                 [DRM_COLOR_YCBCR_BT709] = {
 536                         0x7C98, 0x7800, 0x0,
 537                         0x9EF8, 0x7800, 0xAC00,
 538                         0x0, 0x7800,  0x7ED8,
 539                 },
 540                 /*
 541                  * BT.2020 full range YCbCr -> full range RGB
 542                  * The matrix required is :
 543                  * [1.000, 0.000, 1.474,
 544                  *  1.000, -0.1645, -0.5713,
 545                  *  1.000, 1.8814, 0.0000]
 546                  */
 547                 [DRM_COLOR_YCBCR_BT2020] = {
 548                         0x7BC8, 0x7800, 0x0,
 549                         0x8928, 0x7800, 0xAA88,
 550                         0x0, 0x7800, 0x7F10,
 551                 },
 552         };
 553         const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
 554
 555         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
 556                           ROFF(csc[0]) | GOFF(csc[1]));
 557         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),
 558                           BOFF(csc[2]));
 559         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),
 560                           ROFF(csc[3]) | GOFF(csc[4]));
 561         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),
 562                           BOFF(csc[5]));
 563         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),
 564                           ROFF(csc[6]) | GOFF(csc[7]));
 565         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),
 566                           BOFF(csc[8]));
 567
 568         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
 569                           PREOFF_YUV_TO_RGB_HI);
 570         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
 571                           PREOFF_YUV_TO_RGB_ME);
 572         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
 573                           PREOFF_YUV_TO_RGB_LO);
 574         intel_de_write_fw(dev_priv,
 575                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
 576         intel_de_write_fw(dev_priv,
 577                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
 578         intel_de_write_fw(dev_priv,
 579                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 580 }
 581
 582 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 583                                           int color_plane, unsigned int rotation)
 584 {
 585         /*
 586          * The stride is either expressed as a multiple of 64 bytes chunks for
 587          * linear buffers or in number of tiles for tiled buffers.
 588          */
 589         if (is_surface_linear(fb, color_plane))
 590                 return 64;
 591         else if (drm_rotation_90_or_270(rotation))
 592                 return intel_tile_height(fb, color_plane);
 593         else
 594                 return intel_tile_width_bytes(fb, color_plane);
 595 }
 596
 597 static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 598                             int color_plane)
 599 {
 600         const struct drm_framebuffer *fb = plane_state->hw.fb;
 601         unsigned int rotation = plane_state->hw.rotation;
 602         u32 stride = plane_state->view.color_plane[color_plane].scanout_stride;
 603
 604         if (color_plane >= fb->format->num_planes)
 605                 return 0;
 606
 607         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
 608 }
 609
 610 static void
 611 skl_plane_disable_arm(struct intel_plane *plane,
 612                       const struct intel_crtc_state *crtc_state)
 613 {
 614         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 615         enum plane_id plane_id = plane->id;
 616         enum pipe pipe = plane->pipe;
 617         unsigned long irqflags;
 618
 619         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 620
 621         if (icl_is_hdr_plane(dev_priv, plane_id))
 622                 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
 623
 624         skl_write_plane_wm(plane, crtc_state);
 625
 626         intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
 627         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
 628         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
 629
 630         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 631 }
 632
 633 static bool
 634 skl_plane_get_hw_state(struct intel_plane *plane,
 635                        enum pipe *pipe)
 636 {
 637         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 638         enum intel_display_power_domain power_domain;
 639         enum plane_id plane_id = plane->id;
 640         intel_wakeref_t wakeref;
 641         bool ret;
 642
 643         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 644         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 645         if (!wakeref)
 646                 return false;
 647
 648         ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
 649
 650         *pipe = plane->pipe;
 651
 652         intel_display_power_put(dev_priv, power_domain, wakeref);
 653
 654         return ret;
 655 }
 656
 657 static u32 skl_plane_ctl_format(u32 pixel_format)
 658 {
 659         switch (pixel_format) {
 660         case DRM_FORMAT_C8:
 661                 return PLANE_CTL_FORMAT_INDEXED;
 662         case DRM_FORMAT_RGB565:
 663                 return PLANE_CTL_FORMAT_RGB_565;
 664         case DRM_FORMAT_XBGR8888:
 665         case DRM_FORMAT_ABGR8888:
 666                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
 667         case DRM_FORMAT_XRGB8888:
 668         case DRM_FORMAT_ARGB8888:
 669                 return PLANE_CTL_FORMAT_XRGB_8888;
 670         case DRM_FORMAT_XBGR2101010:
 671         case DRM_FORMAT_ABGR2101010:
 672                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
 673         case DRM_FORMAT_XRGB2101010:
 674         case DRM_FORMAT_ARGB2101010:
 675                 return PLANE_CTL_FORMAT_XRGB_2101010;
 676         case DRM_FORMAT_XBGR16161616F:
 677         case DRM_FORMAT_ABGR16161616F:
 678                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
 679         case DRM_FORMAT_XRGB16161616F:
 680         case DRM_FORMAT_ARGB16161616F:
 681                 return PLANE_CTL_FORMAT_XRGB_16161616F;
 682         case DRM_FORMAT_XYUV8888:
 683                 return PLANE_CTL_FORMAT_XYUV;
 684         case DRM_FORMAT_YUYV:
 685                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
 686         case DRM_FORMAT_YVYU:
 687                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
 688         case DRM_FORMAT_UYVY:
 689                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
 690         case DRM_FORMAT_VYUY:
 691                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 692         case DRM_FORMAT_NV12:
 693                 return PLANE_CTL_FORMAT_NV12;
 694         case DRM_FORMAT_P010:
 695                 return PLANE_CTL_FORMAT_P010;
 696         case DRM_FORMAT_P012:
 697                 return PLANE_CTL_FORMAT_P012;
 698         case DRM_FORMAT_P016:
 699                 return PLANE_CTL_FORMAT_P016;
 700         case DRM_FORMAT_Y210:
 701                 return PLANE_CTL_FORMAT_Y210;
 702         case DRM_FORMAT_Y212:
 703                 return PLANE_CTL_FORMAT_Y212;
 704         case DRM_FORMAT_Y216:
 705                 return PLANE_CTL_FORMAT_Y216;
 706         case DRM_FORMAT_XVYU2101010:
 707                 return PLANE_CTL_FORMAT_Y410;
 708         case DRM_FORMAT_XVYU12_16161616:
 709                 return PLANE_CTL_FORMAT_Y412;
 710         case DRM_FORMAT_XVYU16161616:
 711                 return PLANE_CTL_FORMAT_Y416;
 712         default:
 713                 MISSING_CASE(pixel_format);
 714         }
 715
 716         return 0;
 717 }
 718
 719 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
 720 {
 721         if (!plane_state->hw.fb->format->has_alpha)
 722                 return PLANE_CTL_ALPHA_DISABLE;
 723
 724         switch (plane_state->hw.pixel_blend_mode) {
 725         case DRM_MODE_BLEND_PIXEL_NONE:
 726                 return PLANE_CTL_ALPHA_DISABLE;
 727         case DRM_MODE_BLEND_PREMULTI:
 728                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
 729         case DRM_MODE_BLEND_COVERAGE:
 730                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
 731         default:
 732                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
 733                 return PLANE_CTL_ALPHA_DISABLE;
 734         }
 735 }
 736
 737 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
 738 {
 739         if (!plane_state->hw.fb->format->has_alpha)
 740                 return PLANE_COLOR_ALPHA_DISABLE;
 741
 742         switch (plane_state->hw.pixel_blend_mode) {
 743         case DRM_MODE_BLEND_PIXEL_NONE:
 744                 return PLANE_COLOR_ALPHA_DISABLE;
 745         case DRM_MODE_BLEND_PREMULTI:
 746                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
 747         case DRM_MODE_BLEND_COVERAGE:
 748                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
 749         default:
 750                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
 751                 return PLANE_COLOR_ALPHA_DISABLE;
 752         }
 753 }
 754
 755 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 756 {
 757         switch (fb_modifier) {
 758         case DRM_FORMAT_MOD_LINEAR:
 759                 break;
 760         case I915_FORMAT_MOD_X_TILED:
 761                 return PLANE_CTL_TILED_X;
 762         case I915_FORMAT_MOD_Y_TILED:
 763                 return PLANE_CTL_TILED_Y;
 764         case I915_FORMAT_MOD_Y_TILED_CCS:
 765         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 766                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 767         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 768                 return PLANE_CTL_TILED_Y |
 769                        PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 770                        PLANE_CTL_CLEAR_COLOR_DISABLE;
 771         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 772                 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 773         case I915_FORMAT_MOD_Yf_TILED:
 774                 return PLANE_CTL_TILED_YF;
 775         case I915_FORMAT_MOD_Yf_TILED_CCS:
 776                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 777         default:
 778                 MISSING_CASE(fb_modifier);
 779         }
 780
 781         return 0;
 782 }
 783
 784 static u32 skl_plane_ctl_rotate(unsigned int rotate)
 785 {
 786         switch (rotate) {
 787         case DRM_MODE_ROTATE_0:
 788                 break;
 789         /*
 790          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
 791          * while i915 HW rotation is clockwise, thats why this swapping.
 792          */
 793         case DRM_MODE_ROTATE_90:
 794                 return PLANE_CTL_ROTATE_270;
 795         case DRM_MODE_ROTATE_180:
 796                 return PLANE_CTL_ROTATE_180;
 797         case DRM_MODE_ROTATE_270:
 798                 return PLANE_CTL_ROTATE_90;
 799         default:
 800                 MISSING_CASE(rotate);
 801         }
 802
 803         return 0;
 804 }
 805
 806 static u32 icl_plane_ctl_flip(unsigned int reflect)
 807 {
 808         switch (reflect) {
 809         case 0:
 810                 break;
 811         case DRM_MODE_REFLECT_X:
 812                 return PLANE_CTL_FLIP_HORIZONTAL;
 813         case DRM_MODE_REFLECT_Y:
 814         default:
 815                 MISSING_CASE(reflect);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)
 822 {
 823         const struct drm_framebuffer *fb = plane_state->hw.fb;
 824
 825         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 826                 switch (fb->format->cpp[0]) {
 827                 case 2:
 828                         return PLANE_CTL_ARB_SLOTS(1);
 829                 default:
 830                         return PLANE_CTL_ARB_SLOTS(0);
 831                 }
 832         } else {
 833                 switch (fb->format->cpp[0]) {
 834                 case 8:
 835                         return PLANE_CTL_ARB_SLOTS(3);
 836                 case 4:
 837                         return PLANE_CTL_ARB_SLOTS(1);
 838                 default:
 839                         return PLANE_CTL_ARB_SLOTS(0);
 840                 }
 841         }
 842 }
 843
 844 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 845 {
 846         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 847         u32 plane_ctl = 0;
 848
 849         if (DISPLAY_VER(dev_priv) >= 10)
 850                 return plane_ctl;
 851
 852         if (crtc_state->gamma_enable)
 853                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
 854
 855         if (crtc_state->csc_enable)
 856                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 857
 858         return plane_ctl;
 859 }
 860
 861 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 862                          const struct intel_plane_state *plane_state)
 863 {
 864         struct drm_i915_private *dev_priv =
 865                 to_i915(plane_state->uapi.plane->dev);
 866         const struct drm_framebuffer *fb = plane_state->hw.fb;
 867         unsigned int rotation = plane_state->hw.rotation;
 868         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 869         u32 plane_ctl;
 870
 871         plane_ctl = PLANE_CTL_ENABLE;
 872
 873         if (DISPLAY_VER(dev_priv) < 10) {
 874                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
 875                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
 876
 877                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 878                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
 879
 880                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 881                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
 882         }
 883
 884         plane_ctl |= skl_plane_ctl_format(fb->format->format);
 885         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
 886         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
 887
 888         if (DISPLAY_VER(dev_priv) >= 11)
 889                 plane_ctl |= icl_plane_ctl_flip(rotation &
 890                                                 DRM_MODE_REFLECT_MASK);
 891
 892         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 893                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 894         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 895                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 896
 897         /* Wa_22012358565:adl-p */
 898         if (DISPLAY_VER(dev_priv) == 13)
 899                 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
 900
 901         return plane_ctl;
 902 }
 903
 904 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 905 {
 906         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 907         u32 plane_color_ctl = 0;
 908
 909         if (DISPLAY_VER(dev_priv) >= 11)
 910                 return plane_color_ctl;
 911
 912         if (crtc_state->gamma_enable)
 913                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
 914
 915         if (crtc_state->csc_enable)
 916                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
 917
 918         return plane_color_ctl;
 919 }
 920
 921 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 922                                const struct intel_plane_state *plane_state)
 923 {
 924         struct drm_i915_private *dev_priv =
 925                 to_i915(plane_state->uapi.plane->dev);
 926         const struct drm_framebuffer *fb = plane_state->hw.fb;
 927         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 928         u32 plane_color_ctl = 0;
 929
 930         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
 931         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 932
 933         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
 934                 switch (plane_state->hw.color_encoding) {
 935                 case DRM_COLOR_YCBCR_BT709:
 936                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 937                         break;
 938                 case DRM_COLOR_YCBCR_BT2020:
 939                         plane_color_ctl |=
 940                                 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
 941                         break;
 942                 default:
 943                         plane_color_ctl |=
 944                                 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
 945                 }
 946                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 947                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
 948         } else if (fb->format->is_yuv) {
 949                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
 950                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 951                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
 952         }
 953
 954         if (plane_state->force_black)
 955                 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
 956
 957         return plane_color_ctl;
 958 }
 959
 960 static u32 skl_surf_address(const struct intel_plane_state *plane_state,
 961                             int color_plane)
 962 {
 963         const struct drm_framebuffer *fb = plane_state->hw.fb;
 964         u32 offset = plane_state->view.color_plane[color_plane].offset;
 965
 966         if (intel_fb_uses_dpt(fb)) {
 967                 /*
 968                  * The DPT object contains only one vma, so the VMA's offset
 969                  * within the DPT is always 0.
 970                  */
 971                 WARN_ON(plane_state->dpt_vma->node.start);
 972                 WARN_ON(offset & 0x1fffff);
 973                 return offset >> 9;
 974         } else {
 975                 WARN_ON(offset & 0xfff);
 976                 return offset;
 977         }
 978 }
 979
 980 static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
 981                           int color_plane)
 982 {
 983         u32 plane_surf;
 984
 985         plane_surf = intel_plane_ggtt_offset(plane_state) +
 986                 skl_surf_address(plane_state, color_plane);
 987
 988         if (plane_state->decrypt)
 989                 plane_surf |= PLANE_SURF_DECRYPT;
 990
 991         return plane_surf;
 992 }
 993
 994 static void icl_plane_csc_load_black(struct intel_plane *plane)
 995 {
 996         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 997         enum plane_id plane_id = plane->id;
 998         enum pipe pipe = plane->pipe;
 999
1000         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);
1001         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);
1002
1003         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);
1004         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);
1005
1006         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);
1007         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);
1008
1009         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);
1010         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);
1011         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);
1012
1013         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
1014         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
1015         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
1016 }
1017
1018 static void
1019 skl_program_plane_noarm(struct intel_plane *plane,
1020                         const struct intel_crtc_state *crtc_state,
1021                         const struct intel_plane_state *plane_state,
1022                         int color_plane)
1023 {
1024         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1025         enum plane_id plane_id = plane->id;
1026         enum pipe pipe = plane->pipe;
1027         u32 stride = skl_plane_stride(plane_state, color_plane);
1028         const struct drm_framebuffer *fb = plane_state->hw.fb;
1029         int crtc_x = plane_state->uapi.dst.x1;
1030         int crtc_y = plane_state->uapi.dst.y1;
1031         u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1032         u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1033         unsigned long irqflags;
1034
1035         /* Sizes are 0 based */
1036         src_w--;
1037         src_h--;
1038
1039         /* The scaler will handle the output position */
1040         if (plane_state->scaler_id >= 0) {
1041                 crtc_x = 0;
1042                 crtc_y = 0;
1043         }
1044
1045         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1046
1047         /*
1048          * FIXME: pxp session invalidation can hit any time even at time of commit
1049          * or after the commit, display content will be garbage.
1050          */
1051         if (plane_state->force_black)
1052                 icl_plane_csc_load_black(plane);
1053
1054         intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
1055         intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
1056                           (crtc_y << 16) | crtc_x);
1057         intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
1058                           (src_h << 16) | src_w);
1059
1060         if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
1061                 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
1062                                   lower_32_bits(plane_state->ccval));
1063                 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
1064                                   upper_32_bits(plane_state->ccval));
1065         }
1066
1067         if (icl_is_hdr_plane(dev_priv, plane_id))
1068                 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
1069                                   plane_state->cus_ctl);
1070
1071         if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
1072                 icl_program_input_csc(plane, crtc_state, plane_state);
1073
1074         skl_write_plane_wm(plane, crtc_state);
1075
1076         intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
1077
1078         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1079 }
1080
1081 static void
1082 skl_program_plane_arm(struct intel_plane *plane,
1083                       const struct intel_crtc_state *crtc_state,
1084                       const struct intel_plane_state *plane_state,
1085                       int color_plane)
1086 {
1087         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1088         enum plane_id plane_id = plane->id;
1089         enum pipe pipe = plane->pipe;
1090         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1091         const struct drm_framebuffer *fb = plane_state->hw.fb;
1092         int aux_plane = skl_main_to_aux_plane(fb, color_plane);
1093         u32 x = plane_state->view.color_plane[color_plane].x;
1094         u32 y = plane_state->view.color_plane[color_plane].y;
1095         u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
1096         u8 alpha = plane_state->hw.alpha >> 8;
1097         u32 plane_ctl = plane_state->ctl;
1098         unsigned long irqflags;
1099
1100         plane_ctl |= skl_plane_ctl_crtc(crtc_state);
1101
1102         if (DISPLAY_VER(dev_priv) >= 10)
1103                 plane_color_ctl = plane_state->color_ctl |
1104                         glk_plane_color_ctl_crtc(crtc_state);
1105
1106         keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
1107
1108         keymsk = key->channel_mask & 0x7ffffff;
1109         if (alpha < 0xff)
1110                 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
1111
1112         if (aux_plane) {
1113                 aux_dist = skl_surf_address(plane_state, aux_plane) -
1114                         skl_surf_address(plane_state, color_plane);
1115
1116                 if (DISPLAY_VER(dev_priv) < 12)
1117                         aux_dist |= skl_plane_stride(plane_state, aux_plane);
1118         }
1119
1120         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1121
1122         intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
1123                           key->min_value);
1124         intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
1125         intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
1126
1127         intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
1128                           (y << 16) | x);
1129
1130         intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
1131
1132         if (DISPLAY_VER(dev_priv) < 11)
1133                 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
1134                                   (plane_state->view.color_plane[1].y << 16) |
1135                                    plane_state->view.color_plane[1].x);
1136
1137         if (DISPLAY_VER(dev_priv) >= 10)
1138                 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
1139
1140         /*
1141          * Enable the scaler before the plane so that we don't
1142          * get a catastrophic underrun even if the two operations
1143          * end up happening in two different frames.
1144          *
1145          * TODO: split into noarm+arm pair
1146          */
1147         if (plane_state->scaler_id >= 0)
1148                 skl_program_plane_scaler(plane, crtc_state, plane_state);
1149
1150         /*
1151          * The control register self-arms if the plane was previously
1152          * disabled. Try to make the plane enable atomic by writing
1153          * the control register just before the surface register.
1154          */
1155         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1156         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1157                           skl_plane_surf(plane_state, color_plane));
1158
1159         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1160 }
1161
1162 static void
1163 skl_plane_async_flip(struct intel_plane *plane,
1164                      const struct intel_crtc_state *crtc_state,
1165                      const struct intel_plane_state *plane_state,
1166                      bool async_flip)
1167 {
1168         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1169         unsigned long irqflags;
1170         enum plane_id plane_id = plane->id;
1171         enum pipe pipe = plane->pipe;
1172         u32 plane_ctl = plane_state->ctl;
1173
1174         plane_ctl |= skl_plane_ctl_crtc(crtc_state);
1175
1176         if (async_flip)
1177                 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
1178
1179         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1180
1181         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1182         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1183                           skl_plane_surf(plane_state, 0));
1184
1185         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1186 }
1187
1188 static void
1189 skl_plane_update_noarm(struct intel_plane *plane,
1190                        const struct intel_crtc_state *crtc_state,
1191                        const struct intel_plane_state *plane_state)
1192 {
1193         int color_plane = 0;
1194
1195         if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1196                 /* Program the UV plane on planar master */
1197                 color_plane = 1;
1198
1199         skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
1200 }
1201
1202 static void
1203 skl_plane_update_arm(struct intel_plane *plane,
1204                      const struct intel_crtc_state *crtc_state,
1205                      const struct intel_plane_state *plane_state)
1206 {
1207         int color_plane = 0;
1208
1209         if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1210                 /* Program the UV plane on planar master */
1211                 color_plane = 1;
1212
1213         skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
1214 }
1215
1216 static bool intel_format_is_p01x(u32 format)
1217 {
1218         switch (format) {
1219         case DRM_FORMAT_P010:
1220         case DRM_FORMAT_P012:
1221         case DRM_FORMAT_P016:
1222                 return true;
1223         default:
1224                 return false;
1225         }
1226 }
1227
1228 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1229                               const struct intel_plane_state *plane_state)
1230 {
1231         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1232         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1233         const struct drm_framebuffer *fb = plane_state->hw.fb;
1234         unsigned int rotation = plane_state->hw.rotation;
1235
1236         if (!fb)
1237                 return 0;
1238
1239         if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1240             intel_fb_is_ccs_modifier(fb->modifier)) {
1241                 drm_dbg_kms(&dev_priv->drm,
1242                             "RC support only with 0/180 degree rotation (%x)\n",
1243                             rotation);
1244                 return -EINVAL;
1245         }
1246
1247         if (rotation & DRM_MODE_REFLECT_X &&
1248             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1249                 drm_dbg_kms(&dev_priv->drm,
1250                             "horizontal flip is not supported with linear surface formats\n");
1251                 return -EINVAL;
1252         }
1253
1254         if (drm_rotation_90_or_270(rotation)) {
1255                 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {
1256                         drm_dbg_kms(&dev_priv->drm,
1257                                     "Y/Yf tiling required for 90/270!\n");
1258                         return -EINVAL;
1259                 }
1260
1261                 /*
1262                  * 90/270 is not allowed with RGB64 16:16:16:16 and
1263                  * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1264                  */
1265                 switch (fb->format->format) {
1266                 case DRM_FORMAT_RGB565:
1267                         if (DISPLAY_VER(dev_priv) >= 11)
1268                                 break;
1269                         fallthrough;
1270                 case DRM_FORMAT_C8:
1271                 case DRM_FORMAT_XRGB16161616F:
1272                 case DRM_FORMAT_XBGR16161616F:
1273                 case DRM_FORMAT_ARGB16161616F:
1274                 case DRM_FORMAT_ABGR16161616F:
1275                 case DRM_FORMAT_Y210:
1276                 case DRM_FORMAT_Y212:
1277                 case DRM_FORMAT_Y216:
1278                 case DRM_FORMAT_XVYU12_16161616:
1279                 case DRM_FORMAT_XVYU16161616:
1280                         drm_dbg_kms(&dev_priv->drm,
1281                                     "Unsupported pixel format %p4cc for 90/270!\n",
1282                                     &fb->format->format);
1283                         return -EINVAL;
1284                 default:
1285                         break;
1286                 }
1287         }
1288
1289         /* Y-tiling is not supported in IF-ID Interlace mode */
1290         if (crtc_state->hw.enable &&
1291             crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1292             fb->modifier != DRM_FORMAT_MOD_LINEAR &&
1293             fb->modifier != I915_FORMAT_MOD_X_TILED) {
1294                 drm_dbg_kms(&dev_priv->drm,
1295                             "Y/Yf tiling not supported in IF-ID mode\n");
1296                 return -EINVAL;
1297         }
1298
1299         /* Wa_1606054188:tgl,adl-s */
1300         if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
1301             plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
1302             intel_format_is_p01x(fb->format->format)) {
1303                 drm_dbg_kms(&dev_priv->drm,
1304                             "Source color keying not supported with P01x formats\n");
1305                 return -EINVAL;
1306         }
1307
1308         return 0;
1309 }
1310
1311 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1312                                            const struct intel_plane_state *plane_state)
1313 {
1314         struct drm_i915_private *dev_priv =
1315                 to_i915(plane_state->uapi.plane->dev);
1316         int crtc_x = plane_state->uapi.dst.x1;
1317         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
1318         int pipe_src_w = crtc_state->pipe_src_w;
1319
1320         /*
1321          * Display WA #1175: glk
1322          * Planes other than the cursor may cause FIFO underflow and display
1323          * corruption if starting less than 4 pixels from the right edge of
1324          * the screen.
1325          * Besides the above WA fix the similar problem, where planes other
1326          * than the cursor ending less than 4 pixels from the left edge of the
1327          * screen may cause FIFO underflow and display corruption.
1328          */
1329         if (DISPLAY_VER(dev_priv) == 10 &&
1330             (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1331                 drm_dbg_kms(&dev_priv->drm,
1332                             "requested plane X %s position %d invalid (valid range %d-%d)\n",
1333                             crtc_x + crtc_w < 4 ? "end" : "start",
1334                             crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1335                             4, pipe_src_w - 4);
1336                 return -ERANGE;
1337         }
1338
1339         return 0;
1340 }
1341
1342 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
1343 {
1344         const struct drm_framebuffer *fb = plane_state->hw.fb;
1345         unsigned int rotation = plane_state->hw.rotation;
1346         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1347
1348         /* Display WA #1106 */
1349         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1350             src_w & 3 &&
1351             (rotation == DRM_MODE_ROTATE_270 ||
1352              rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1353                 DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n");
1354                 return -EINVAL;
1355         }
1356
1357         return 0;
1358 }
1359
1360 static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
1361                                const struct drm_framebuffer *fb)
1362 {
1363         /*
1364          * We don't yet know the final source width nor
1365          * whether we can use the HQ scaler mode. Assume
1366          * the best case.
1367          * FIXME need to properly check this later.
1368          */
1369         if (DISPLAY_VER(dev_priv) >= 10 ||
1370             !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
1371                 return 0x30000 - 1;
1372         else
1373                 return 0x20000 - 1;
1374 }
1375
1376 static int intel_plane_min_width(struct intel_plane *plane,
1377                                  const struct drm_framebuffer *fb,
1378                                  int color_plane,
1379                                  unsigned int rotation)
1380 {
1381         if (plane->min_width)
1382                 return plane->min_width(fb, color_plane, rotation);
1383         else
1384                 return 1;
1385 }
1386
1387 static int intel_plane_max_width(struct intel_plane *plane,
1388                                  const struct drm_framebuffer *fb,
1389                                  int color_plane,
1390                                  unsigned int rotation)
1391 {
1392         if (plane->max_width)
1393                 return plane->max_width(fb, color_plane, rotation);
1394         else
1395                 return INT_MAX;
1396 }
1397
1398 static int intel_plane_max_height(struct intel_plane *plane,
1399                                   const struct drm_framebuffer *fb,
1400                                   int color_plane,
1401                                   unsigned int rotation)
1402 {
1403         if (plane->max_height)
1404                 return plane->max_height(fb, color_plane, rotation);
1405         else
1406                 return INT_MAX;
1407 }
1408
1409 static bool
1410 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
1411                                int main_x, int main_y, u32 main_offset,
1412                                int ccs_plane)
1413 {
1414         const struct drm_framebuffer *fb = plane_state->hw.fb;
1415         int aux_x = plane_state->view.color_plane[ccs_plane].x;
1416         int aux_y = plane_state->view.color_plane[ccs_plane].y;
1417         u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1418         u32 alignment = intel_surf_alignment(fb, ccs_plane);
1419         int hsub;
1420         int vsub;
1421
1422         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1423         while (aux_offset >= main_offset && aux_y <= main_y) {
1424                 int x, y;
1425
1426                 if (aux_x == main_x && aux_y == main_y)
1427                         break;
1428
1429                 if (aux_offset == 0)
1430                         break;
1431
1432                 x = aux_x / hsub;
1433                 y = aux_y / vsub;
1434                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
1435                                                                plane_state,
1436                                                                ccs_plane,
1437                                                                aux_offset,
1438                                                                aux_offset -
1439                                                                 alignment);
1440                 aux_x = x * hsub + aux_x % hsub;
1441                 aux_y = y * vsub + aux_y % vsub;
1442         }
1443
1444         if (aux_x != main_x || aux_y != main_y)
1445                 return false;
1446
1447         plane_state->view.color_plane[ccs_plane].offset = aux_offset;
1448         plane_state->view.color_plane[ccs_plane].x = aux_x;
1449         plane_state->view.color_plane[ccs_plane].y = aux_y;
1450
1451         return true;
1452 }
1453
1454
1455 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
1456                                  int *x, int *y, u32 *offset)
1457 {
1458         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1459         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1460         const struct drm_framebuffer *fb = plane_state->hw.fb;
1461         const int aux_plane = skl_main_to_aux_plane(fb, 0);
1462         const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset;
1463         const u32 alignment = intel_surf_alignment(fb, 0);
1464         const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1465
1466         intel_add_fb_offsets(x, y, plane_state, 0);
1467         *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
1468         if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
1469                 return -EINVAL;
1470
1471         /*
1472          * AUX surface offset is specified as the distance from the
1473          * main surface offset, and it must be non-negative. Make
1474          * sure that is what we will get.
1475          */
1476         if (aux_plane && *offset > aux_offset)
1477                 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1478                                                             *offset,
1479                                                             aux_offset & ~(alignment - 1));
1480
1481         /*
1482          * When using an X-tiled surface, the plane blows up
1483          * if the x offset + width exceed the stride.
1484          *
1485          * TODO: linear and Y-tiled seem fine, Yf untested,
1486          */
1487         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
1488                 int cpp = fb->format->cpp[0];
1489
1490                 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) {
1491                         if (*offset == 0) {
1492                                 drm_dbg_kms(&dev_priv->drm,
1493                                             "Unable to find suitable display surface offset due to X-tiling\n");
1494                                 return -EINVAL;
1495                         }
1496
1497                         *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1498                                                                     *offset,
1499                                                                     *offset - alignment);
1500                 }
1501         }
1502
1503         return 0;
1504 }
1505
1506 static int skl_check_main_surface(struct intel_plane_state *plane_state)
1507 {
1508         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1509         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1510         const struct drm_framebuffer *fb = plane_state->hw.fb;
1511         const unsigned int rotation = plane_state->hw.rotation;
1512         int x = plane_state->uapi.src.x1 >> 16;
1513         int y = plane_state->uapi.src.y1 >> 16;
1514         const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1515         const int h = drm_rect_height(&plane_state->uapi.src) >> 16;
1516         const int min_width = intel_plane_min_width(plane, fb, 0, rotation);
1517         const int max_width = intel_plane_max_width(plane, fb, 0, rotation);
1518         const int max_height = intel_plane_max_height(plane, fb, 0, rotation);
1519         const int aux_plane = skl_main_to_aux_plane(fb, 0);
1520         const u32 alignment = intel_surf_alignment(fb, 0);
1521         u32 offset;
1522         int ret;
1523
1524         if (w > max_width || w < min_width || h > max_height) {
1525                 drm_dbg_kms(&dev_priv->drm,
1526                             "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
1527                             w, h, min_width, max_width, max_height);
1528                 return -EINVAL;
1529         }
1530
1531         ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
1532         if (ret)
1533                 return ret;
1534
1535         /*
1536          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
1537          * they match with the main surface x/y offsets.
1538          */
1539         if (intel_fb_is_ccs_modifier(fb->modifier)) {
1540                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1541                                                        offset, aux_plane)) {
1542                         if (offset == 0)
1543                                 break;
1544
1545                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
1546                                                                    offset, offset - alignment);
1547                 }
1548
1549                 if (x != plane_state->view.color_plane[aux_plane].x ||
1550                     y != plane_state->view.color_plane[aux_plane].y) {
1551                         drm_dbg_kms(&dev_priv->drm,
1552                                     "Unable to find suitable display surface offset due to CCS\n");
1553                         return -EINVAL;
1554                 }
1555         }
1556
1557         if (DISPLAY_VER(dev_priv) >= 13)
1558                 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
1559         else
1560                 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
1561
1562         plane_state->view.color_plane[0].offset = offset;
1563         plane_state->view.color_plane[0].x = x;
1564         plane_state->view.color_plane[0].y = y;
1565
1566         /*
1567          * Put the final coordinates back so that the src
1568          * coordinate checks will see the right values.
1569          */
1570         drm_rect_translate_to(&plane_state->uapi.src,
1571                               x << 16, y << 16);
1572
1573         return 0;
1574 }
1575
1576 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
1577 {
1578         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1579         struct drm_i915_private *i915 = to_i915(plane->base.dev);
1580         const struct drm_framebuffer *fb = plane_state->hw.fb;
1581         unsigned int rotation = plane_state->hw.rotation;
1582         int uv_plane = 1;
1583         int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
1584         int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
1585         int x = plane_state->uapi.src.x1 >> 17;
1586         int y = plane_state->uapi.src.y1 >> 17;
1587         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
1588         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
1589         u32 offset;
1590
1591         /* FIXME not quite sure how/if these apply to the chroma plane */
1592         if (w > max_width || h > max_height) {
1593                 drm_dbg_kms(&i915->drm,
1594                             "CbCr source size %dx%d too big (limit %dx%d)\n",
1595                             w, h, max_width, max_height);
1596                 return -EINVAL;
1597         }
1598
1599         intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
1600         offset = intel_plane_compute_aligned_offset(&x, &y,
1601                                                     plane_state, uv_plane);
1602
1603         if (intel_fb_is_ccs_modifier(fb->modifier)) {
1604                 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
1605                 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1606                 u32 alignment = intel_surf_alignment(fb, uv_plane);
1607
1608                 if (offset > aux_offset)
1609                         offset = intel_plane_adjust_aligned_offset(&x, &y,
1610                                                                    plane_state,
1611                                                                    uv_plane,
1612                                                                    offset,
1613                                                                    aux_offset & ~(alignment - 1));
1614
1615                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1616                                                        offset, ccs_plane)) {
1617                         if (offset == 0)
1618                                 break;
1619
1620                         offset = intel_plane_adjust_aligned_offset(&x, &y,
1621                                                                    plane_state,
1622                                                                    uv_plane,
1623                                                                    offset, offset - alignment);
1624                 }
1625
1626                 if (x != plane_state->view.color_plane[ccs_plane].x ||
1627                     y != plane_state->view.color_plane[ccs_plane].y) {
1628                         drm_dbg_kms(&i915->drm,
1629                                     "Unable to find suitable display surface offset due to CCS\n");
1630                         return -EINVAL;
1631                 }
1632         }
1633
1634         if (DISPLAY_VER(i915) >= 13)
1635                 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
1636         else
1637                 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
1638
1639         plane_state->view.color_plane[uv_plane].offset = offset;
1640         plane_state->view.color_plane[uv_plane].x = x;
1641         plane_state->view.color_plane[uv_plane].y = y;
1642
1643         return 0;
1644 }
1645
1646 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
1647 {
1648         const struct drm_framebuffer *fb = plane_state->hw.fb;
1649         int src_x = plane_state->uapi.src.x1 >> 16;
1650         int src_y = plane_state->uapi.src.y1 >> 16;
1651         u32 offset;
1652         int ccs_plane;
1653
1654         for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
1655                 int main_hsub, main_vsub;
1656                 int hsub, vsub;
1657                 int x, y;
1658
1659                 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
1660                         continue;
1661
1662                 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
1663                                                skl_ccs_to_main_plane(fb, ccs_plane));
1664                 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1665
1666                 hsub *= main_hsub;
1667                 vsub *= main_vsub;
1668                 x = src_x / hsub;
1669                 y = src_y / vsub;
1670
1671                 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
1672
1673                 offset = intel_plane_compute_aligned_offset(&x, &y,
1674                                                             plane_state,
1675                                                             ccs_plane);
1676
1677                 plane_state->view.color_plane[ccs_plane].offset = offset;
1678                 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub;
1679                 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub;
1680         }
1681
1682         return 0;
1683 }
1684
1685 static int skl_check_plane_surface(struct intel_plane_state *plane_state)
1686 {
1687         const struct drm_framebuffer *fb = plane_state->hw.fb;
1688         int ret;
1689
1690         ret = intel_plane_compute_gtt(plane_state);
1691         if (ret)
1692                 return ret;
1693
1694         if (!plane_state->uapi.visible)
1695                 return 0;
1696
1697         /*
1698          * Handle the AUX surface first since the main surface setup depends on
1699          * it.
1700          */
1701         if (intel_fb_is_ccs_modifier(fb->modifier)) {
1702                 ret = skl_check_ccs_aux_surface(plane_state);
1703                 if (ret)
1704                         return ret;
1705         }
1706
1707         if (intel_format_info_is_yuv_semiplanar(fb->format,
1708                                                 fb->modifier)) {
1709                 ret = skl_check_nv12_aux_surface(plane_state);
1710                 if (ret)
1711                         return ret;
1712         }
1713
1714         ret = skl_check_main_surface(plane_state);
1715         if (ret)
1716                 return ret;
1717
1718         return 0;
1719 }
1720
1721 static bool skl_fb_scalable(const struct drm_framebuffer *fb)
1722 {
1723         if (!fb)
1724                 return false;
1725
1726         switch (fb->format->format) {
1727         case DRM_FORMAT_C8:
1728                 return false;
1729         case DRM_FORMAT_XRGB16161616F:
1730         case DRM_FORMAT_ARGB16161616F:
1731         case DRM_FORMAT_XBGR16161616F:
1732         case DRM_FORMAT_ABGR16161616F:
1733                 return DISPLAY_VER(to_i915(fb->dev)) >= 11;
1734         default:
1735                 return true;
1736         }
1737 }
1738
1739 static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj)
1740 {
1741         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1742
1743         return intel_pxp_key_check(&i915->gt.pxp, obj, false) == 0;
1744 }
1745
1746 static bool pxp_is_borked(struct drm_i915_gem_object *obj)
1747 {
1748         return i915_gem_object_is_protected(obj) && !bo_has_valid_encryption(obj);
1749 }
1750
1751 static int skl_plane_check(struct intel_crtc_state *crtc_state,
1752                            struct intel_plane_state *plane_state)
1753 {
1754         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1755         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1756         const struct drm_framebuffer *fb = plane_state->hw.fb;
1757         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
1758         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1759         int ret;
1760
1761         ret = skl_plane_check_fb(crtc_state, plane_state);
1762         if (ret)
1763                 return ret;
1764
1765         /* use scaler when colorkey is not required */
1766         if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
1767                 min_scale = 1;
1768                 max_scale = skl_plane_max_scale(dev_priv, fb);
1769         }
1770
1771         ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
1772                                                 min_scale, max_scale, true);
1773         if (ret)
1774                 return ret;
1775
1776         ret = skl_check_plane_surface(plane_state);
1777         if (ret)
1778                 return ret;
1779
1780         if (!plane_state->uapi.visible)
1781                 return 0;
1782
1783         ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1784         if (ret)
1785                 return ret;
1786
1787         ret = intel_plane_check_src_coordinates(plane_state);
1788         if (ret)
1789                 return ret;
1790
1791         ret = skl_plane_check_nv12_rotation(plane_state);
1792         if (ret)
1793                 return ret;
1794
1795         if (DISPLAY_VER(dev_priv) >= 11) {
1796                 plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb));
1797                 plane_state->force_black = pxp_is_borked(intel_fb_obj(fb));
1798         }
1799
1800         /* HW only has 8 bits pixel precision, disable plane if invisible */
1801         if (!(plane_state->hw.alpha >> 8))
1802                 plane_state->uapi.visible = false;
1803
1804         plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1805
1806         if (DISPLAY_VER(dev_priv) >= 10)
1807                 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1808                                                              plane_state);
1809
1810         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1811             icl_is_hdr_plane(dev_priv, plane->id))
1812                 /* Enable and use MPEG-2 chroma siting */
1813                 plane_state->cus_ctl = PLANE_CUS_ENABLE |
1814                         PLANE_CUS_HPHASE_0 |
1815                         PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
1816         else
1817                 plane_state->cus_ctl = 0;
1818
1819         return 0;
1820 }
1821
1822 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
1823                               enum pipe pipe, enum plane_id plane_id)
1824 {
1825         if (!HAS_FBC(dev_priv))
1826                 return false;
1827
1828         return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
1829 }
1830
1831 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
1832                                  enum pipe pipe, enum plane_id plane_id)
1833 {
1834         /* Display WA #0870: skl, bxt */
1835         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
1836                 return false;
1837
1838         if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
1839                 return false;
1840
1841         if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
1842                 return false;
1843
1844         return true;
1845 }
1846
1847 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
1848                                         enum pipe pipe, enum plane_id plane_id,
1849                                         int *num_formats)
1850 {
1851         if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
1852                 *num_formats = ARRAY_SIZE(skl_planar_formats);
1853                 return skl_planar_formats;
1854         } else {
1855                 *num_formats = ARRAY_SIZE(skl_plane_formats);
1856                 return skl_plane_formats;
1857         }
1858 }
1859
1860 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
1861                                         enum pipe pipe, enum plane_id plane_id,
1862                                         int *num_formats)
1863 {
1864         if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
1865                 *num_formats = ARRAY_SIZE(glk_planar_formats);
1866                 return glk_planar_formats;
1867         } else {
1868                 *num_formats = ARRAY_SIZE(skl_plane_formats);
1869                 return skl_plane_formats;
1870         }
1871 }
1872
1873 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
1874                                         enum pipe pipe, enum plane_id plane_id,
1875                                         int *num_formats)
1876 {
1877         if (icl_is_hdr_plane(dev_priv, plane_id)) {
1878                 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
1879                 return icl_hdr_plane_formats;
1880         } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
1881                 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
1882                 return icl_sdr_y_plane_formats;
1883         } else {
1884                 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
1885                 return icl_sdr_uv_plane_formats;
1886         }
1887 }
1888
1889 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1890                                            u32 format, u64 modifier)
1891 {
1892         struct intel_plane *plane = to_intel_plane(_plane);
1893
1894         if (!intel_fb_plane_supports_modifier(plane, modifier))
1895                 return false;
1896
1897         switch (format) {
1898         case DRM_FORMAT_XRGB8888:
1899         case DRM_FORMAT_XBGR8888:
1900         case DRM_FORMAT_ARGB8888:
1901         case DRM_FORMAT_ABGR8888:
1902                 if (intel_fb_is_ccs_modifier(modifier))
1903                         return true;
1904                 fallthrough;
1905         case DRM_FORMAT_RGB565:
1906         case DRM_FORMAT_XRGB2101010:
1907         case DRM_FORMAT_XBGR2101010:
1908         case DRM_FORMAT_ARGB2101010:
1909         case DRM_FORMAT_ABGR2101010:
1910         case DRM_FORMAT_YUYV:
1911         case DRM_FORMAT_YVYU:
1912         case DRM_FORMAT_UYVY:
1913         case DRM_FORMAT_VYUY:
1914         case DRM_FORMAT_NV12:
1915         case DRM_FORMAT_XYUV8888:
1916         case DRM_FORMAT_P010:
1917         case DRM_FORMAT_P012:
1918         case DRM_FORMAT_P016:
1919         case DRM_FORMAT_XVYU2101010:
1920                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1921                         return true;
1922                 fallthrough;
1923         case DRM_FORMAT_C8:
1924         case DRM_FORMAT_XBGR16161616F:
1925         case DRM_FORMAT_ABGR16161616F:
1926         case DRM_FORMAT_XRGB16161616F:
1927         case DRM_FORMAT_ARGB16161616F:
1928         case DRM_FORMAT_Y210:
1929         case DRM_FORMAT_Y212:
1930         case DRM_FORMAT_Y216:
1931         case DRM_FORMAT_XVYU12_16161616:
1932         case DRM_FORMAT_XVYU16161616:
1933                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1934                     modifier == I915_FORMAT_MOD_X_TILED ||
1935                     modifier == I915_FORMAT_MOD_Y_TILED)
1936                         return true;
1937                 fallthrough;
1938         default:
1939                 return false;
1940         }
1941 }
1942
1943 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
1944                                              u32 format, u64 modifier)
1945 {
1946         struct intel_plane *plane = to_intel_plane(_plane);
1947
1948         if (!intel_fb_plane_supports_modifier(plane, modifier))
1949                 return false;
1950
1951         switch (format) {
1952         case DRM_FORMAT_XRGB8888:
1953         case DRM_FORMAT_XBGR8888:
1954         case DRM_FORMAT_ARGB8888:
1955         case DRM_FORMAT_ABGR8888:
1956                 if (intel_fb_is_ccs_modifier(modifier))
1957                         return true;
1958                 fallthrough;
1959         case DRM_FORMAT_YUYV:
1960         case DRM_FORMAT_YVYU:
1961         case DRM_FORMAT_UYVY:
1962         case DRM_FORMAT_VYUY:
1963         case DRM_FORMAT_NV12:
1964         case DRM_FORMAT_XYUV8888:
1965         case DRM_FORMAT_P010:
1966         case DRM_FORMAT_P012:
1967         case DRM_FORMAT_P016:
1968                 if (intel_fb_is_mc_ccs_modifier(modifier))
1969                         return true;
1970                 fallthrough;
1971         case DRM_FORMAT_RGB565:
1972         case DRM_FORMAT_XRGB2101010:
1973         case DRM_FORMAT_XBGR2101010:
1974         case DRM_FORMAT_ARGB2101010:
1975         case DRM_FORMAT_ABGR2101010:
1976         case DRM_FORMAT_XVYU2101010:
1977         case DRM_FORMAT_C8:
1978         case DRM_FORMAT_XBGR16161616F:
1979         case DRM_FORMAT_ABGR16161616F:
1980         case DRM_FORMAT_XRGB16161616F:
1981         case DRM_FORMAT_ARGB16161616F:
1982         case DRM_FORMAT_Y210:
1983         case DRM_FORMAT_Y212:
1984         case DRM_FORMAT_Y216:
1985         case DRM_FORMAT_XVYU12_16161616:
1986         case DRM_FORMAT_XVYU16161616:
1987                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1988                     modifier == I915_FORMAT_MOD_X_TILED ||
1989                     modifier == I915_FORMAT_MOD_Y_TILED)
1990                         return true;
1991                 fallthrough;
1992         default:
1993                 return false;
1994         }
1995 }
1996
1997 static const struct drm_plane_funcs skl_plane_funcs = {
1998         .update_plane = drm_atomic_helper_update_plane,
1999         .disable_plane = drm_atomic_helper_disable_plane,
2000         .destroy = intel_plane_destroy,
2001         .atomic_duplicate_state = intel_plane_duplicate_state,
2002         .atomic_destroy_state = intel_plane_destroy_state,
2003         .format_mod_supported = skl_plane_format_mod_supported,
2004 };
2005
2006 static const struct drm_plane_funcs gen12_plane_funcs = {
2007         .update_plane = drm_atomic_helper_update_plane,
2008         .disable_plane = drm_atomic_helper_disable_plane,
2009         .destroy = intel_plane_destroy,
2010         .atomic_duplicate_state = intel_plane_duplicate_state,
2011         .atomic_destroy_state = intel_plane_destroy_state,
2012         .format_mod_supported = gen12_plane_format_mod_supported,
2013 };
2014
2015 static void
2016 skl_plane_enable_flip_done(struct intel_plane *plane)
2017 {
2018         struct drm_i915_private *i915 = to_i915(plane->base.dev);
2019         enum pipe pipe = plane->pipe;
2020
2021         spin_lock_irq(&i915->irq_lock);
2022         bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2023         spin_unlock_irq(&i915->irq_lock);
2024 }
2025
2026 static void
2027 skl_plane_disable_flip_done(struct intel_plane *plane)
2028 {
2029         struct drm_i915_private *i915 = to_i915(plane->base.dev);
2030         enum pipe pipe = plane->pipe;
2031
2032         spin_lock_irq(&i915->irq_lock);
2033         bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2034         spin_unlock_irq(&i915->irq_lock);
2035 }
2036
2037 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
2038                                  enum pipe pipe, enum plane_id plane_id)
2039 {
2040         /* Wa_22011186057 */
2041         if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2042                 return false;
2043
2044         if (DISPLAY_VER(i915) >= 11)
2045                 return true;
2046
2047         if (IS_GEMINILAKE(i915))
2048                 return pipe != PIPE_C;
2049
2050         return pipe != PIPE_C &&
2051                 (plane_id == PLANE_PRIMARY ||
2052                  plane_id == PLANE_SPRITE0);
2053 }
2054
2055 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
2056                                    enum plane_id plane_id)
2057 {
2058         if (DISPLAY_VER(i915) < 12)
2059                 return false;
2060
2061         /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
2062         if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
2063             IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
2064                 return false;
2065
2066         /* Wa_22011186057 */
2067         if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2068                 return false;
2069
2070         return plane_id < PLANE_SPRITE4;
2071 }
2072
2073 static u8 skl_get_plane_caps(struct drm_i915_private *i915,
2074                              enum pipe pipe, enum plane_id plane_id)
2075 {
2076         u8 caps = INTEL_PLANE_CAP_TILING_X;
2077
2078         if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915))
2079                 caps |= INTEL_PLANE_CAP_TILING_Y;
2080         if (DISPLAY_VER(i915) < 12)
2081                 caps |= INTEL_PLANE_CAP_TILING_Yf;
2082
2083         if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
2084                 caps |= INTEL_PLANE_CAP_CCS_RC;
2085                 if (DISPLAY_VER(i915) >= 12)
2086                         caps |= INTEL_PLANE_CAP_CCS_RC_CC;
2087         }
2088
2089         if (gen12_plane_has_mc_ccs(i915, plane_id))
2090                 caps |= INTEL_PLANE_CAP_CCS_MC;
2091
2092         return caps;
2093 }
2094
2095 struct intel_plane *
2096 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2097                            enum pipe pipe, enum plane_id plane_id)
2098 {
2099         const struct drm_plane_funcs *plane_funcs;
2100         struct intel_plane *plane;
2101         enum drm_plane_type plane_type;
2102         unsigned int supported_rotations;
2103         unsigned int supported_csc;
2104         const u64 *modifiers;
2105         const u32 *formats;
2106         int num_formats;
2107         int ret;
2108
2109         plane = intel_plane_alloc();
2110         if (IS_ERR(plane))
2111                 return plane;
2112
2113         plane->pipe = pipe;
2114         plane->id = plane_id;
2115         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2116
2117         if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
2118                 plane->fbc = &dev_priv->fbc;
2119         if (plane->fbc)
2120                 plane->fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
2121
2122         if (DISPLAY_VER(dev_priv) >= 11) {
2123                 plane->min_width = icl_plane_min_width;
2124                 if (icl_is_hdr_plane(dev_priv, plane_id))
2125                         plane->max_width = icl_hdr_plane_max_width;
2126                 else
2127                         plane->max_width = icl_sdr_plane_max_width;
2128                 plane->max_height = icl_plane_max_height;
2129                 plane->min_cdclk = icl_plane_min_cdclk;
2130         } else if (DISPLAY_VER(dev_priv) >= 10) {
2131                 plane->max_width = glk_plane_max_width;
2132                 plane->max_height = skl_plane_max_height;
2133                 plane->min_cdclk = glk_plane_min_cdclk;
2134         } else {
2135                 plane->max_width = skl_plane_max_width;
2136                 plane->max_height = skl_plane_max_height;
2137                 plane->min_cdclk = skl_plane_min_cdclk;
2138         }
2139
2140         plane->max_stride = skl_plane_max_stride;
2141         plane->update_noarm = skl_plane_update_noarm;
2142         plane->update_arm = skl_plane_update_arm;
2143         plane->disable_arm = skl_plane_disable_arm;
2144         plane->get_hw_state = skl_plane_get_hw_state;
2145         plane->check_plane = skl_plane_check;
2146
2147         if (plane_id == PLANE_PRIMARY) {
2148                 plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv,
2149                                                                    9, 10);
2150                 plane->async_flip = skl_plane_async_flip;
2151                 plane->enable_flip_done = skl_plane_enable_flip_done;
2152                 plane->disable_flip_done = skl_plane_disable_flip_done;
2153         }
2154
2155         if (DISPLAY_VER(dev_priv) >= 11)
2156                 formats = icl_get_plane_formats(dev_priv, pipe,
2157                                                 plane_id, &num_formats);
2158         else if (DISPLAY_VER(dev_priv) >= 10)
2159                 formats = glk_get_plane_formats(dev_priv, pipe,
2160                                                 plane_id, &num_formats);
2161         else
2162                 formats = skl_get_plane_formats(dev_priv, pipe,
2163                                                 plane_id, &num_formats);
2164
2165         if (DISPLAY_VER(dev_priv) >= 12)
2166                 plane_funcs = &gen12_plane_funcs;
2167         else
2168                 plane_funcs = &skl_plane_funcs;
2169
2170         if (plane_id == PLANE_PRIMARY)
2171                 plane_type = DRM_PLANE_TYPE_PRIMARY;
2172         else
2173                 plane_type = DRM_PLANE_TYPE_OVERLAY;
2174
2175         modifiers = intel_fb_plane_get_modifiers(dev_priv,
2176                                                  skl_get_plane_caps(dev_priv, pipe, plane_id));
2177
2178         ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2179                                        0, plane_funcs,
2180                                        formats, num_formats, modifiers,
2181                                        plane_type,
2182                                        "plane %d%c", plane_id + 1,
2183                                        pipe_name(pipe));
2184
2185         kfree(modifiers);
2186
2187         if (ret)
2188                 goto fail;
2189
2190         if (DISPLAY_VER(dev_priv) >= 13)
2191                 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
2192         else
2193                 supported_rotations =
2194                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2195                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2196
2197         if (DISPLAY_VER(dev_priv) >= 11)
2198                 supported_rotations |= DRM_MODE_REFLECT_X;
2199
2200         drm_plane_create_rotation_property(&plane->base,
2201                                            DRM_MODE_ROTATE_0,
2202                                            supported_rotations);
2203
2204         supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
2205
2206         if (DISPLAY_VER(dev_priv) >= 10)
2207                 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
2208
2209         drm_plane_create_color_properties(&plane->base,
2210                                           supported_csc,
2211                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2212                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2213                                           DRM_COLOR_YCBCR_BT709,
2214                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
2215
2216         drm_plane_create_alpha_property(&plane->base);
2217         drm_plane_create_blend_mode_property(&plane->base,
2218                                              BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2219                                              BIT(DRM_MODE_BLEND_PREMULTI) |
2220                                              BIT(DRM_MODE_BLEND_COVERAGE));
2221
2222         drm_plane_create_zpos_immutable_property(&plane->base, plane_id);
2223
2224         if (DISPLAY_VER(dev_priv) >= 12)
2225                 drm_plane_enable_fb_damage_clips(&plane->base);
2226
2227         if (DISPLAY_VER(dev_priv) >= 11)
2228                 drm_plane_create_scaling_filter_property(&plane->base,
2229                                                 BIT(DRM_SCALING_FILTER_DEFAULT) |
2230                                                 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
2231
2232         intel_plane_helper_add(plane);
2233
2234         return plane;
2235
2236 fail:
2237         intel_plane_free(plane);
2238
2239         return ERR_PTR(ret);
2240 }
2241
2242 void
2243 skl_get_initial_plane_config(struct intel_crtc *crtc,
2244                              struct intel_initial_plane_config *plane_config)
2245 {
2246         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
2247         struct drm_device *dev = crtc->base.dev;
2248         struct drm_i915_private *dev_priv = to_i915(dev);
2249         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2250         enum plane_id plane_id = plane->id;
2251         enum pipe pipe;
2252         u32 val, base, offset, stride_mult, tiling, alpha;
2253         int fourcc, pixel_format;
2254         unsigned int aligned_height;
2255         struct drm_framebuffer *fb;
2256         struct intel_framebuffer *intel_fb;
2257
2258         if (!plane->get_hw_state(plane, &pipe))
2259                 return;
2260
2261         drm_WARN_ON(dev, pipe != crtc->pipe);
2262
2263         if (crtc_state->bigjoiner) {
2264                 drm_dbg_kms(&dev_priv->drm,
2265                             "Unsupported bigjoiner configuration for initial FB\n");
2266                 return;
2267         }
2268
2269         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2270         if (!intel_fb) {
2271                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
2272                 return;
2273         }
2274
2275         fb = &intel_fb->base;
2276
2277         fb->dev = dev;
2278
2279         val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
2280
2281         if (DISPLAY_VER(dev_priv) >= 11)
2282                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
2283         else
2284                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
2285
2286         if (DISPLAY_VER(dev_priv) >= 10) {
2287                 alpha = intel_de_read(dev_priv,
2288                                       PLANE_COLOR_CTL(pipe, plane_id));
2289                 alpha &= PLANE_COLOR_ALPHA_MASK;
2290         } else {
2291                 alpha = val & PLANE_CTL_ALPHA_MASK;
2292         }
2293
2294         fourcc = skl_format_to_fourcc(pixel_format,
2295                                       val & PLANE_CTL_ORDER_RGBX, alpha);
2296         fb->format = drm_format_info(fourcc);
2297
2298         tiling = val & PLANE_CTL_TILED_MASK;
2299         switch (tiling) {
2300         case PLANE_CTL_TILED_LINEAR:
2301                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
2302                 break;
2303         case PLANE_CTL_TILED_X:
2304                 plane_config->tiling = I915_TILING_X;
2305                 fb->modifier = I915_FORMAT_MOD_X_TILED;
2306                 break;
2307         case PLANE_CTL_TILED_Y:
2308                 plane_config->tiling = I915_TILING_Y;
2309                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2310                         fb->modifier = DISPLAY_VER(dev_priv) >= 12 ?
2311                                 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
2312                                 I915_FORMAT_MOD_Y_TILED_CCS;
2313                 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2314                         fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2315                 else
2316                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
2317                 break;
2318         case PLANE_CTL_TILED_YF:
2319                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2320                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
2321                 else
2322                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
2323                 break;
2324         default:
2325                 MISSING_CASE(tiling);
2326                 goto error;
2327         }
2328
2329         /*
2330          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
2331          * while i915 HW rotation is clockwise, thats why this swapping.
2332          */
2333         switch (val & PLANE_CTL_ROTATE_MASK) {
2334         case PLANE_CTL_ROTATE_0:
2335                 plane_config->rotation = DRM_MODE_ROTATE_0;
2336                 break;
2337         case PLANE_CTL_ROTATE_90:
2338                 plane_config->rotation = DRM_MODE_ROTATE_270;
2339                 break;
2340         case PLANE_CTL_ROTATE_180:
2341                 plane_config->rotation = DRM_MODE_ROTATE_180;
2342                 break;
2343         case PLANE_CTL_ROTATE_270:
2344                 plane_config->rotation = DRM_MODE_ROTATE_90;
2345                 break;
2346         }
2347
2348         if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
2349                 plane_config->rotation |= DRM_MODE_REFLECT_X;
2350
2351         /* 90/270 degree rotation would require extra work */
2352         if (drm_rotation_90_or_270(plane_config->rotation))
2353                 goto error;
2354
2355         base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
2356         plane_config->base = base;
2357
2358         offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
2359
2360         val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
2361         fb->height = ((val >> 16) & 0xffff) + 1;
2362         fb->width = ((val >> 0) & 0xffff) + 1;
2363
2364         val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
2365         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
2366
2367         if (DISPLAY_VER(dev_priv) >= 13)
2368                 fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
2369         else
2370                 fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
2371
2372         aligned_height = intel_fb_align_height(fb, 0, fb->height);
2373
2374         plane_config->size = fb->pitches[0] * aligned_height;
2375
2376         drm_dbg_kms(&dev_priv->drm,
2377                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
2378                     crtc->base.name, plane->base.name, fb->width, fb->height,
2379                     fb->format->cpp[0] * 8, base, fb->pitches[0],
2380                     plane_config->size);
2381
2382         plane_config->fb = intel_fb;
2383         return;
2384
2385 error:
2386         kfree(intel_fb);
2387 }