2 * Copyright © 2006-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Eric Anholt <eric@anholt.net>
29 * This information is private to VBT parsing in intel_bios.c.
31 * Please do NOT include anywhere else.
33 #ifndef _INTEL_BIOS_PRIVATE
34 #error "intel_vbt_defs.h is private to intel_bios.c"
37 #ifndef _INTEL_VBT_DEFS_H_
38 #define _INTEL_VBT_DEFS_H_
40 #include "intel_bios.h"
43 * struct vbt_header - VBT Header structure
44 * @signature: VBT signature, always starts with "$VBT"
45 * @version: Version of this structure
46 * @header_size: Size of this structure
47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks)
48 * @vbt_checksum: Checksum
49 * @reserved0: Reserved
50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT
51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT
65 * struct bdb_header - BDB Header structure
66 * @signature: BDB signature "BIOS_DATA_BLOCK"
67 * @version: Version of the data block definitions
68 * @header_size: Size of this structure
69 * @bdb_size: Size of BDB (BDB Header and data blocks)
79 * There are several types of BIOS data blocks (BDBs), each block has
80 * an ID and size in the first 3 bytes (ID in first, size in next 2).
81 * Known types are listed below.
84 BDB_GENERAL_FEATURES = 1,
85 BDB_GENERAL_DEFINITIONS = 2,
86 BDB_OLD_TOGGLE_LIST = 3,
87 BDB_MODE_SUPPORT_LIST = 4,
88 BDB_GENERIC_MODE_TABLE = 5,
89 BDB_EXT_MMIO_REGS = 6,
93 BDB_MODE_REMOVAL_TABLE = 10,
94 BDB_CHILD_DEVICE_TABLE = 11,
95 BDB_DRIVER_FEATURES = 12,
96 BDB_DRIVER_PERSISTENCE = 13,
97 BDB_EXT_TABLE_PTRS = 14,
98 BDB_DOT_CLOCK_OVERRIDE = 15,
99 BDB_DISPLAY_SELECT = 16,
100 BDB_DRIVER_ROTATION = 18,
101 BDB_DISPLAY_REMOVE = 19,
103 BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */
104 BDB_SDVO_LVDS_OPTIONS = 22,
105 BDB_SDVO_PANEL_DTDS = 23,
106 BDB_SDVO_LVDS_PNP_IDS = 24,
107 BDB_SDVO_LVDS_POWER_SEQ = 25,
110 BDB_LVDS_OPTIONS = 40,
111 BDB_LVDS_LFP_DATA_PTRS = 41,
112 BDB_LVDS_LFP_DATA = 42,
113 BDB_LVDS_BACKLIGHT = 43,
115 BDB_MIPI_CONFIG = 52,
116 BDB_MIPI_SEQUENCE = 53,
117 BDB_COMPRESSION_PARAMETERS = 56,
118 BDB_GENERIC_DTD = 58,
119 BDB_SKIP = 254, /* VBIOS private block, ignore */
123 * Block 1 - General Bit Definitions
126 struct bdb_general_features {
135 u8 download_ext_vbt:1;
138 u8 enable_lfp_on_override:1;
139 u8 disable_ssc_ddt:1;
140 u8 underscan_vga_timings:1;
141 u8 display_clock_mode:1;
142 u8 vbios_hotplug_support:1;
145 u8 disable_smooth_vision:1;
147 u8 rotate_180:1; /* 181 */
148 u8 fdi_rx_polarity_inverted:1;
149 u8 vbios_extended_mode:1; /* 160 */
150 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */
151 u8 panel_best_fit_timing:1; /* 160 */
152 u8 ignore_strap_state:1; /* 160 */
155 u8 legacy_monitor_detect;
158 u8 int_crt_support:1;
160 u8 int_efp_support:1;
161 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */
162 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
163 u8 dp_ssc_dongle_supported:1;
164 u8 rsvd11:2; /* finish byte */
168 * Block 2 - General Bytes Definition
172 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
173 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
174 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
175 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
178 #define DEVICE_TYPE_NONE 0x00
179 #define DEVICE_TYPE_CRT 0x01
180 #define DEVICE_TYPE_TV 0x09
181 #define DEVICE_TYPE_EFP 0x12
182 #define DEVICE_TYPE_LFP 0x22
184 #define DEVICE_TYPE_CRT_DPMS 0x6001
185 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
186 #define DEVICE_TYPE_TV_COMPOSITE 0x0209
187 #define DEVICE_TYPE_TV_MACROVISION 0x0289
188 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
189 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
190 #define DEVICE_TYPE_TV_SCART 0x0209
191 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
192 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
193 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
194 #define DEVICE_TYPE_EFP_DVI_I 0x6053
195 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
196 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
197 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
198 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
199 #define DEVICE_TYPE_LFP_PANELLINK 0x5012
200 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
201 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
202 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
203 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
205 /* Add the device class for LFP, TV, HDMI */
206 #define DEVICE_TYPE_INT_LFP 0x1022
207 #define DEVICE_TYPE_INT_TV 0x1009
208 #define DEVICE_TYPE_HDMI 0x60D2
209 #define DEVICE_TYPE_DP 0x68C6
210 #define DEVICE_TYPE_DP_DUAL_MODE 0x60D6
211 #define DEVICE_TYPE_eDP 0x78C6
213 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15)
214 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14)
215 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13)
216 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
217 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11)
218 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10)
219 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9)
220 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8)
221 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6)
222 #define DEVICE_TYPE_LVDS_SIGNALING (1 << 5)
223 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
224 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3)
225 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
226 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1)
227 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0)
230 * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
231 * system, the other bits may or may not be set for eDP outputs.
233 #define DEVICE_TYPE_eDP_BITS \
234 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
235 DEVICE_TYPE_MIPI_OUTPUT | \
236 DEVICE_TYPE_COMPOSITE_OUTPUT | \
237 DEVICE_TYPE_DUAL_CHANNEL | \
238 DEVICE_TYPE_LVDS_SIGNALING | \
239 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
240 DEVICE_TYPE_VIDEO_SIGNALING | \
241 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
242 DEVICE_TYPE_ANALOG_OUTPUT)
244 #define DEVICE_TYPE_DP_DUAL_MODE_BITS \
245 (DEVICE_TYPE_INTERNAL_CONNECTOR | \
246 DEVICE_TYPE_MIPI_OUTPUT | \
247 DEVICE_TYPE_COMPOSITE_OUTPUT | \
248 DEVICE_TYPE_LVDS_SIGNALING | \
249 DEVICE_TYPE_TMDS_DVI_SIGNALING | \
250 DEVICE_TYPE_VIDEO_SIGNALING | \
251 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
252 DEVICE_TYPE_DIGITAL_OUTPUT | \
253 DEVICE_TYPE_ANALOG_OUTPUT)
255 #define DEVICE_CFG_NONE 0x00
256 #define DEVICE_CFG_12BIT_DVOB 0x01
257 #define DEVICE_CFG_12BIT_DVOC 0x02
258 #define DEVICE_CFG_24BIT_DVOBC 0x09
259 #define DEVICE_CFG_24BIT_DVOCB 0x0a
260 #define DEVICE_CFG_DUAL_DVOB 0x11
261 #define DEVICE_CFG_DUAL_DVOC 0x12
262 #define DEVICE_CFG_DUAL_DVOBC 0x13
263 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
264 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
266 #define DEVICE_WIRE_NONE 0x00
267 #define DEVICE_WIRE_DVOB 0x01
268 #define DEVICE_WIRE_DVOC 0x02
269 #define DEVICE_WIRE_DVOBC 0x03
270 #define DEVICE_WIRE_DVOBB 0x05
271 #define DEVICE_WIRE_DVOCC 0x06
272 #define DEVICE_WIRE_DVOB_MASTER 0x0d
273 #define DEVICE_WIRE_DVOC_MASTER 0x0e
275 /* dvo_port pre BDB 155 */
276 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
277 #define DEVICE_PORT_DVOB 0x01
278 #define DEVICE_PORT_DVOC 0x02
280 /* dvo_port BDB 155+ */
281 #define DVO_PORT_HDMIA 0
282 #define DVO_PORT_HDMIB 1
283 #define DVO_PORT_HDMIC 2
284 #define DVO_PORT_HDMID 3
285 #define DVO_PORT_LVDS 4
286 #define DVO_PORT_TV 5
287 #define DVO_PORT_CRT 6
288 #define DVO_PORT_DPB 7
289 #define DVO_PORT_DPC 8
290 #define DVO_PORT_DPD 9
291 #define DVO_PORT_DPA 10
292 #define DVO_PORT_DPE 11 /* 193 */
293 #define DVO_PORT_HDMIE 12 /* 193 */
294 #define DVO_PORT_DPF 13 /* N/A */
295 #define DVO_PORT_HDMIF 14 /* N/A */
296 #define DVO_PORT_DPG 15 /* 217 */
297 #define DVO_PORT_HDMIG 16 /* 217 */
298 #define DVO_PORT_DPH 17 /* 217 */
299 #define DVO_PORT_HDMIH 18 /* 217 */
300 #define DVO_PORT_DPI 19 /* 217 */
301 #define DVO_PORT_HDMII 20 /* 217 */
302 #define DVO_PORT_MIPIA 21 /* 171 */
303 #define DVO_PORT_MIPIB 22 /* 171 */
304 #define DVO_PORT_MIPIC 23 /* 171 */
305 #define DVO_PORT_MIPID 24 /* 171 */
307 #define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */
308 #define HDMI_MAX_DATA_RATE_297 1 /* 204 */
309 #define HDMI_MAX_DATA_RATE_165 2 /* 204 */
311 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33
313 /* DDC Bus DDI Type 155+ */
319 ICL_DDC_BUS_DDI_A = 0x1,
322 ICL_DDC_BUS_PORT_1 = 0x4,
330 #define DP_AUX_A 0x40
331 #define DP_AUX_B 0x10
332 #define DP_AUX_C 0x20
333 #define DP_AUX_D 0x30
334 #define DP_AUX_E 0x50
335 #define DP_AUX_F 0x60
336 #define DP_AUX_G 0x70
337 #define DP_AUX_H 0x80
338 #define DP_AUX_I 0x90
340 #define VBT_DP_MAX_LINK_RATE_HBR3 0
341 #define VBT_DP_MAX_LINK_RATE_HBR2 1
342 #define VBT_DP_MAX_LINK_RATE_HBR 2
343 #define VBT_DP_MAX_LINK_RATE_LBR 3
346 * The child device config, aka the display device data structure, provides a
347 * description of a port and its configuration on the platform.
349 * The child device config size has been increased, and fields have been added
350 * and their meaning has changed over time. Care must be taken when accessing
351 * basically any of the fields to ensure the correct interpretation for the BDB
352 * version in question.
354 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
355 * space for the full structure below, and initialize the tail not actually
356 * present in VBT to zeros. Accessing those fields is fine, as long as the
357 * default zero is taken into account, again according to the BDB version.
359 * BDB versions 155 and below are considered legacy, and version 155 seems to be
360 * a baseline for some of the VBT documentation. When adding new fields, please
361 * include the BDB version when the field was added, if it's above that.
363 struct child_device_config {
365 u16 device_type; /* See DEVICE_TYPE_* above */
368 u8 device_id[10]; /* ascii string */
371 u8 dp_onboard_redriver; /* 158 */
372 u8 dp_ondock_redriver; /* 158 */
373 u8 hdmi_level_shifter_value:5; /* 169 */
374 u8 hdmi_max_data_rate:3; /* 204 */
375 u16 dtd_buf_ptr; /* 161 */
376 u8 edidless_efp:1; /* 161 */
377 u8 compression_enable:1; /* 198 */
378 u8 compression_method_cps:1; /* 198 */
379 u8 ganged_edp:1; /* 202 */
381 u8 compression_structure_index:4; /* 198 */
383 u8 slave_port; /* 202 */
389 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
394 u8 dvo_cfg; /* See DEVICE_CFG_* above */
404 u8 efp_routed:1; /* 158 */
405 u8 lane_reversal:1; /* 184 */
406 u8 lspcon:1; /* 192 */
407 u8 iboost:1; /* 196 */
408 u8 hpd_invert:1; /* 196 */
409 u8 use_vbt_vswing:1; /* 218 */
411 u8 hdmi_support:1; /* 158 */
412 u8 dp_support:1; /* 158 */
413 u8 tmds_support:1; /* 158 */
414 u8 support_reserved:5;
421 u8 sdvo_stall:1; /* 158 */
423 u8 integrated_encoder:1;
424 u8 capabilities_reserved:2;
425 u8 dvo_wiring; /* See DEVICE_WIRE_* above */
429 u8 mipi_bridge_type; /* 171 */
434 u8 dp_usb_type_c:1; /* 195 */
436 u8 flags2_reserved:2; /* 195 */
437 u8 dp_port_trace_length:4; /* 209 */
438 u8 dp_gpio_index; /* 195 */
439 u16 dp_gpio_pin_num; /* 195 */
440 u8 dp_iboost_level:4; /* 196 */
441 u8 hdmi_iboost_level:4; /* 196 */
442 u8 dp_max_link_rate:2; /* 216 CNL+ */
443 u8 dp_max_link_rate_reserved:6; /* 216 */
446 struct bdb_general_definitions {
448 u8 crt_ddc_gmbus_pin;
452 u8 skip_boot_crt_detect:1;
454 u8 rsvd1:5; /* finish byte */
456 /* boot device bits */
462 * If TV is present, it'll be at devices[0].
463 * LVDS will be next, either devices[0] or [1], if present.
464 * On some platforms the number of device is 6. But could be as few as
465 * 4 if both TV and LVDS are missing.
466 * And the device num is related with the size of general definition
467 * block. It is obtained by using the following formula:
468 * number = (block_size - sizeof(bdb_general_definitions))/
469 * defs->child_dev_size;
475 * Block 9 - SRD Feature Block
481 u8 require_aux_to_wakeup:1;
482 u8 feature_bits_rsvd:6;
487 u8 wait_times_rsvd:1;
489 /* TP wake up time in multiple of 100 */
491 u16 tp2_tp3_wakeup_time;
495 struct psr_table psr_table[16];
497 /* PSR2 TP2/TP3 wakeup time for 16 panels */
498 u32 psr2_tp2_tp3_wakeup_time;
502 * Block 12 - Driver Features Data Block
505 #define BDB_DRIVER_FEATURE_NO_LVDS 0
506 #define BDB_DRIVER_FEATURE_INT_LVDS 1
507 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2
508 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3
510 struct bdb_driver_features {
511 u8 boot_dev_algorithm:1;
512 u8 block_display_switch:1;
513 u8 allow_display_switch:1;
517 u8 sprite_in_clone:1;
523 u8 boot_mode_refresh;
525 u16 enable_lfp_primary:1;
526 u16 selective_mode_pruning:1;
527 u16 dual_frequency:1;
528 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
529 u16 nt_clone_support:1;
530 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
531 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
532 u16 cui_aspect_scaling:1;
533 u16 preserve_aspect_ratio:1;
534 u16 sdvo_device_power_down:1;
542 u16 legacy_crt_max_x;
543 u16 legacy_crt_max_y;
544 u8 legacy_crt_max_refresh;
547 u8 custom_vbt_version;
548 /* Driver features data block */
552 u16 bltclt_enabled:1;
561 u16 pc_feature_valid:1;
565 * Block 22 - SDVO LVDS General Options
568 struct bdb_sdvo_lvds_options {
570 u8 h40_set_panel_type;
575 u8 sclalarcoeff_tab_row_num;
576 u8 sclalarcoeff_tab_row_size;
578 u8 panel_misc_bits_1;
579 u8 panel_misc_bits_2;
580 u8 panel_misc_bits_3;
581 u8 panel_misc_bits_4;
585 * Block 23 - SDVO LVDS Panel DTDs
588 struct lvds_dvo_timing {
589 u16 clock; /**< In 10khz */
599 u8 hsync_pulse_width_lo;
600 u8 vsync_pulse_width_lo:4;
602 u8 vsync_pulse_width_hi:2;
604 u8 hsync_pulse_width_hi:2;
619 struct bdb_sdvo_panel_dtds {
620 struct lvds_dvo_timing dtds[4];
624 * Block 27 - eDP VBT Block
630 #define EDP_RATE_1_62 0
631 #define EDP_RATE_2_7 1
635 #define EDP_PREEMPHASIS_NONE 0
636 #define EDP_PREEMPHASIS_3_5dB 1
637 #define EDP_PREEMPHASIS_6dB 2
638 #define EDP_PREEMPHASIS_9_5dB 3
639 #define EDP_VSWING_0_4V 0
640 #define EDP_VSWING_0_6V 1
641 #define EDP_VSWING_0_8V 2
642 #define EDP_VSWING_1_2V 3
645 struct edp_fast_link_params {
652 struct edp_pwm_delays {
653 u16 pwm_on_to_backlight_enable;
654 u16 backlight_disable_to_pwm_off;
657 struct edp_full_link_params {
663 struct edp_power_seq power_seqs[16];
665 struct edp_fast_link_params fast_link_params[16];
666 u32 sdrrs_msa_timing_delay;
668 /* ith bit indicates enabled/disabled for (i+1)th panel */
669 u16 edp_s3d_feature; /* 162 */
670 u16 edp_t3_optimization; /* 165 */
671 u64 edp_vswing_preemph; /* 173 */
672 u16 fast_link_training; /* 182 */
673 u16 dpcd_600h_write_required; /* 185 */
674 struct edp_pwm_delays pwm_delays[16]; /* 186 */
675 u16 full_link_params_provided; /* 199 */
676 struct edp_full_link_params full_link_params[16]; /* 199 */
680 * Block 40 - LFP Data Block
683 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
684 #define MODE_MASK 0x3
686 struct bdb_lvds_options {
688 u8 panel_type2; /* 212 */
689 /* LVDS capabilities, stored in a dword */
691 u8 pfit_text_mode_enhanced:1;
692 u8 pfit_gfx_mode_enhanced:1;
693 u8 pfit_ratio_auto:1;
698 /* LVDS Panel channel bits stored here */
699 u32 lvds_panel_channel_bits;
700 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
704 /* Panel color depth defined here */
705 u16 panel_color_depth;
706 /* LVDS panel type bits stored here */
707 u32 dps_panel_type_bits;
708 /* LVDS backlight control type bits stored here */
709 u32 blt_control_type_bits;
711 u16 lcdvcc_s0_enable; /* 200 */
712 u32 rotation; /* 228 */
716 * Block 41 - LFP Data Table Pointers
719 /* LFP pointer table contains entries to the struct below */
720 struct lvds_lfp_data_ptr {
721 u16 fp_timing_offset; /* offsets are from start of bdb */
723 u16 dvo_timing_offset;
725 u16 panel_pnp_id_offset;
729 struct bdb_lvds_lfp_data_ptrs {
730 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
731 struct lvds_lfp_data_ptr ptr[16];
735 * Block 42 - LFP Data Tables
738 /* LFP data has 3 blocks per entry */
739 struct lvds_fp_timing {
749 u32 pp_cycle_reg_val;
763 struct lvds_lfp_data_entry {
764 struct lvds_fp_timing fp_timing;
765 struct lvds_dvo_timing dvo_timing;
766 struct lvds_pnp_id pnp_id;
769 struct bdb_lvds_lfp_data {
770 struct lvds_lfp_data_entry data[16];
774 * Block 43 - LFP Backlight Control Data Block
777 #define BDB_BACKLIGHT_TYPE_NONE 0
778 #define BDB_BACKLIGHT_TYPE_PWM 2
780 struct lfp_backlight_data_entry {
790 struct lfp_backlight_control_method {
795 struct bdb_lfp_backlight_data {
797 struct lfp_backlight_data_entry data[16];
799 struct lfp_backlight_control_method backlight_control[16];
803 * Block 44 - LFP Power Conservation Features Block
806 struct als_data_entry {
807 u16 backlight_adjust;
811 struct agressiveness_profile_entry {
812 u8 dpst_agressiveness : 4;
813 u8 lace_agressiveness : 4;
816 struct bdb_lfp_power {
818 struct als_data_entry als[5];
819 u8 lace_aggressiveness_profile;
827 u16 lace_enabled_status;
828 struct agressiveness_profile_entry aggressivenes[16];
833 * Block 52 - MIPI Configuration Block
836 #define MAX_MIPI_CONFIGURATIONS 6
838 struct bdb_mipi_config {
839 struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
840 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
844 * Block 53 - MIPI Sequence Block
847 struct bdb_mipi_sequence {
849 u8 data[]; /* up to 6 variable length blocks */
853 * Block 56 - Compression Parameters
856 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0
857 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1
858 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2
859 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3
861 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */
862 #define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2)
864 struct dsc_compression_parameters_entry {
868 u8 rc_buffer_block_size:2;
872 * Buffer size in bytes:
874 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes
879 u8 line_buffer_depth:4;
883 u8 block_prediction_enable:1;
886 u8 max_bpp; /* mapping */
888 /* Color depth capabilities */
898 struct bdb_compression_parameters {
900 struct dsc_compression_parameters_entry data[16];
904 * Block 58 - Generic DTD Block
907 struct generic_dtd_entry {
922 u8 vsync_positive_polarity:1;
923 u8 hsync_positive_polarity:1;
928 struct bdb_generic_dtd {
930 struct generic_dtd_entry dtd[]; /* up to 24 DTD's */
933 #endif /* _INTEL_VBT_DEFS_H_ */