2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_atomic.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_color_mgmt.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_fourcc.h>
38 #include <drm/drm_plane_helper.h>
39 #include <drm/drm_rect.h>
40 #include <drm/i915_drm.h>
43 #include "i915_trace.h"
44 #include "intel_atomic_plane.h"
45 #include "intel_display_types.h"
46 #include "intel_frontbuffer.h"
48 #include "intel_psr.h"
49 #include "intel_sprite.h"
51 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
55 if (!adjusted_mode->crtc_htotal)
58 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
59 1000 * adjusted_mode->crtc_htotal);
62 /* FIXME: We should instead only take spinlocks once for the entire update
63 * instead of once per mmio. */
64 #if IS_ENABLED(CONFIG_PROVE_LOCKING)
65 #define VBLANK_EVASION_TIME_US 250
67 #define VBLANK_EVASION_TIME_US 100
71 * intel_pipe_update_start() - start update of a set of display registers
72 * @new_crtc_state: the new crtc state
74 * Mark the start of an update to pipe registers that should be updated
75 * atomically regarding vblank. If the next vblank will happens within
76 * the next 100 us, this function waits until the vblank passes.
78 * After a successful call to this function, interrupts will be disabled
79 * until a subsequent call to intel_pipe_update_end(). That is done to
80 * avoid random delays.
82 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
84 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
85 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
86 const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
87 long timeout = msecs_to_jiffies_timeout(1);
88 int scanline, min, max, vblank_start;
89 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
90 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
91 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
95 vblank_start = adjusted_mode->crtc_vblank_start;
96 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
97 vblank_start = DIV_ROUND_UP(vblank_start, 2);
99 /* FIXME needs to be calibrated sensibly */
100 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
101 VBLANK_EVASION_TIME_US);
102 max = vblank_start - 1;
104 if (min <= 0 || max <= 0)
107 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
111 * Wait for psr to idle out after enabling the VBL interrupts
112 * VBL interrupts will start the PSR exit and prevent a PSR
115 if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
116 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
121 crtc->debug.min_vbl = min;
122 crtc->debug.max_vbl = max;
123 trace_i915_pipe_update_start(crtc);
127 * prepare_to_wait() has a memory barrier, which guarantees
128 * other CPUs can see the task state update by the time we
131 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
133 scanline = intel_get_crtc_scanline(crtc);
134 if (scanline < min || scanline > max)
138 DRM_ERROR("Potential atomic update failure on pipe %c\n",
139 pipe_name(crtc->pipe));
145 timeout = schedule_timeout(timeout);
150 finish_wait(wq, &wait);
152 drm_crtc_vblank_put(&crtc->base);
155 * On VLV/CHV DSI the scanline counter would appear to
156 * increment approx. 1/3 of a scanline before start of vblank.
157 * The registers still get latched at start of vblank however.
158 * This means we must not write any registers on the first
159 * line of vblank (since not the whole line is actually in
160 * vblank). And unfortunately we can't use the interrupt to
161 * wait here since it will fire too soon. We could use the
162 * frame start interrupt instead since it will fire after the
163 * critical scanline, but that would require more changes
164 * in the interrupt code. So for now we'll just do the nasty
165 * thing and poll for the bad scanline to pass us by.
167 * FIXME figure out if BXT+ DSI suffers from this as well
169 while (need_vlv_dsi_wa && scanline == vblank_start)
170 scanline = intel_get_crtc_scanline(crtc);
172 crtc->debug.scanline_start = scanline;
173 crtc->debug.start_vbl_time = ktime_get();
174 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
176 trace_i915_pipe_update_vblank_evaded(crtc);
184 * intel_pipe_update_end() - end update of a set of display registers
185 * @new_crtc_state: the new crtc state
187 * Mark the end of an update started with intel_pipe_update_start(). This
188 * re-enables interrupts and verifies the update was actually completed
191 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
193 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
194 enum pipe pipe = crtc->pipe;
195 int scanline_end = intel_get_crtc_scanline(crtc);
196 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
197 ktime_t end_vbl_time = ktime_get();
198 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
200 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
202 /* We're still in the vblank-evade critical section, this can't race.
203 * Would be slightly nice to just grab the vblank count and arm the
204 * event outside of the critical section - the spinlock might spin for a
206 if (new_crtc_state->uapi.event) {
207 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
209 spin_lock(&crtc->base.dev->event_lock);
210 drm_crtc_arm_vblank_event(&crtc->base,
211 new_crtc_state->uapi.event);
212 spin_unlock(&crtc->base.dev->event_lock);
214 new_crtc_state->uapi.event = NULL;
219 if (intel_vgpu_active(dev_priv))
222 if (crtc->debug.start_vbl_count &&
223 crtc->debug.start_vbl_count != end_vbl_count) {
224 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
225 pipe_name(pipe), crtc->debug.start_vbl_count,
227 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
228 crtc->debug.min_vbl, crtc->debug.max_vbl,
229 crtc->debug.scanline_start, scanline_end);
231 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
232 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
233 VBLANK_EVASION_TIME_US)
234 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
236 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
237 VBLANK_EVASION_TIME_US);
241 int intel_plane_check_stride(const struct intel_plane_state *plane_state)
243 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
244 const struct drm_framebuffer *fb = plane_state->hw.fb;
245 unsigned int rotation = plane_state->hw.rotation;
246 u32 stride, max_stride;
249 * We ignore stride for all invisible planes that
250 * can be remapped. Otherwise we could end up
251 * with a false positive when the remapping didn't
252 * kick in due the plane being invisible.
254 if (intel_plane_can_remap(plane_state) &&
255 !plane_state->uapi.visible)
258 /* FIXME other color planes? */
259 stride = plane_state->color_plane[0].stride;
260 max_stride = plane->max_stride(plane, fb->format->format,
261 fb->modifier, rotation);
263 if (stride > max_stride) {
264 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
266 plane->base.base.id, plane->base.name, max_stride);
273 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
275 const struct drm_framebuffer *fb = plane_state->hw.fb;
276 struct drm_rect *src = &plane_state->uapi.src;
277 u32 src_x, src_y, src_w, src_h, hsub, vsub;
278 bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
281 * Hardware doesn't handle subpixel coordinates.
282 * Adjust to (macro)pixel boundary, but be careful not to
283 * increase the source viewport size, because that could
284 * push the downscaling factor out of bounds.
286 src_x = src->x1 >> 16;
287 src_w = drm_rect_width(src) >> 16;
288 src_y = src->y1 >> 16;
289 src_h = drm_rect_height(src) >> 16;
291 drm_rect_init(src, src_x << 16, src_y << 16,
292 src_w << 16, src_h << 16);
294 if (!fb->format->is_yuv)
297 /* YUV specific checks */
299 hsub = fb->format->hsub;
300 vsub = fb->format->vsub;
302 hsub = vsub = max(fb->format->hsub, fb->format->vsub);
305 if (src_x % hsub || src_w % hsub) {
306 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u for %sYUV planes\n",
307 src_x, src_w, hsub, rotated ? "rotated " : "");
311 if (src_y % vsub || src_h % vsub) {
312 DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u for %sYUV planes\n",
313 src_y, src_h, vsub, rotated ? "rotated " : "");
320 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
322 return INTEL_GEN(dev_priv) >= 11 &&
323 icl_hdr_plane_mask() & BIT(plane_id);
327 skl_plane_ratio(const struct intel_crtc_state *crtc_state,
328 const struct intel_plane_state *plane_state,
329 unsigned int *num, unsigned int *den)
331 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
332 const struct drm_framebuffer *fb = plane_state->hw.fb;
334 if (fb->format->cpp[0] == 8) {
335 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
348 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
349 const struct intel_plane_state *plane_state)
351 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
352 unsigned int pixel_rate = crtc_state->pixel_rate;
353 unsigned int src_w, src_h, dst_w, dst_h;
354 unsigned int num, den;
356 skl_plane_ratio(crtc_state, plane_state, &num, &den);
358 /* two pixels per clock on glk+ */
359 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
362 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
363 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
364 dst_w = drm_rect_width(&plane_state->uapi.dst);
365 dst_h = drm_rect_height(&plane_state->uapi.dst);
367 /* Downscaling limits the maximum pixel rate */
368 dst_w = min(src_w, dst_w);
369 dst_h = min(src_h, dst_h);
371 return DIV64_U64_ROUND_UP(mul_u32_u32(pixel_rate * num, src_w * src_h),
372 mul_u32_u32(den, dst_w * dst_h));
376 skl_plane_max_stride(struct intel_plane *plane,
377 u32 pixel_format, u64 modifier,
378 unsigned int rotation)
380 const struct drm_format_info *info = drm_format_info(pixel_format);
381 int cpp = info->cpp[0];
384 * "The stride in bytes must not exceed the
385 * of the size of 8K pixels and 32K bytes."
387 if (drm_rotation_90_or_270(rotation))
388 return min(8192, 32768 / cpp);
390 return min(8192 * cpp, 32768);
394 skl_program_scaler(struct intel_plane *plane,
395 const struct intel_crtc_state *crtc_state,
396 const struct intel_plane_state *plane_state)
398 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
399 const struct drm_framebuffer *fb = plane_state->hw.fb;
400 enum pipe pipe = plane->pipe;
401 int scaler_id = plane_state->scaler_id;
402 const struct intel_scaler *scaler =
403 &crtc_state->scaler_state.scalers[scaler_id];
404 int crtc_x = plane_state->uapi.dst.x1;
405 int crtc_y = plane_state->uapi.dst.y1;
406 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
407 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
408 u16 y_hphase, uv_rgb_hphase;
409 u16 y_vphase, uv_rgb_vphase;
412 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
413 &plane_state->uapi.dst,
415 vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
416 &plane_state->uapi.dst,
419 /* TODO: handle sub-pixel coordinates */
420 if (drm_format_info_is_yuv_semiplanar(fb->format) &&
421 !icl_is_hdr_plane(dev_priv, plane->id)) {
422 y_hphase = skl_scaler_calc_phase(1, hscale, false);
423 y_vphase = skl_scaler_calc_phase(1, vscale, false);
425 /* MPEG2 chroma siting convention */
426 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
427 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
433 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
434 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
437 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
438 PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
439 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
440 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
441 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
442 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
443 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
444 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
447 /* Preoffset values for YUV to RGB Conversion */
448 #define PREOFF_YUV_TO_RGB_HI 0x1800
449 #define PREOFF_YUV_TO_RGB_ME 0x1F00
450 #define PREOFF_YUV_TO_RGB_LO 0x1800
452 #define ROFF(x) (((x) & 0xffff) << 16)
453 #define GOFF(x) (((x) & 0xffff) << 0)
454 #define BOFF(x) (((x) & 0xffff) << 16)
457 icl_program_input_csc(struct intel_plane *plane,
458 const struct intel_crtc_state *crtc_state,
459 const struct intel_plane_state *plane_state)
461 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
462 enum pipe pipe = plane->pipe;
463 enum plane_id plane_id = plane->id;
465 static const u16 input_csc_matrix[][9] = {
467 * BT.601 full range YCbCr -> full range RGB
468 * The matrix required is :
469 * [1.000, 0.000, 1.371,
470 * 1.000, -0.336, -0.698,
471 * 1.000, 1.732, 0.0000]
473 [DRM_COLOR_YCBCR_BT601] = {
475 0x8B28, 0x7800, 0x9AC0,
479 * BT.709 full range YCbCr -> full range RGB
480 * The matrix required is :
481 * [1.000, 0.000, 1.574,
482 * 1.000, -0.187, -0.468,
483 * 1.000, 1.855, 0.0000]
485 [DRM_COLOR_YCBCR_BT709] = {
487 0x9EF8, 0x7800, 0xAC00,
491 * BT.2020 full range YCbCr -> full range RGB
492 * The matrix required is :
493 * [1.000, 0.000, 1.474,
494 * 1.000, -0.1645, -0.5713,
495 * 1.000, 1.8814, 0.0000]
497 [DRM_COLOR_YCBCR_BT2020] = {
499 0x8928, 0x7800, 0xAA88,
504 /* Matrix for Limited Range to Full Range Conversion */
505 static const u16 input_csc_matrix_lr[][9] = {
507 * BT.601 Limted range YCbCr -> full range RGB
508 * The matrix required is :
509 * [1.164384, 0.000, 1.596027,
510 * 1.164384, -0.39175, -0.812813,
511 * 1.164384, 2.017232, 0.0000]
513 [DRM_COLOR_YCBCR_BT601] = {
515 0x8D00, 0x7950, 0x9C88,
519 * BT.709 Limited range YCbCr -> full range RGB
520 * The matrix required is :
521 * [1.164384, 0.000, 1.792741,
522 * 1.164384, -0.213249, -0.532909,
523 * 1.164384, 2.112402, 0.0000]
525 [DRM_COLOR_YCBCR_BT709] = {
527 0x8888, 0x7950, 0xADA8,
531 * BT.2020 Limited range YCbCr -> full range RGB
532 * The matrix required is :
533 * [1.164, 0.000, 1.678,
534 * 1.164, -0.1873, -0.6504,
535 * 1.164, 2.1417, 0.0000]
537 [DRM_COLOR_YCBCR_BT2020] = {
539 0x8A68, 0x7950, 0xAC00,
545 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
546 csc = input_csc_matrix[plane_state->hw.color_encoding];
548 csc = input_csc_matrix_lr[plane_state->hw.color_encoding];
550 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |
552 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2]));
553 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) |
555 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5]));
556 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) |
558 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8]));
560 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
561 PREOFF_YUV_TO_RGB_HI);
562 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
563 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0);
565 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
566 PREOFF_YUV_TO_RGB_ME);
567 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
568 PREOFF_YUV_TO_RGB_LO);
569 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
570 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
571 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
575 skl_program_plane(struct intel_plane *plane,
576 const struct intel_crtc_state *crtc_state,
577 const struct intel_plane_state *plane_state,
578 int color_plane, bool slave, u32 plane_ctl)
580 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
581 enum plane_id plane_id = plane->id;
582 enum pipe pipe = plane->pipe;
583 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
584 u32 surf_addr = plane_state->color_plane[color_plane].offset;
585 u32 stride = skl_plane_stride(plane_state, color_plane);
586 u32 aux_stride = skl_plane_stride(plane_state, 1);
587 int crtc_x = plane_state->uapi.dst.x1;
588 int crtc_y = plane_state->uapi.dst.y1;
589 u32 x = plane_state->color_plane[color_plane].x;
590 u32 y = plane_state->color_plane[color_plane].y;
591 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
592 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
593 struct intel_plane *linked = plane_state->planar_linked_plane;
594 const struct drm_framebuffer *fb = plane_state->hw.fb;
595 u8 alpha = plane_state->hw.alpha >> 8;
596 u32 plane_color_ctl = 0;
597 unsigned long irqflags;
600 plane_ctl |= skl_plane_ctl_crtc(crtc_state);
602 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
603 plane_color_ctl = plane_state->color_ctl |
604 glk_plane_color_ctl_crtc(crtc_state);
606 /* Sizes are 0 based */
610 keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
612 keymsk = key->channel_mask & 0x7ffffff;
614 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
616 /* The scaler will handle the output position */
617 if (plane_state->scaler_id >= 0) {
622 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
624 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
625 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
626 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
627 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
628 (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
630 if (icl_is_hdr_plane(dev_priv, plane_id)) {
634 /* Enable and use MPEG-2 chroma siting */
635 cus_ctl = PLANE_CUS_ENABLE |
637 PLANE_CUS_VPHASE_SIGN_NEGATIVE |
638 PLANE_CUS_VPHASE_0_25;
640 if (linked->id == PLANE_SPRITE5)
641 cus_ctl |= PLANE_CUS_PLANE_7;
642 else if (linked->id == PLANE_SPRITE4)
643 cus_ctl |= PLANE_CUS_PLANE_6;
645 MISSING_CASE(linked->id);
648 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
651 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
652 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
654 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
655 icl_program_input_csc(plane, crtc_state, plane_state);
657 skl_write_plane_wm(plane, crtc_state);
659 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
660 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
661 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
663 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
665 if (INTEL_GEN(dev_priv) < 11)
666 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
667 (plane_state->color_plane[1].y << 16) |
668 plane_state->color_plane[1].x);
671 * The control register self-arms if the plane was previously
672 * disabled. Try to make the plane enable atomic by writing
673 * the control register just before the surface register.
675 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
676 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
677 intel_plane_ggtt_offset(plane_state) + surf_addr);
679 if (!slave && plane_state->scaler_id >= 0)
680 skl_program_scaler(plane, crtc_state, plane_state);
682 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
686 skl_update_plane(struct intel_plane *plane,
687 const struct intel_crtc_state *crtc_state,
688 const struct intel_plane_state *plane_state)
692 if (plane_state->planar_linked_plane) {
693 /* Program the UV plane */
697 skl_program_plane(plane, crtc_state, plane_state,
698 color_plane, false, plane_state->ctl);
702 icl_update_slave(struct intel_plane *plane,
703 const struct intel_crtc_state *crtc_state,
704 const struct intel_plane_state *plane_state)
706 skl_program_plane(plane, crtc_state, plane_state, 0, true,
707 plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
711 skl_disable_plane(struct intel_plane *plane,
712 const struct intel_crtc_state *crtc_state)
714 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
715 enum plane_id plane_id = plane->id;
716 enum pipe pipe = plane->pipe;
717 unsigned long irqflags;
719 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
721 if (icl_is_hdr_plane(dev_priv, plane_id))
722 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0);
724 skl_write_plane_wm(plane, crtc_state);
726 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
727 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
729 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
733 skl_plane_get_hw_state(struct intel_plane *plane,
736 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
737 enum intel_display_power_domain power_domain;
738 enum plane_id plane_id = plane->id;
739 intel_wakeref_t wakeref;
742 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
743 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
747 ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
751 intel_display_power_put(dev_priv, power_domain, wakeref);
756 static void i9xx_plane_linear_gamma(u16 gamma[8])
758 /* The points are not evenly spaced. */
759 static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 };
762 for (i = 0; i < 8; i++)
763 gamma[i] = (in[i] << 8) / 32;
767 chv_update_csc(const struct intel_plane_state *plane_state)
769 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
770 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
771 const struct drm_framebuffer *fb = plane_state->hw.fb;
772 enum plane_id plane_id = plane->id;
774 * |r| | c0 c1 c2 | |cr|
775 * |g| = | c3 c4 c5 | x |y |
776 * |b| | c6 c7 c8 | |cb|
778 * Coefficients are s3.12.
780 * Cb and Cr apparently come in as signed already, and
781 * we always get full range data in on account of CLRC0/1.
783 static const s16 csc_matrix[][9] = {
784 /* BT.601 full range YCbCr -> full range RGB */
785 [DRM_COLOR_YCBCR_BT601] = {
790 /* BT.709 full range YCbCr -> full range RGB */
791 [DRM_COLOR_YCBCR_BT709] = {
797 const s16 *csc = csc_matrix[plane_state->hw.color_encoding];
799 /* Seems RGB data bypasses the CSC always */
800 if (!fb->format->is_yuv)
803 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
804 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
805 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
807 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
808 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
809 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
810 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
811 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
813 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
814 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
815 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
817 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
818 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
819 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
826 vlv_update_clrc(const struct intel_plane_state *plane_state)
828 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
829 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
830 const struct drm_framebuffer *fb = plane_state->hw.fb;
831 enum pipe pipe = plane->pipe;
832 enum plane_id plane_id = plane->id;
833 int contrast, brightness, sh_scale, sh_sin, sh_cos;
835 if (fb->format->is_yuv &&
836 plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
838 * Expand limited range to full range:
839 * Contrast is applied first and is used to expand Y range.
840 * Brightness is applied second and is used to remove the
841 * offset from Y. Saturation/hue is used to expand CbCr range.
843 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
844 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
845 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
846 sh_sin = SIN_0 * sh_scale;
847 sh_cos = COS_0 * sh_scale;
849 /* Pass-through everything. */
853 sh_sin = SIN_0 * sh_scale;
854 sh_cos = COS_0 * sh_scale;
857 /* FIXME these register are single buffered :( */
858 I915_WRITE_FW(SPCLRC0(pipe, plane_id),
859 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
860 I915_WRITE_FW(SPCLRC1(pipe, plane_id),
861 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
865 vlv_plane_ratio(const struct intel_crtc_state *crtc_state,
866 const struct intel_plane_state *plane_state,
867 unsigned int *num, unsigned int *den)
869 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
870 const struct drm_framebuffer *fb = plane_state->hw.fb;
871 unsigned int cpp = fb->format->cpp[0];
874 * VLV bspec only considers cases where all three planes are
875 * enabled, and cases where the primary and one sprite is enabled.
876 * Let's assume the case with just two sprites enabled also
877 * maps to the latter case.
879 if (hweight8(active_planes) == 3) {
894 } else if (hweight8(active_planes) == 2) {
923 int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
924 const struct intel_plane_state *plane_state)
926 unsigned int pixel_rate;
927 unsigned int num, den;
930 * Note that crtc_state->pixel_rate accounts for both
931 * horizontal and vertical panel fitter downscaling factors.
932 * Pre-HSW bspec tells us to only consider the horizontal
933 * downscaling factor here. We ignore that and just consider
934 * both for simplicity.
936 pixel_rate = crtc_state->pixel_rate;
938 vlv_plane_ratio(crtc_state, plane_state, &num, &den);
940 return DIV_ROUND_UP(pixel_rate * num, den);
943 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
947 if (crtc_state->gamma_enable)
948 sprctl |= SP_GAMMA_ENABLE;
953 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
954 const struct intel_plane_state *plane_state)
956 const struct drm_framebuffer *fb = plane_state->hw.fb;
957 unsigned int rotation = plane_state->hw.rotation;
958 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
963 switch (fb->format->format) {
964 case DRM_FORMAT_YUYV:
965 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
967 case DRM_FORMAT_YVYU:
968 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
970 case DRM_FORMAT_UYVY:
971 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
973 case DRM_FORMAT_VYUY:
974 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
976 case DRM_FORMAT_RGB565:
977 sprctl |= SP_FORMAT_BGR565;
979 case DRM_FORMAT_XRGB8888:
980 sprctl |= SP_FORMAT_BGRX8888;
982 case DRM_FORMAT_ARGB8888:
983 sprctl |= SP_FORMAT_BGRA8888;
985 case DRM_FORMAT_XBGR2101010:
986 sprctl |= SP_FORMAT_RGBX1010102;
988 case DRM_FORMAT_ABGR2101010:
989 sprctl |= SP_FORMAT_RGBA1010102;
991 case DRM_FORMAT_XBGR8888:
992 sprctl |= SP_FORMAT_RGBX8888;
994 case DRM_FORMAT_ABGR8888:
995 sprctl |= SP_FORMAT_RGBA8888;
998 MISSING_CASE(fb->format->format);
1002 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
1003 sprctl |= SP_YUV_FORMAT_BT709;
1005 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1008 if (rotation & DRM_MODE_ROTATE_180)
1009 sprctl |= SP_ROTATE_180;
1011 if (rotation & DRM_MODE_REFLECT_X)
1012 sprctl |= SP_MIRROR;
1014 if (key->flags & I915_SET_COLORKEY_SOURCE)
1015 sprctl |= SP_SOURCE_KEY;
1020 static void vlv_update_gamma(const struct intel_plane_state *plane_state)
1022 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1023 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1024 const struct drm_framebuffer *fb = plane_state->hw.fb;
1025 enum pipe pipe = plane->pipe;
1026 enum plane_id plane_id = plane->id;
1030 /* Seems RGB data bypasses the gamma always */
1031 if (!fb->format->is_yuv)
1034 i9xx_plane_linear_gamma(gamma);
1036 /* FIXME these register are single buffered :( */
1037 /* The two end points are implicit (0.0 and 1.0) */
1038 for (i = 1; i < 8 - 1; i++)
1039 I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1),
1046 vlv_update_plane(struct intel_plane *plane,
1047 const struct intel_crtc_state *crtc_state,
1048 const struct intel_plane_state *plane_state)
1050 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1051 enum pipe pipe = plane->pipe;
1052 enum plane_id plane_id = plane->id;
1053 u32 sprsurf_offset = plane_state->color_plane[0].offset;
1055 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1056 int crtc_x = plane_state->uapi.dst.x1;
1057 int crtc_y = plane_state->uapi.dst.y1;
1058 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
1059 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
1060 u32 x = plane_state->color_plane[0].x;
1061 u32 y = plane_state->color_plane[0].y;
1062 unsigned long irqflags;
1065 sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
1067 /* Sizes are 0 based */
1071 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1073 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1075 I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
1076 plane_state->color_plane[0].stride);
1077 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
1078 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
1079 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
1081 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
1082 chv_update_csc(plane_state);
1085 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
1086 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
1087 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
1090 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
1091 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
1094 * The control register self-arms if the plane was previously
1095 * disabled. Try to make the plane enable atomic by writing
1096 * the control register just before the surface register.
1098 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
1099 I915_WRITE_FW(SPSURF(pipe, plane_id),
1100 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
1102 vlv_update_clrc(plane_state);
1103 vlv_update_gamma(plane_state);
1105 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1109 vlv_disable_plane(struct intel_plane *plane,
1110 const struct intel_crtc_state *crtc_state)
1112 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1113 enum pipe pipe = plane->pipe;
1114 enum plane_id plane_id = plane->id;
1115 unsigned long irqflags;
1117 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1119 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
1120 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
1122 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1126 vlv_plane_get_hw_state(struct intel_plane *plane,
1129 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1130 enum intel_display_power_domain power_domain;
1131 enum plane_id plane_id = plane->id;
1132 intel_wakeref_t wakeref;
1135 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1136 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1140 ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
1142 *pipe = plane->pipe;
1144 intel_display_power_put(dev_priv, power_domain, wakeref);
1149 static void ivb_plane_ratio(const struct intel_crtc_state *crtc_state,
1150 const struct intel_plane_state *plane_state,
1151 unsigned int *num, unsigned int *den)
1153 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1154 const struct drm_framebuffer *fb = plane_state->hw.fb;
1155 unsigned int cpp = fb->format->cpp[0];
1157 if (hweight8(active_planes) == 2) {
1186 static void ivb_plane_ratio_scaling(const struct intel_crtc_state *crtc_state,
1187 const struct intel_plane_state *plane_state,
1188 unsigned int *num, unsigned int *den)
1190 const struct drm_framebuffer *fb = plane_state->hw.fb;
1191 unsigned int cpp = fb->format->cpp[0];
1213 int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
1214 const struct intel_plane_state *plane_state)
1216 unsigned int pixel_rate;
1217 unsigned int num, den;
1220 * Note that crtc_state->pixel_rate accounts for both
1221 * horizontal and vertical panel fitter downscaling factors.
1222 * Pre-HSW bspec tells us to only consider the horizontal
1223 * downscaling factor here. We ignore that and just consider
1224 * both for simplicity.
1226 pixel_rate = crtc_state->pixel_rate;
1228 ivb_plane_ratio(crtc_state, plane_state, &num, &den);
1230 return DIV_ROUND_UP(pixel_rate * num, den);
1233 static int ivb_sprite_min_cdclk(const struct intel_crtc_state *crtc_state,
1234 const struct intel_plane_state *plane_state)
1236 unsigned int src_w, dst_w, pixel_rate;
1237 unsigned int num, den;
1240 * Note that crtc_state->pixel_rate accounts for both
1241 * horizontal and vertical panel fitter downscaling factors.
1242 * Pre-HSW bspec tells us to only consider the horizontal
1243 * downscaling factor here. We ignore that and just consider
1244 * both for simplicity.
1246 pixel_rate = crtc_state->pixel_rate;
1248 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1249 dst_w = drm_rect_width(&plane_state->uapi.dst);
1252 ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den);
1254 ivb_plane_ratio(crtc_state, plane_state, &num, &den);
1256 /* Horizontal downscaling limits the maximum pixel rate */
1257 dst_w = min(src_w, dst_w);
1259 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w),
1263 static void hsw_plane_ratio(const struct intel_crtc_state *crtc_state,
1264 const struct intel_plane_state *plane_state,
1265 unsigned int *num, unsigned int *den)
1267 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1268 const struct drm_framebuffer *fb = plane_state->hw.fb;
1269 unsigned int cpp = fb->format->cpp[0];
1271 if (hweight8(active_planes) == 2) {
1296 int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
1297 const struct intel_plane_state *plane_state)
1299 unsigned int pixel_rate = crtc_state->pixel_rate;
1300 unsigned int num, den;
1302 hsw_plane_ratio(crtc_state, plane_state, &num, &den);
1304 return DIV_ROUND_UP(pixel_rate * num, den);
1307 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
1311 if (crtc_state->gamma_enable)
1312 sprctl |= SPRITE_GAMMA_ENABLE;
1314 if (crtc_state->csc_enable)
1315 sprctl |= SPRITE_PIPE_CSC_ENABLE;
1320 static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state)
1322 struct drm_i915_private *dev_priv =
1323 to_i915(plane_state->uapi.plane->dev);
1324 const struct drm_framebuffer *fb = plane_state->hw.fb;
1326 return fb->format->cpp[0] == 8 &&
1327 (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv));
1330 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
1331 const struct intel_plane_state *plane_state)
1333 struct drm_i915_private *dev_priv =
1334 to_i915(plane_state->uapi.plane->dev);
1335 const struct drm_framebuffer *fb = plane_state->hw.fb;
1336 unsigned int rotation = plane_state->hw.rotation;
1337 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1340 sprctl = SPRITE_ENABLE;
1342 if (IS_IVYBRIDGE(dev_priv))
1343 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
1345 switch (fb->format->format) {
1346 case DRM_FORMAT_XBGR8888:
1347 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
1349 case DRM_FORMAT_XRGB8888:
1350 sprctl |= SPRITE_FORMAT_RGBX888;
1352 case DRM_FORMAT_XBGR16161616F:
1353 sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX;
1355 case DRM_FORMAT_XRGB16161616F:
1356 sprctl |= SPRITE_FORMAT_RGBX161616;
1358 case DRM_FORMAT_YUYV:
1359 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
1361 case DRM_FORMAT_YVYU:
1362 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
1364 case DRM_FORMAT_UYVY:
1365 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
1367 case DRM_FORMAT_VYUY:
1368 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
1371 MISSING_CASE(fb->format->format);
1375 if (!ivb_need_sprite_gamma(plane_state))
1376 sprctl |= SPRITE_INT_GAMMA_DISABLE;
1378 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
1379 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
1381 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1382 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
1384 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1385 sprctl |= SPRITE_TILED;
1387 if (rotation & DRM_MODE_ROTATE_180)
1388 sprctl |= SPRITE_ROTATE_180;
1390 if (key->flags & I915_SET_COLORKEY_DESTINATION)
1391 sprctl |= SPRITE_DEST_KEY;
1392 else if (key->flags & I915_SET_COLORKEY_SOURCE)
1393 sprctl |= SPRITE_SOURCE_KEY;
1398 static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state,
1404 * WaFP16GammaEnabling:ivb,hsw
1405 * "Workaround : When using the 64-bit format, the sprite output
1406 * on each color channel has one quarter amplitude. It can be
1407 * brought up to full amplitude by using sprite internal gamma
1408 * correction, pipe gamma correction, or pipe color space
1409 * conversion to multiply the sprite output by four."
1413 for (i = 0; i < 16; i++)
1414 gamma[i] = min((scale * i << 10) / 16, (1 << 10) - 1);
1416 gamma[i] = min((scale * i << 10) / 16, 1 << 10);
1423 static void ivb_update_gamma(const struct intel_plane_state *plane_state)
1425 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1426 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1427 enum pipe pipe = plane->pipe;
1431 if (!ivb_need_sprite_gamma(plane_state))
1434 ivb_sprite_linear_gamma(plane_state, gamma);
1436 /* FIXME these register are single buffered :( */
1437 for (i = 0; i < 16; i++)
1438 I915_WRITE_FW(SPRGAMC(pipe, i),
1443 I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]);
1444 I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]);
1445 I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]);
1448 I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]);
1449 I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]);
1450 I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]);
1455 ivb_update_plane(struct intel_plane *plane,
1456 const struct intel_crtc_state *crtc_state,
1457 const struct intel_plane_state *plane_state)
1459 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1460 enum pipe pipe = plane->pipe;
1461 u32 sprsurf_offset = plane_state->color_plane[0].offset;
1463 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1464 int crtc_x = plane_state->uapi.dst.x1;
1465 int crtc_y = plane_state->uapi.dst.y1;
1466 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
1467 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
1468 u32 x = plane_state->color_plane[0].x;
1469 u32 y = plane_state->color_plane[0].y;
1470 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1471 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1472 u32 sprctl, sprscale = 0;
1473 unsigned long irqflags;
1475 sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
1477 /* Sizes are 0 based */
1483 if (crtc_w != src_w || crtc_h != src_h)
1484 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
1486 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1488 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1490 I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
1491 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
1492 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
1493 if (IS_IVYBRIDGE(dev_priv))
1494 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
1497 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
1498 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
1499 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
1502 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
1504 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1505 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
1507 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
1508 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
1512 * The control register self-arms if the plane was previously
1513 * disabled. Try to make the plane enable atomic by writing
1514 * the control register just before the surface register.
1516 I915_WRITE_FW(SPRCTL(pipe), sprctl);
1517 I915_WRITE_FW(SPRSURF(pipe),
1518 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
1520 ivb_update_gamma(plane_state);
1522 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1526 ivb_disable_plane(struct intel_plane *plane,
1527 const struct intel_crtc_state *crtc_state)
1529 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1530 enum pipe pipe = plane->pipe;
1531 unsigned long irqflags;
1533 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1535 I915_WRITE_FW(SPRCTL(pipe), 0);
1536 /* Disable the scaler */
1537 if (IS_IVYBRIDGE(dev_priv))
1538 I915_WRITE_FW(SPRSCALE(pipe), 0);
1539 I915_WRITE_FW(SPRSURF(pipe), 0);
1541 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1545 ivb_plane_get_hw_state(struct intel_plane *plane,
1548 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1549 enum intel_display_power_domain power_domain;
1550 intel_wakeref_t wakeref;
1553 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1554 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1558 ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
1560 *pipe = plane->pipe;
1562 intel_display_power_put(dev_priv, power_domain, wakeref);
1567 static int g4x_sprite_min_cdclk(const struct intel_crtc_state *crtc_state,
1568 const struct intel_plane_state *plane_state)
1570 const struct drm_framebuffer *fb = plane_state->hw.fb;
1571 unsigned int hscale, pixel_rate;
1572 unsigned int limit, decimate;
1575 * Note that crtc_state->pixel_rate accounts for both
1576 * horizontal and vertical panel fitter downscaling factors.
1577 * Pre-HSW bspec tells us to only consider the horizontal
1578 * downscaling factor here. We ignore that and just consider
1579 * both for simplicity.
1581 pixel_rate = crtc_state->pixel_rate;
1583 /* Horizontal downscaling limits the maximum pixel rate */
1584 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
1585 &plane_state->uapi.dst,
1587 if (hscale < 0x10000)
1590 /* Decimation steps at 2x,4x,8x,16x */
1591 decimate = ilog2(hscale >> 16);
1592 hscale >>= decimate;
1594 /* Starting limit is 90% of cdclk */
1597 /* -10% per decimation step */
1601 if (fb->format->cpp[0] >= 4)
1602 limit--; /* -10% for RGB */
1605 * We should also do -10% if sprite scaling is enabled
1606 * on the other pipe, but we can't really check for that,
1610 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale),
1615 g4x_sprite_max_stride(struct intel_plane *plane,
1616 u32 pixel_format, u64 modifier,
1617 unsigned int rotation)
1622 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
1626 if (crtc_state->gamma_enable)
1627 dvscntr |= DVS_GAMMA_ENABLE;
1629 if (crtc_state->csc_enable)
1630 dvscntr |= DVS_PIPE_CSC_ENABLE;
1635 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
1636 const struct intel_plane_state *plane_state)
1638 struct drm_i915_private *dev_priv =
1639 to_i915(plane_state->uapi.plane->dev);
1640 const struct drm_framebuffer *fb = plane_state->hw.fb;
1641 unsigned int rotation = plane_state->hw.rotation;
1642 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1645 dvscntr = DVS_ENABLE;
1647 if (IS_GEN(dev_priv, 6))
1648 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
1650 switch (fb->format->format) {
1651 case DRM_FORMAT_XBGR8888:
1652 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
1654 case DRM_FORMAT_XRGB8888:
1655 dvscntr |= DVS_FORMAT_RGBX888;
1657 case DRM_FORMAT_XBGR16161616F:
1658 dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR;
1660 case DRM_FORMAT_XRGB16161616F:
1661 dvscntr |= DVS_FORMAT_RGBX161616;
1663 case DRM_FORMAT_YUYV:
1664 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
1666 case DRM_FORMAT_YVYU:
1667 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
1669 case DRM_FORMAT_UYVY:
1670 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
1672 case DRM_FORMAT_VYUY:
1673 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
1676 MISSING_CASE(fb->format->format);
1680 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
1681 dvscntr |= DVS_YUV_FORMAT_BT709;
1683 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
1684 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
1686 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
1687 dvscntr |= DVS_TILED;
1689 if (rotation & DRM_MODE_ROTATE_180)
1690 dvscntr |= DVS_ROTATE_180;
1692 if (key->flags & I915_SET_COLORKEY_DESTINATION)
1693 dvscntr |= DVS_DEST_KEY;
1694 else if (key->flags & I915_SET_COLORKEY_SOURCE)
1695 dvscntr |= DVS_SOURCE_KEY;
1700 static void g4x_update_gamma(const struct intel_plane_state *plane_state)
1702 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1703 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1704 const struct drm_framebuffer *fb = plane_state->hw.fb;
1705 enum pipe pipe = plane->pipe;
1709 /* Seems RGB data bypasses the gamma always */
1710 if (!fb->format->is_yuv)
1713 i9xx_plane_linear_gamma(gamma);
1715 /* FIXME these register are single buffered :( */
1716 /* The two end points are implicit (0.0 and 1.0) */
1717 for (i = 1; i < 8 - 1; i++)
1718 I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1),
1724 static void ilk_sprite_linear_gamma(u16 gamma[17])
1728 for (i = 0; i < 17; i++)
1729 gamma[i] = (i << 10) / 16;
1732 static void ilk_update_gamma(const struct intel_plane_state *plane_state)
1734 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1735 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1736 const struct drm_framebuffer *fb = plane_state->hw.fb;
1737 enum pipe pipe = plane->pipe;
1741 /* Seems RGB data bypasses the gamma always */
1742 if (!fb->format->is_yuv)
1745 ilk_sprite_linear_gamma(gamma);
1747 /* FIXME these register are single buffered :( */
1748 for (i = 0; i < 16; i++)
1749 I915_WRITE_FW(DVSGAMC_ILK(pipe, i),
1754 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
1755 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
1756 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
1761 g4x_update_plane(struct intel_plane *plane,
1762 const struct intel_crtc_state *crtc_state,
1763 const struct intel_plane_state *plane_state)
1765 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1766 enum pipe pipe = plane->pipe;
1767 u32 dvssurf_offset = plane_state->color_plane[0].offset;
1769 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1770 int crtc_x = plane_state->uapi.dst.x1;
1771 int crtc_y = plane_state->uapi.dst.y1;
1772 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
1773 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
1774 u32 x = plane_state->color_plane[0].x;
1775 u32 y = plane_state->color_plane[0].y;
1776 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1777 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1778 u32 dvscntr, dvsscale = 0;
1779 unsigned long irqflags;
1781 dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
1783 /* Sizes are 0 based */
1789 if (crtc_w != src_w || crtc_h != src_h)
1790 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
1792 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
1794 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1796 I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
1797 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
1798 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
1799 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
1802 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
1803 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
1804 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
1807 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
1808 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
1811 * The control register self-arms if the plane was previously
1812 * disabled. Try to make the plane enable atomic by writing
1813 * the control register just before the surface register.
1815 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
1816 I915_WRITE_FW(DVSSURF(pipe),
1817 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1819 if (IS_G4X(dev_priv))
1820 g4x_update_gamma(plane_state);
1822 ilk_update_gamma(plane_state);
1824 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1828 g4x_disable_plane(struct intel_plane *plane,
1829 const struct intel_crtc_state *crtc_state)
1831 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1832 enum pipe pipe = plane->pipe;
1833 unsigned long irqflags;
1835 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1837 I915_WRITE_FW(DVSCNTR(pipe), 0);
1838 /* Disable the scaler */
1839 I915_WRITE_FW(DVSSCALE(pipe), 0);
1840 I915_WRITE_FW(DVSSURF(pipe), 0);
1842 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1846 g4x_plane_get_hw_state(struct intel_plane *plane,
1849 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1850 enum intel_display_power_domain power_domain;
1851 intel_wakeref_t wakeref;
1854 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1855 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1859 ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
1861 *pipe = plane->pipe;
1863 intel_display_power_put(dev_priv, power_domain, wakeref);
1868 static bool intel_fb_scalable(const struct drm_framebuffer *fb)
1873 switch (fb->format->format) {
1876 case DRM_FORMAT_XRGB16161616F:
1877 case DRM_FORMAT_ARGB16161616F:
1878 case DRM_FORMAT_XBGR16161616F:
1879 case DRM_FORMAT_ABGR16161616F:
1880 return INTEL_GEN(to_i915(fb->dev)) >= 11;
1887 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
1888 struct intel_plane_state *plane_state)
1890 const struct drm_framebuffer *fb = plane_state->hw.fb;
1891 const struct drm_rect *src = &plane_state->uapi.src;
1892 const struct drm_rect *dst = &plane_state->uapi.dst;
1893 int src_x, src_w, src_h, crtc_w, crtc_h;
1894 const struct drm_display_mode *adjusted_mode =
1895 &crtc_state->hw.adjusted_mode;
1896 unsigned int stride = plane_state->color_plane[0].stride;
1897 unsigned int cpp = fb->format->cpp[0];
1898 unsigned int width_bytes;
1899 int min_width, min_height;
1901 crtc_w = drm_rect_width(dst);
1902 crtc_h = drm_rect_height(dst);
1904 src_x = src->x1 >> 16;
1905 src_w = drm_rect_width(src) >> 16;
1906 src_h = drm_rect_height(src) >> 16;
1908 if (src_w == crtc_w && src_h == crtc_h)
1913 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1915 DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1923 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1925 if (src_w < min_width || src_h < min_height ||
1926 src_w > 2048 || src_h > 2048) {
1927 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1928 src_w, src_h, min_width, min_height, 2048, 2048);
1932 if (width_bytes > 4096) {
1933 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1938 if (stride > 4096) {
1939 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1948 g4x_sprite_check(struct intel_crtc_state *crtc_state,
1949 struct intel_plane_state *plane_state)
1951 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1952 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1953 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
1954 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
1957 if (intel_fb_scalable(plane_state->hw.fb)) {
1958 if (INTEL_GEN(dev_priv) < 7) {
1960 max_scale = 16 << 16;
1961 } else if (IS_IVYBRIDGE(dev_priv)) {
1963 max_scale = 2 << 16;
1967 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
1969 min_scale, max_scale,
1974 ret = i9xx_check_plane_surface(plane_state);
1978 if (!plane_state->uapi.visible)
1981 ret = intel_plane_check_src_coordinates(plane_state);
1985 ret = g4x_sprite_check_scaling(crtc_state, plane_state);
1989 if (INTEL_GEN(dev_priv) >= 7)
1990 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1992 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
1997 int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
1999 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2000 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2001 unsigned int rotation = plane_state->hw.rotation;
2003 /* CHV ignores the mirror bit when the rotate bit is set :( */
2004 if (IS_CHERRYVIEW(dev_priv) &&
2005 rotation & DRM_MODE_ROTATE_180 &&
2006 rotation & DRM_MODE_REFLECT_X) {
2007 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
2015 vlv_sprite_check(struct intel_crtc_state *crtc_state,
2016 struct intel_plane_state *plane_state)
2020 ret = chv_plane_check_rotation(plane_state);
2024 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
2026 DRM_PLANE_HELPER_NO_SCALING,
2027 DRM_PLANE_HELPER_NO_SCALING,
2032 ret = i9xx_check_plane_surface(plane_state);
2036 if (!plane_state->uapi.visible)
2039 ret = intel_plane_check_src_coordinates(plane_state);
2043 plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
2048 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
2049 const struct intel_plane_state *plane_state)
2051 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2052 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2053 const struct drm_framebuffer *fb = plane_state->hw.fb;
2054 unsigned int rotation = plane_state->hw.rotation;
2055 struct drm_format_name_buf format_name;
2060 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
2061 is_ccs_modifier(fb->modifier)) {
2062 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
2067 if (rotation & DRM_MODE_REFLECT_X &&
2068 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2069 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
2073 if (drm_rotation_90_or_270(rotation)) {
2074 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2075 fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
2076 DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
2081 * 90/270 is not allowed with RGB64 16:16:16:16 and
2082 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
2084 switch (fb->format->format) {
2085 case DRM_FORMAT_RGB565:
2086 if (INTEL_GEN(dev_priv) >= 11)
2090 case DRM_FORMAT_XRGB16161616F:
2091 case DRM_FORMAT_XBGR16161616F:
2092 case DRM_FORMAT_ARGB16161616F:
2093 case DRM_FORMAT_ABGR16161616F:
2094 case DRM_FORMAT_Y210:
2095 case DRM_FORMAT_Y212:
2096 case DRM_FORMAT_Y216:
2097 case DRM_FORMAT_XVYU12_16161616:
2098 case DRM_FORMAT_XVYU16161616:
2099 DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
2100 drm_get_format_name(fb->format->format,
2108 /* Y-tiling is not supported in IF-ID Interlace mode */
2109 if (crtc_state->hw.enable &&
2110 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
2111 (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
2112 fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
2113 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2114 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
2115 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
2122 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
2123 const struct intel_plane_state *plane_state)
2125 struct drm_i915_private *dev_priv =
2126 to_i915(plane_state->uapi.plane->dev);
2127 int crtc_x = plane_state->uapi.dst.x1;
2128 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
2129 int pipe_src_w = crtc_state->pipe_src_w;
2132 * Display WA #1175: cnl,glk
2133 * Planes other than the cursor may cause FIFO underflow and display
2134 * corruption if starting less than 4 pixels from the right edge of
2136 * Besides the above WA fix the similar problem, where planes other
2137 * than the cursor ending less than 4 pixels from the left edge of the
2138 * screen may cause FIFO underflow and display corruption.
2140 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
2141 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
2142 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
2143 crtc_x + crtc_w < 4 ? "end" : "start",
2144 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
2152 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
2154 const struct drm_framebuffer *fb = plane_state->hw.fb;
2155 unsigned int rotation = plane_state->hw.rotation;
2156 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
2158 /* Display WA #1106 */
2159 if (drm_format_info_is_yuv_semiplanar(fb->format) && src_w & 3 &&
2160 (rotation == DRM_MODE_ROTATE_270 ||
2161 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
2162 DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n");
2169 static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
2170 const struct drm_framebuffer *fb)
2173 * We don't yet know the final source width nor
2174 * whether we can use the HQ scaler mode. Assume
2176 * FIXME need to properly check this later.
2178 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
2179 !drm_format_info_is_yuv_semiplanar(fb->format))
2185 static int skl_plane_check(struct intel_crtc_state *crtc_state,
2186 struct intel_plane_state *plane_state)
2188 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2189 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2190 const struct drm_framebuffer *fb = plane_state->hw.fb;
2191 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
2192 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
2195 ret = skl_plane_check_fb(crtc_state, plane_state);
2199 /* use scaler when colorkey is not required */
2200 if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
2202 max_scale = skl_plane_max_scale(dev_priv, fb);
2205 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
2207 min_scale, max_scale,
2212 ret = skl_check_plane_surface(plane_state);
2216 if (!plane_state->uapi.visible)
2219 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
2223 ret = intel_plane_check_src_coordinates(plane_state);
2227 ret = skl_plane_check_nv12_rotation(plane_state);
2231 /* HW only has 8 bits pixel precision, disable plane if invisible */
2232 if (!(plane_state->hw.alpha >> 8))
2233 plane_state->uapi.visible = false;
2235 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
2237 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2238 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
2244 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
2246 return INTEL_GEN(dev_priv) >= 9;
2249 static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
2250 const struct drm_intel_sprite_colorkey *set)
2252 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2253 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2254 struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
2259 * We want src key enabled on the
2260 * sprite and not on the primary.
2262 if (plane->id == PLANE_PRIMARY &&
2263 set->flags & I915_SET_COLORKEY_SOURCE)
2267 * On SKL+ we want dst key enabled on
2268 * the primary and not on the sprite.
2270 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
2271 set->flags & I915_SET_COLORKEY_DESTINATION)
2275 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2276 struct drm_file *file_priv)
2278 struct drm_i915_private *dev_priv = to_i915(dev);
2279 struct drm_intel_sprite_colorkey *set = data;
2280 struct drm_plane *plane;
2281 struct drm_plane_state *plane_state;
2282 struct drm_atomic_state *state;
2283 struct drm_modeset_acquire_ctx ctx;
2286 /* ignore the pointless "none" flag */
2287 set->flags &= ~I915_SET_COLORKEY_NONE;
2289 if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
2292 /* Make sure we don't try to enable both src & dest simultaneously */
2293 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
2296 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2297 set->flags & I915_SET_COLORKEY_DESTINATION)
2300 plane = drm_plane_find(dev, file_priv, set->plane_id);
2301 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
2305 * SKL+ only plane 2 can do destination keying against plane 1.
2306 * Also multiple planes can't do destination keying on the same
2307 * pipe simultaneously.
2309 if (INTEL_GEN(dev_priv) >= 9 &&
2310 to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
2311 set->flags & I915_SET_COLORKEY_DESTINATION)
2314 drm_modeset_acquire_init(&ctx, 0);
2316 state = drm_atomic_state_alloc(plane->dev);
2321 state->acquire_ctx = &ctx;
2324 plane_state = drm_atomic_get_plane_state(state, plane);
2325 ret = PTR_ERR_OR_ZERO(plane_state);
2327 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
2330 * On some platforms we have to configure
2331 * the dst colorkey on the primary plane.
2333 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
2334 struct intel_crtc *crtc =
2335 intel_get_crtc_for_pipe(dev_priv,
2336 to_intel_plane(plane)->pipe);
2338 plane_state = drm_atomic_get_plane_state(state,
2339 crtc->base.primary);
2340 ret = PTR_ERR_OR_ZERO(plane_state);
2342 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
2346 ret = drm_atomic_commit(state);
2348 if (ret != -EDEADLK)
2351 drm_atomic_state_clear(state);
2352 drm_modeset_backoff(&ctx);
2355 drm_atomic_state_put(state);
2357 drm_modeset_drop_locks(&ctx);
2358 drm_modeset_acquire_fini(&ctx);
2362 static const u32 g4x_plane_formats[] = {
2363 DRM_FORMAT_XRGB8888,
2370 static const u64 i9xx_plane_format_modifiers[] = {
2371 I915_FORMAT_MOD_X_TILED,
2372 DRM_FORMAT_MOD_LINEAR,
2373 DRM_FORMAT_MOD_INVALID
2376 static const u32 snb_plane_formats[] = {
2377 DRM_FORMAT_XRGB8888,
2378 DRM_FORMAT_XBGR8888,
2379 DRM_FORMAT_XRGB16161616F,
2380 DRM_FORMAT_XBGR16161616F,
2387 static const u32 vlv_plane_formats[] = {
2389 DRM_FORMAT_ABGR8888,
2390 DRM_FORMAT_ARGB8888,
2391 DRM_FORMAT_XBGR8888,
2392 DRM_FORMAT_XRGB8888,
2393 DRM_FORMAT_XBGR2101010,
2394 DRM_FORMAT_ABGR2101010,
2401 static const u32 skl_plane_formats[] = {
2404 DRM_FORMAT_XRGB8888,
2405 DRM_FORMAT_XBGR8888,
2406 DRM_FORMAT_ARGB8888,
2407 DRM_FORMAT_ABGR8888,
2408 DRM_FORMAT_XRGB2101010,
2409 DRM_FORMAT_XBGR2101010,
2410 DRM_FORMAT_XRGB16161616F,
2411 DRM_FORMAT_XBGR16161616F,
2418 static const u32 skl_planar_formats[] = {
2421 DRM_FORMAT_XRGB8888,
2422 DRM_FORMAT_XBGR8888,
2423 DRM_FORMAT_ARGB8888,
2424 DRM_FORMAT_ABGR8888,
2425 DRM_FORMAT_XRGB2101010,
2426 DRM_FORMAT_XBGR2101010,
2427 DRM_FORMAT_XRGB16161616F,
2428 DRM_FORMAT_XBGR16161616F,
2436 static const u32 glk_planar_formats[] = {
2439 DRM_FORMAT_XRGB8888,
2440 DRM_FORMAT_XBGR8888,
2441 DRM_FORMAT_ARGB8888,
2442 DRM_FORMAT_ABGR8888,
2443 DRM_FORMAT_XRGB2101010,
2444 DRM_FORMAT_XBGR2101010,
2445 DRM_FORMAT_XRGB16161616F,
2446 DRM_FORMAT_XBGR16161616F,
2457 static const u32 icl_sdr_y_plane_formats[] = {
2460 DRM_FORMAT_XRGB8888,
2461 DRM_FORMAT_XBGR8888,
2462 DRM_FORMAT_ARGB8888,
2463 DRM_FORMAT_ABGR8888,
2464 DRM_FORMAT_XRGB2101010,
2465 DRM_FORMAT_XBGR2101010,
2473 DRM_FORMAT_XVYU2101010,
2474 DRM_FORMAT_XVYU12_16161616,
2475 DRM_FORMAT_XVYU16161616,
2478 static const u32 icl_sdr_uv_plane_formats[] = {
2481 DRM_FORMAT_XRGB8888,
2482 DRM_FORMAT_XBGR8888,
2483 DRM_FORMAT_ARGB8888,
2484 DRM_FORMAT_ABGR8888,
2485 DRM_FORMAT_XRGB2101010,
2486 DRM_FORMAT_XBGR2101010,
2498 DRM_FORMAT_XVYU2101010,
2499 DRM_FORMAT_XVYU12_16161616,
2500 DRM_FORMAT_XVYU16161616,
2503 static const u32 icl_hdr_plane_formats[] = {
2506 DRM_FORMAT_XRGB8888,
2507 DRM_FORMAT_XBGR8888,
2508 DRM_FORMAT_ARGB8888,
2509 DRM_FORMAT_ABGR8888,
2510 DRM_FORMAT_XRGB2101010,
2511 DRM_FORMAT_XBGR2101010,
2512 DRM_FORMAT_XRGB16161616F,
2513 DRM_FORMAT_XBGR16161616F,
2514 DRM_FORMAT_ARGB16161616F,
2515 DRM_FORMAT_ABGR16161616F,
2527 DRM_FORMAT_XVYU2101010,
2528 DRM_FORMAT_XVYU12_16161616,
2529 DRM_FORMAT_XVYU16161616,
2532 static const u64 skl_plane_format_modifiers_noccs[] = {
2533 I915_FORMAT_MOD_Yf_TILED,
2534 I915_FORMAT_MOD_Y_TILED,
2535 I915_FORMAT_MOD_X_TILED,
2536 DRM_FORMAT_MOD_LINEAR,
2537 DRM_FORMAT_MOD_INVALID
2540 static const u64 skl_plane_format_modifiers_ccs[] = {
2541 I915_FORMAT_MOD_Yf_TILED_CCS,
2542 I915_FORMAT_MOD_Y_TILED_CCS,
2543 I915_FORMAT_MOD_Yf_TILED,
2544 I915_FORMAT_MOD_Y_TILED,
2545 I915_FORMAT_MOD_X_TILED,
2546 DRM_FORMAT_MOD_LINEAR,
2547 DRM_FORMAT_MOD_INVALID
2550 static const u64 gen12_plane_format_modifiers_noccs[] = {
2551 I915_FORMAT_MOD_Y_TILED,
2552 I915_FORMAT_MOD_X_TILED,
2553 DRM_FORMAT_MOD_LINEAR,
2554 DRM_FORMAT_MOD_INVALID
2557 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
2558 u32 format, u64 modifier)
2561 case DRM_FORMAT_MOD_LINEAR:
2562 case I915_FORMAT_MOD_X_TILED:
2569 case DRM_FORMAT_XRGB8888:
2570 case DRM_FORMAT_YUYV:
2571 case DRM_FORMAT_YVYU:
2572 case DRM_FORMAT_UYVY:
2573 case DRM_FORMAT_VYUY:
2574 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2575 modifier == I915_FORMAT_MOD_X_TILED)
2583 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
2584 u32 format, u64 modifier)
2587 case DRM_FORMAT_MOD_LINEAR:
2588 case I915_FORMAT_MOD_X_TILED:
2595 case DRM_FORMAT_XRGB8888:
2596 case DRM_FORMAT_XBGR8888:
2597 case DRM_FORMAT_XRGB16161616F:
2598 case DRM_FORMAT_XBGR16161616F:
2599 case DRM_FORMAT_YUYV:
2600 case DRM_FORMAT_YVYU:
2601 case DRM_FORMAT_UYVY:
2602 case DRM_FORMAT_VYUY:
2603 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2604 modifier == I915_FORMAT_MOD_X_TILED)
2612 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
2613 u32 format, u64 modifier)
2616 case DRM_FORMAT_MOD_LINEAR:
2617 case I915_FORMAT_MOD_X_TILED:
2624 case DRM_FORMAT_RGB565:
2625 case DRM_FORMAT_ABGR8888:
2626 case DRM_FORMAT_ARGB8888:
2627 case DRM_FORMAT_XBGR8888:
2628 case DRM_FORMAT_XRGB8888:
2629 case DRM_FORMAT_XBGR2101010:
2630 case DRM_FORMAT_ABGR2101010:
2631 case DRM_FORMAT_YUYV:
2632 case DRM_FORMAT_YVYU:
2633 case DRM_FORMAT_UYVY:
2634 case DRM_FORMAT_VYUY:
2635 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2636 modifier == I915_FORMAT_MOD_X_TILED)
2644 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
2645 u32 format, u64 modifier)
2647 struct intel_plane *plane = to_intel_plane(_plane);
2650 case DRM_FORMAT_MOD_LINEAR:
2651 case I915_FORMAT_MOD_X_TILED:
2652 case I915_FORMAT_MOD_Y_TILED:
2653 case I915_FORMAT_MOD_Yf_TILED:
2655 case I915_FORMAT_MOD_Y_TILED_CCS:
2656 case I915_FORMAT_MOD_Yf_TILED_CCS:
2657 if (!plane->has_ccs)
2665 case DRM_FORMAT_XRGB8888:
2666 case DRM_FORMAT_XBGR8888:
2667 case DRM_FORMAT_ARGB8888:
2668 case DRM_FORMAT_ABGR8888:
2669 if (is_ccs_modifier(modifier))
2672 case DRM_FORMAT_RGB565:
2673 case DRM_FORMAT_XRGB2101010:
2674 case DRM_FORMAT_XBGR2101010:
2675 case DRM_FORMAT_YUYV:
2676 case DRM_FORMAT_YVYU:
2677 case DRM_FORMAT_UYVY:
2678 case DRM_FORMAT_VYUY:
2679 case DRM_FORMAT_NV12:
2680 case DRM_FORMAT_P010:
2681 case DRM_FORMAT_P012:
2682 case DRM_FORMAT_P016:
2683 case DRM_FORMAT_XVYU2101010:
2684 if (modifier == I915_FORMAT_MOD_Yf_TILED)
2688 case DRM_FORMAT_XBGR16161616F:
2689 case DRM_FORMAT_ABGR16161616F:
2690 case DRM_FORMAT_XRGB16161616F:
2691 case DRM_FORMAT_ARGB16161616F:
2692 case DRM_FORMAT_Y210:
2693 case DRM_FORMAT_Y212:
2694 case DRM_FORMAT_Y216:
2695 case DRM_FORMAT_XVYU12_16161616:
2696 case DRM_FORMAT_XVYU16161616:
2697 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2698 modifier == I915_FORMAT_MOD_X_TILED ||
2699 modifier == I915_FORMAT_MOD_Y_TILED)
2707 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
2708 u32 format, u64 modifier)
2711 case DRM_FORMAT_MOD_LINEAR:
2712 case I915_FORMAT_MOD_X_TILED:
2713 case I915_FORMAT_MOD_Y_TILED:
2720 case DRM_FORMAT_XRGB8888:
2721 case DRM_FORMAT_XBGR8888:
2722 case DRM_FORMAT_ARGB8888:
2723 case DRM_FORMAT_ABGR8888:
2724 case DRM_FORMAT_RGB565:
2725 case DRM_FORMAT_XRGB2101010:
2726 case DRM_FORMAT_XBGR2101010:
2727 case DRM_FORMAT_YUYV:
2728 case DRM_FORMAT_YVYU:
2729 case DRM_FORMAT_UYVY:
2730 case DRM_FORMAT_VYUY:
2731 case DRM_FORMAT_NV12:
2732 case DRM_FORMAT_P010:
2733 case DRM_FORMAT_P012:
2734 case DRM_FORMAT_P016:
2735 case DRM_FORMAT_XVYU2101010:
2737 case DRM_FORMAT_XBGR16161616F:
2738 case DRM_FORMAT_ABGR16161616F:
2739 case DRM_FORMAT_XRGB16161616F:
2740 case DRM_FORMAT_ARGB16161616F:
2741 case DRM_FORMAT_Y210:
2742 case DRM_FORMAT_Y212:
2743 case DRM_FORMAT_Y216:
2744 case DRM_FORMAT_XVYU12_16161616:
2745 case DRM_FORMAT_XVYU16161616:
2746 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2747 modifier == I915_FORMAT_MOD_X_TILED ||
2748 modifier == I915_FORMAT_MOD_Y_TILED)
2756 static const struct drm_plane_funcs g4x_sprite_funcs = {
2757 .update_plane = drm_atomic_helper_update_plane,
2758 .disable_plane = drm_atomic_helper_disable_plane,
2759 .destroy = intel_plane_destroy,
2760 .atomic_duplicate_state = intel_plane_duplicate_state,
2761 .atomic_destroy_state = intel_plane_destroy_state,
2762 .format_mod_supported = g4x_sprite_format_mod_supported,
2765 static const struct drm_plane_funcs snb_sprite_funcs = {
2766 .update_plane = drm_atomic_helper_update_plane,
2767 .disable_plane = drm_atomic_helper_disable_plane,
2768 .destroy = intel_plane_destroy,
2769 .atomic_duplicate_state = intel_plane_duplicate_state,
2770 .atomic_destroy_state = intel_plane_destroy_state,
2771 .format_mod_supported = snb_sprite_format_mod_supported,
2774 static const struct drm_plane_funcs vlv_sprite_funcs = {
2775 .update_plane = drm_atomic_helper_update_plane,
2776 .disable_plane = drm_atomic_helper_disable_plane,
2777 .destroy = intel_plane_destroy,
2778 .atomic_duplicate_state = intel_plane_duplicate_state,
2779 .atomic_destroy_state = intel_plane_destroy_state,
2780 .format_mod_supported = vlv_sprite_format_mod_supported,
2783 static const struct drm_plane_funcs skl_plane_funcs = {
2784 .update_plane = drm_atomic_helper_update_plane,
2785 .disable_plane = drm_atomic_helper_disable_plane,
2786 .destroy = intel_plane_destroy,
2787 .atomic_duplicate_state = intel_plane_duplicate_state,
2788 .atomic_destroy_state = intel_plane_destroy_state,
2789 .format_mod_supported = skl_plane_format_mod_supported,
2792 static const struct drm_plane_funcs gen12_plane_funcs = {
2793 .update_plane = drm_atomic_helper_update_plane,
2794 .disable_plane = drm_atomic_helper_disable_plane,
2795 .destroy = intel_plane_destroy,
2796 .atomic_duplicate_state = intel_plane_duplicate_state,
2797 .atomic_destroy_state = intel_plane_destroy_state,
2798 .format_mod_supported = gen12_plane_format_mod_supported,
2801 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
2802 enum pipe pipe, enum plane_id plane_id)
2804 if (!HAS_FBC(dev_priv))
2807 return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
2810 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2811 enum pipe pipe, enum plane_id plane_id)
2813 /* Display WA #0870: skl, bxt */
2814 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
2817 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
2820 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
2826 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
2827 enum pipe pipe, enum plane_id plane_id,
2830 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2831 *num_formats = ARRAY_SIZE(skl_planar_formats);
2832 return skl_planar_formats;
2834 *num_formats = ARRAY_SIZE(skl_plane_formats);
2835 return skl_plane_formats;
2839 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
2840 enum pipe pipe, enum plane_id plane_id,
2843 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2844 *num_formats = ARRAY_SIZE(glk_planar_formats);
2845 return glk_planar_formats;
2847 *num_formats = ARRAY_SIZE(skl_plane_formats);
2848 return skl_plane_formats;
2852 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
2853 enum pipe pipe, enum plane_id plane_id,
2856 if (icl_is_hdr_plane(dev_priv, plane_id)) {
2857 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
2858 return icl_hdr_plane_formats;
2859 } else if (icl_is_nv12_y_plane(plane_id)) {
2860 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
2861 return icl_sdr_y_plane_formats;
2863 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
2864 return icl_sdr_uv_plane_formats;
2868 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2869 enum pipe pipe, enum plane_id plane_id)
2871 if (plane_id == PLANE_CURSOR)
2874 if (INTEL_GEN(dev_priv) >= 10)
2877 if (IS_GEMINILAKE(dev_priv))
2878 return pipe != PIPE_C;
2880 return pipe != PIPE_C &&
2881 (plane_id == PLANE_PRIMARY ||
2882 plane_id == PLANE_SPRITE0);
2885 struct intel_plane *
2886 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2887 enum pipe pipe, enum plane_id plane_id)
2889 static const struct drm_plane_funcs *plane_funcs;
2890 struct intel_plane *plane;
2891 enum drm_plane_type plane_type;
2892 unsigned int supported_rotations;
2893 unsigned int possible_crtcs;
2894 const u64 *modifiers;
2899 plane = intel_plane_alloc();
2904 plane->id = plane_id;
2905 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2907 plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
2908 if (plane->has_fbc) {
2909 struct intel_fbc *fbc = &dev_priv->fbc;
2911 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
2914 plane->max_stride = skl_plane_max_stride;
2915 plane->update_plane = skl_update_plane;
2916 plane->disable_plane = skl_disable_plane;
2917 plane->get_hw_state = skl_plane_get_hw_state;
2918 plane->check_plane = skl_plane_check;
2919 plane->min_cdclk = skl_plane_min_cdclk;
2920 if (icl_is_nv12_y_plane(plane_id))
2921 plane->update_slave = icl_update_slave;
2923 if (INTEL_GEN(dev_priv) >= 11)
2924 formats = icl_get_plane_formats(dev_priv, pipe,
2925 plane_id, &num_formats);
2926 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2927 formats = glk_get_plane_formats(dev_priv, pipe,
2928 plane_id, &num_formats);
2930 formats = skl_get_plane_formats(dev_priv, pipe,
2931 plane_id, &num_formats);
2933 if (INTEL_GEN(dev_priv) >= 12) {
2934 /* TODO: Implement support for gen-12 CCS modifiers */
2935 plane->has_ccs = false;
2936 modifiers = gen12_plane_format_modifiers_noccs;
2937 plane_funcs = &gen12_plane_funcs;
2939 plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
2941 modifiers = skl_plane_format_modifiers_ccs;
2943 modifiers = skl_plane_format_modifiers_noccs;
2944 plane_funcs = &skl_plane_funcs;
2947 if (plane_id == PLANE_PRIMARY)
2948 plane_type = DRM_PLANE_TYPE_PRIMARY;
2950 plane_type = DRM_PLANE_TYPE_OVERLAY;
2952 possible_crtcs = BIT(pipe);
2954 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2955 possible_crtcs, plane_funcs,
2956 formats, num_formats, modifiers,
2958 "plane %d%c", plane_id + 1,
2963 supported_rotations =
2964 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2965 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2967 if (INTEL_GEN(dev_priv) >= 10)
2968 supported_rotations |= DRM_MODE_REFLECT_X;
2970 drm_plane_create_rotation_property(&plane->base,
2972 supported_rotations);
2974 drm_plane_create_color_properties(&plane->base,
2975 BIT(DRM_COLOR_YCBCR_BT601) |
2976 BIT(DRM_COLOR_YCBCR_BT709),
2977 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2978 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2979 DRM_COLOR_YCBCR_BT709,
2980 DRM_COLOR_YCBCR_LIMITED_RANGE);
2982 drm_plane_create_alpha_property(&plane->base);
2983 drm_plane_create_blend_mode_property(&plane->base,
2984 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2985 BIT(DRM_MODE_BLEND_PREMULTI) |
2986 BIT(DRM_MODE_BLEND_COVERAGE));
2988 drm_plane_create_zpos_immutable_property(&plane->base, plane_id);
2990 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
2995 intel_plane_free(plane);
2997 return ERR_PTR(ret);
3000 struct intel_plane *
3001 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
3002 enum pipe pipe, int sprite)
3004 struct intel_plane *plane;
3005 const struct drm_plane_funcs *plane_funcs;
3006 unsigned long possible_crtcs;
3007 unsigned int supported_rotations;
3008 const u64 *modifiers;
3013 if (INTEL_GEN(dev_priv) >= 9)
3014 return skl_universal_plane_create(dev_priv, pipe,
3015 PLANE_SPRITE0 + sprite);
3017 plane = intel_plane_alloc();
3021 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3022 plane->max_stride = i9xx_plane_max_stride;
3023 plane->update_plane = vlv_update_plane;
3024 plane->disable_plane = vlv_disable_plane;
3025 plane->get_hw_state = vlv_plane_get_hw_state;
3026 plane->check_plane = vlv_sprite_check;
3027 plane->min_cdclk = vlv_plane_min_cdclk;
3029 formats = vlv_plane_formats;
3030 num_formats = ARRAY_SIZE(vlv_plane_formats);
3031 modifiers = i9xx_plane_format_modifiers;
3033 plane_funcs = &vlv_sprite_funcs;
3034 } else if (INTEL_GEN(dev_priv) >= 7) {
3035 plane->max_stride = g4x_sprite_max_stride;
3036 plane->update_plane = ivb_update_plane;
3037 plane->disable_plane = ivb_disable_plane;
3038 plane->get_hw_state = ivb_plane_get_hw_state;
3039 plane->check_plane = g4x_sprite_check;
3041 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3042 plane->min_cdclk = hsw_plane_min_cdclk;
3044 plane->min_cdclk = ivb_sprite_min_cdclk;
3046 formats = snb_plane_formats;
3047 num_formats = ARRAY_SIZE(snb_plane_formats);
3048 modifiers = i9xx_plane_format_modifiers;
3050 plane_funcs = &snb_sprite_funcs;
3052 plane->max_stride = g4x_sprite_max_stride;
3053 plane->update_plane = g4x_update_plane;
3054 plane->disable_plane = g4x_disable_plane;
3055 plane->get_hw_state = g4x_plane_get_hw_state;
3056 plane->check_plane = g4x_sprite_check;
3057 plane->min_cdclk = g4x_sprite_min_cdclk;
3059 modifiers = i9xx_plane_format_modifiers;
3060 if (IS_GEN(dev_priv, 6)) {
3061 formats = snb_plane_formats;
3062 num_formats = ARRAY_SIZE(snb_plane_formats);
3064 plane_funcs = &snb_sprite_funcs;
3066 formats = g4x_plane_formats;
3067 num_formats = ARRAY_SIZE(g4x_plane_formats);
3069 plane_funcs = &g4x_sprite_funcs;
3073 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
3074 supported_rotations =
3075 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
3078 supported_rotations =
3079 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
3083 plane->id = PLANE_SPRITE0 + sprite;
3084 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
3086 possible_crtcs = BIT(pipe);
3088 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
3089 possible_crtcs, plane_funcs,
3090 formats, num_formats, modifiers,
3091 DRM_PLANE_TYPE_OVERLAY,
3092 "sprite %c", sprite_name(pipe, sprite));
3096 drm_plane_create_rotation_property(&plane->base,
3098 supported_rotations);
3100 drm_plane_create_color_properties(&plane->base,
3101 BIT(DRM_COLOR_YCBCR_BT601) |
3102 BIT(DRM_COLOR_YCBCR_BT709),
3103 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
3104 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
3105 DRM_COLOR_YCBCR_BT709,
3106 DRM_COLOR_YCBCR_LIMITED_RANGE);
3109 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
3111 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
3116 intel_plane_free(plane);
3118 return ERR_PTR(ret);