drivers/gpu/drm/i915/display/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <drm/drm_atomic_helper.h>
  25
  26 #include "display/intel_dp.h"
  27
  28 #include "i915_drv.h"
  29 #include "intel_atomic.h"
  30 #include "intel_display_types.h"
  31 #include "intel_psr.h"
  32 #include "intel_sprite.h"
  33
  34 /**
  35  * DOC: Panel Self Refresh (PSR/SRD)
  36  *
  37  * Since Haswell Display controller supports Panel Self-Refresh on display
  38  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  39  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  40  * when system is idle but display is on as it eliminates display refresh
  41  * request to DDR memory completely as long as the frame buffer for that
  42  * display is unchanged.
  43  *
  44  * Panel Self Refresh must be supported by both Hardware (source) and
  45  * Panel (sink).
  46  *
  47  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  48  * to power down the link and memory controller. For DSI panels the same idea
  49  * is called "manual mode".
  50  *
  51  * The implementation uses the hardware-based PSR support which automatically
  52  * enters/exits self-refresh mode. The hardware takes care of sending the
  53  * required DP aux message and could even retrain the link (that part isn't
  54  * enabled yet though). The hardware also keeps track of any frontbuffer
  55  * changes to know when to exit self-refresh mode again. Unfortunately that
  56  * part doesn't work too well, hence why the i915 PSR support uses the
  57  * software frontbuffer tracking to make sure it doesn't miss a screen
  58  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  59  * get called by the frontbuffer tracking code. Note that because of locking
  60  * issues the self-refresh re-enable code is done from a work queue, which
  61  * must be correctly synchronized/cancelled when shutting down the pipe."
  62  *
  63  * DC3CO (DC3 clock off)
  64  *
  65  * On top of PSR2, GEN12 adds a intermediate power savings state that turns
  66  * clock off automatically during PSR2 idle state.
  67  * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
  68  * entry/exit allows the HW to enter a low-power state even when page flipping
  69  * periodically (for instance a 30fps video playback scenario).
  70  *
  71  * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
  72  * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
  73  * frames, if no other flip occurs and the function above is executed, DC3CO is
  74  * disabled and PSR2 is configured to enter deep sleep, resetting again in case
  75  * of another flip.
  76  * Front buffer modifications do not trigger DC3CO activation on purpose as it
  77  * would bring a lot of complexity and most of the moderns systems will only
  78  * use page flips.
  79  */
  80
  81 static bool psr_global_enabled(struct drm_i915_private *i915)
  82 {
  83         switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
  84         case I915_PSR_DEBUG_DEFAULT:
  85                 return i915_modparams.enable_psr;
  86         case I915_PSR_DEBUG_DISABLE:
  87                 return false;
  88         default:
  89                 return true;
  90         }
  91 }
  92
  93 static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
  94                                const struct intel_crtc_state *crtc_state)
  95 {
  96         /* Cannot enable DSC and PSR2 simultaneously */
  97         drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable &&
  98                     crtc_state->has_psr2);
  99
 100         switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 101         case I915_PSR_DEBUG_DISABLE:
 102         case I915_PSR_DEBUG_FORCE_PSR1:
 103                 return false;
 104         default:
 105                 return crtc_state->has_psr2;
 106         }
 107 }
 108
 109 static void psr_irq_control(struct drm_i915_private *dev_priv)
 110 {
 111         enum transcoder trans_shift;
 112         u32 mask, val;
 113         i915_reg_t imr_reg;
 114
 115         /*
 116          * gen12+ has registers relative to transcoder and one per transcoder
 117          * using the same bit definition: handle it as TRANSCODER_EDP to force
 118          * 0 shift in bit definition
 119          */
 120         if (INTEL_GEN(dev_priv) >= 12) {
 121                 trans_shift = 0;
 122                 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
 123         } else {
 124                 trans_shift = dev_priv->psr.transcoder;
 125                 imr_reg = EDP_PSR_IMR;
 126         }
 127
 128         mask = EDP_PSR_ERROR(trans_shift);
 129         if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
 130                 mask |= EDP_PSR_POST_EXIT(trans_shift) |
 131                         EDP_PSR_PRE_ENTRY(trans_shift);
 132
 133         /* Warning: it is masking/setting reserved bits too */
 134         val = intel_de_read(dev_priv, imr_reg);
 135         val &= ~EDP_PSR_TRANS_MASK(trans_shift);
 136         val |= ~mask;
 137         intel_de_write(dev_priv, imr_reg, val);
 138 }
 139
 140 static void psr_event_print(u32 val, bool psr2_enabled)
 141 {
 142         DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val);
 143         if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 144                 DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");
 145         if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
 146                 DRM_DEBUG_KMS("\tPSR2 disabled\n");
 147         if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 148                 DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");
 149         if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
 150                 DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");
 151         if (val & PSR_EVENT_GRAPHICS_RESET)
 152                 DRM_DEBUG_KMS("\tGraphics reset\n");
 153         if (val & PSR_EVENT_PCH_INTERRUPT)
 154                 DRM_DEBUG_KMS("\tPCH interrupt\n");
 155         if (val & PSR_EVENT_MEMORY_UP)
 156                 DRM_DEBUG_KMS("\tMemory up\n");
 157         if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 158                 DRM_DEBUG_KMS("\tFront buffer modification\n");
 159         if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 160                 DRM_DEBUG_KMS("\tPSR watchdog timer expired\n");
 161         if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 162                 DRM_DEBUG_KMS("\tPIPE registers updated\n");
 163         if (val & PSR_EVENT_REGISTER_UPDATE)
 164                 DRM_DEBUG_KMS("\tRegister updated\n");
 165         if (val & PSR_EVENT_HDCP_ENABLE)
 166                 DRM_DEBUG_KMS("\tHDCP enabled\n");
 167         if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 168                 DRM_DEBUG_KMS("\tKVMR session enabled\n");
 169         if (val & PSR_EVENT_VBI_ENABLE)
 170                 DRM_DEBUG_KMS("\tVBI enabled\n");
 171         if (val & PSR_EVENT_LPSP_MODE_EXIT)
 172                 DRM_DEBUG_KMS("\tLPSP mode exited\n");
 173         if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
 174                 DRM_DEBUG_KMS("\tPSR disabled\n");
 175 }
 176
 177 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
 178 {
 179         enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
 180         enum transcoder trans_shift;
 181         i915_reg_t imr_reg;
 182         ktime_t time_ns =  ktime_get();
 183
 184         if (INTEL_GEN(dev_priv) >= 12) {
 185                 trans_shift = 0;
 186                 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
 187         } else {
 188                 trans_shift = dev_priv->psr.transcoder;
 189                 imr_reg = EDP_PSR_IMR;
 190         }
 191
 192         if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
 193                 dev_priv->psr.last_entry_attempt = time_ns;
 194                 drm_dbg_kms(&dev_priv->drm,
 195                             "[transcoder %s] PSR entry attempt in 2 vblanks\n",
 196                             transcoder_name(cpu_transcoder));
 197         }
 198
 199         if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
 200                 dev_priv->psr.last_exit = time_ns;
 201                 drm_dbg_kms(&dev_priv->drm,
 202                             "[transcoder %s] PSR exit completed\n",
 203                             transcoder_name(cpu_transcoder));
 204
 205                 if (INTEL_GEN(dev_priv) >= 9) {
 206                         u32 val = intel_de_read(dev_priv,
 207                                                 PSR_EVENT(cpu_transcoder));
 208                         bool psr2_enabled = dev_priv->psr.psr2_enabled;
 209
 210                         intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
 211                                        val);
 212                         psr_event_print(val, psr2_enabled);
 213                 }
 214         }
 215
 216         if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
 217                 u32 val;
 218
 219                 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
 220                          transcoder_name(cpu_transcoder));
 221
 222                 dev_priv->psr.irq_aux_error = true;
 223
 224                 /*
 225                  * If this interruption is not masked it will keep
 226                  * interrupting so fast that it prevents the scheduled
 227                  * work to run.
 228                  * Also after a PSR error, we don't want to arm PSR
 229                  * again so we don't care about unmask the interruption
 230                  * or unset irq_aux_error.
 231                  */
 232                 val = intel_de_read(dev_priv, imr_reg);
 233                 val |= EDP_PSR_ERROR(trans_shift);
 234                 intel_de_write(dev_priv, imr_reg, val);
 235
 236                 schedule_work(&dev_priv->psr.work);
 237         }
 238 }
 239
 240 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 241 {
 242         u8 alpm_caps = 0;
 243
 244         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
 245                               &alpm_caps) != 1)
 246                 return false;
 247         return alpm_caps & DP_ALPM_CAP;
 248 }
 249
 250 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 251 {
 252         u8 val = 8; /* assume the worst if we can't read the value */
 253
 254         if (drm_dp_dpcd_readb(&intel_dp->aux,
 255                               DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 256                 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 257         else
 258                 DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");
 259         return val;
 260 }
 261
 262 static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
 263 {
 264         u16 val;
 265         ssize_t r;
 266
 267         /*
 268          * Returning the default X granularity if granularity not required or
 269          * if DPCD read fails
 270          */
 271         if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
 272                 return 4;
 273
 274         r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2);
 275         if (r != 2)
 276                 DRM_DEBUG_KMS("Unable to read DP_PSR2_SU_X_GRANULARITY\n");
 277
 278         /*
 279          * Spec says that if the value read is 0 the default granularity should
 280          * be used instead.
 281          */
 282         if (r != 2 || val == 0)
 283                 val = 4;
 284
 285         return val;
 286 }
 287
 288 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 289 {
 290         struct drm_i915_private *dev_priv =
 291                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 292
 293         if (dev_priv->psr.dp) {
 294                 drm_warn(&dev_priv->drm,
 295                          "More than one eDP panel found, PSR support should be extended\n");
 296                 return;
 297         }
 298
 299         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 300                          sizeof(intel_dp->psr_dpcd));
 301
 302         if (!intel_dp->psr_dpcd[0])
 303                 return;
 304         drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
 305                     intel_dp->psr_dpcd[0]);
 306
 307         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
 308                 drm_dbg_kms(&dev_priv->drm,
 309                             "PSR support not currently available for this panel\n");
 310                 return;
 311         }
 312
 313         if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 314                 drm_dbg_kms(&dev_priv->drm,
 315                             "Panel lacks power state control, PSR cannot be enabled\n");
 316                 return;
 317         }
 318
 319         dev_priv->psr.sink_support = true;
 320         dev_priv->psr.sink_sync_latency =
 321                 intel_dp_get_sink_sync_latency(intel_dp);
 322
 323         dev_priv->psr.dp = intel_dp;
 324
 325         if (INTEL_GEN(dev_priv) >= 9 &&
 326             (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 327                 bool y_req = intel_dp->psr_dpcd[1] &
 328                              DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 329                 bool alpm = intel_dp_get_alpm_status(intel_dp);
 330
 331                 /*
 332                  * All panels that supports PSR version 03h (PSR2 +
 333                  * Y-coordinate) can handle Y-coordinates in VSC but we are
 334                  * only sure that it is going to be used when required by the
 335                  * panel. This way panel is capable to do selective update
 336                  * without a aux frame sync.
 337                  *
 338                  * To support PSR version 02h and PSR version 03h without
 339                  * Y-coordinate requirement panels we would need to enable
 340                  * GTC first.
 341                  */
 342                 dev_priv->psr.sink_psr2_support = y_req && alpm;
 343                 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
 344                             dev_priv->psr.sink_psr2_support ? "" : "not ");
 345
 346                 if (dev_priv->psr.sink_psr2_support) {
 347                         dev_priv->psr.colorimetry_support =
 348                                 intel_dp_get_colorimetry_status(intel_dp);
 349                         dev_priv->psr.su_x_granularity =
 350                                 intel_dp_get_su_x_granulartiy(intel_dp);
 351                 }
 352         }
 353 }
 354
 355 static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
 356                                 const struct intel_crtc_state *crtc_state)
 357 {
 358         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 359         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 360         struct dp_sdp psr_vsc;
 361
 362         if (dev_priv->psr.psr2_enabled) {
 363                 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 364                 memset(&psr_vsc, 0, sizeof(psr_vsc));
 365                 psr_vsc.sdp_header.HB0 = 0;
 366                 psr_vsc.sdp_header.HB1 = 0x7;
 367                 if (dev_priv->psr.colorimetry_support) {
 368                         psr_vsc.sdp_header.HB2 = 0x5;
 369                         psr_vsc.sdp_header.HB3 = 0x13;
 370                 } else {
 371                         psr_vsc.sdp_header.HB2 = 0x4;
 372                         psr_vsc.sdp_header.HB3 = 0xe;
 373                 }
 374         } else {
 375                 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
 376                 memset(&psr_vsc, 0, sizeof(psr_vsc));
 377                 psr_vsc.sdp_header.HB0 = 0;
 378                 psr_vsc.sdp_header.HB1 = 0x7;
 379                 psr_vsc.sdp_header.HB2 = 0x2;
 380                 psr_vsc.sdp_header.HB3 = 0x8;
 381         }
 382
 383         intel_dig_port->write_infoframe(&intel_dig_port->base,
 384                                         crtc_state,
 385                                         DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));
 386 }
 387
 388 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 389 {
 390         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 391         u32 aux_clock_divider, aux_ctl;
 392         int i;
 393         static const u8 aux_msg[] = {
 394                 [0] = DP_AUX_NATIVE_WRITE << 4,
 395                 [1] = DP_SET_POWER >> 8,
 396                 [2] = DP_SET_POWER & 0xff,
 397                 [3] = 1 - 1,
 398                 [4] = DP_SET_POWER_D0,
 399         };
 400         u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK |
 401                            EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
 402                            EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
 403                            EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
 404
 405         BUILD_BUG_ON(sizeof(aux_msg) > 20);
 406         for (i = 0; i < sizeof(aux_msg); i += 4)
 407                 intel_de_write(dev_priv,
 408                                EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2),
 409                                intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
 410
 411         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 412
 413         /* Start with bits set for DDI_AUX_CTL register */
 414         aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
 415                                              aux_clock_divider);
 416
 417         /* Select only valid bits for SRD_AUX_CTL */
 418         aux_ctl &= psr_aux_mask;
 419         intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder),
 420                        aux_ctl);
 421 }
 422
 423 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 424 {
 425         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 426         u8 dpcd_val = DP_PSR_ENABLE;
 427
 428         /* Enable ALPM at sink for psr2 */
 429         if (dev_priv->psr.psr2_enabled) {
 430                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 431                                    DP_ALPM_ENABLE |
 432                                    DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
 433
 434                 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 435         } else {
 436                 if (dev_priv->psr.link_standby)
 437                         dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 438
 439                 if (INTEL_GEN(dev_priv) >= 8)
 440                         dpcd_val |= DP_PSR_CRC_VERIFICATION;
 441         }
 442
 443         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 444
 445         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 446 }
 447
 448 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 449 {
 450         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 451         u32 val = 0;
 452
 453         if (INTEL_GEN(dev_priv) >= 11)
 454                 val |= EDP_PSR_TP4_TIME_0US;
 455
 456         if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
 457                 val |= EDP_PSR_TP1_TIME_0us;
 458         else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 459                 val |= EDP_PSR_TP1_TIME_100us;
 460         else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
 461                 val |= EDP_PSR_TP1_TIME_500us;
 462         else
 463                 val |= EDP_PSR_TP1_TIME_2500us;
 464
 465         if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
 466                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 467         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 468                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 469         else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 470                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 471         else
 472                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 473
 474         if (intel_dp_source_supports_hbr2(intel_dp) &&
 475             drm_dp_tps3_supported(intel_dp->dpcd))
 476                 val |= EDP_PSR_TP1_TP3_SEL;
 477         else
 478                 val |= EDP_PSR_TP1_TP2_SEL;
 479
 480         return val;
 481 }
 482
 483 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 484 {
 485         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 486         int idle_frames;
 487
 488         /* Let's use 6 as the minimum to cover all known cases including the
 489          * off-by-one issue that HW has in some cases.
 490          */
 491         idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 492         idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
 493
 494         if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
 495                 idle_frames = 0xf;
 496
 497         return idle_frames;
 498 }
 499
 500 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 501 {
 502         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 503         u32 max_sleep_time = 0x1f;
 504         u32 val = EDP_PSR_ENABLE;
 505
 506         val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
 507
 508         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 509         if (IS_HASWELL(dev_priv))
 510                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 511
 512         if (dev_priv->psr.link_standby)
 513                 val |= EDP_PSR_LINK_STANDBY;
 514
 515         val |= intel_psr1_get_tp_time(intel_dp);
 516
 517         if (INTEL_GEN(dev_priv) >= 8)
 518                 val |= EDP_PSR_CRC_ENABLE;
 519
 520         val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) &
 521                 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
 522         intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val);
 523 }
 524
 525 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 526 {
 527         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 528         u32 val;
 529
 530         val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
 531
 532         val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 533         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 534                 val |= EDP_Y_COORDINATE_ENABLE;
 535
 536         val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 537
 538         if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
 539             dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
 540                 val |= EDP_PSR2_TP2_TIME_50us;
 541         else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
 542                 val |= EDP_PSR2_TP2_TIME_100us;
 543         else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
 544                 val |= EDP_PSR2_TP2_TIME_500us;
 545         else
 546                 val |= EDP_PSR2_TP2_TIME_2500us;
 547
 548         /*
 549          * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
 550          * recommending keep this bit unset while PSR2 is enabled.
 551          */
 552         intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0);
 553
 554         intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
 555 }
 556
 557 static bool
 558 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
 559 {
 560         if (INTEL_GEN(dev_priv) < 9)
 561                 return false;
 562         else if (INTEL_GEN(dev_priv) >= 12)
 563                 return trans == TRANSCODER_A;
 564         else
 565                 return trans == TRANSCODER_EDP;
 566 }
 567
 568 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
 569 {
 570         if (!cstate || !cstate->hw.active)
 571                 return 0;
 572
 573         return DIV_ROUND_UP(1000 * 1000,
 574                             drm_mode_vrefresh(&cstate->hw.adjusted_mode));
 575 }
 576
 577 static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
 578                                      u32 idle_frames)
 579 {
 580         u32 val;
 581
 582         idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT;
 583         val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder));
 584         val &= ~EDP_PSR2_IDLE_FRAME_MASK;
 585         val |= idle_frames;
 586         intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
 587 }
 588
 589 static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv)
 590 {
 591         psr2_program_idle_frames(dev_priv, 0);
 592         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
 593 }
 594
 595 static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv)
 596 {
 597         struct intel_dp *intel_dp = dev_priv->psr.dp;
 598
 599         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 600         psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp));
 601 }
 602
 603 static void tgl_dc3co_disable_work(struct work_struct *work)
 604 {
 605         struct drm_i915_private *dev_priv =
 606                 container_of(work, typeof(*dev_priv), psr.dc3co_work.work);
 607
 608         mutex_lock(&dev_priv->psr.lock);
 609         /* If delayed work is pending, it is not idle */
 610         if (delayed_work_pending(&dev_priv->psr.dc3co_work))
 611                 goto unlock;
 612
 613         tgl_psr2_disable_dc3co(dev_priv);
 614 unlock:
 615         mutex_unlock(&dev_priv->psr.lock);
 616 }
 617
 618 static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
 619 {
 620         if (!dev_priv->psr.dc3co_enabled)
 621                 return;
 622
 623         cancel_delayed_work(&dev_priv->psr.dc3co_work);
 624         /* Before PSR2 exit disallow dc3co*/
 625         tgl_psr2_disable_dc3co(dev_priv);
 626 }
 627
 628 static void
 629 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 630                                   struct intel_crtc_state *crtc_state)
 631 {
 632         const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
 633         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 634         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 635         u32 exit_scanlines;
 636
 637         if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
 638                 return;
 639
 640         /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
 641         if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A ||
 642             dig_port->base.port != PORT_A)
 643                 return;
 644
 645         /*
 646          * DC3CO Exit time 200us B.Spec 49196
 647          * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
 648          */
 649         exit_scanlines =
 650                 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
 651
 652         if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
 653                 return;
 654
 655         crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
 656 }
 657
 658 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 659                                     struct intel_crtc_state *crtc_state)
 660 {
 661         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 662         int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 663         int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 664         int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 665
 666         if (!dev_priv->psr.sink_psr2_support)
 667                 return false;
 668
 669         if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
 670                 drm_dbg_kms(&dev_priv->drm,
 671                             "PSR2 not supported in transcoder %s\n",
 672                             transcoder_name(crtc_state->cpu_transcoder));
 673                 return false;
 674         }
 675
 676         /*
 677          * DSC and PSR2 cannot be enabled simultaneously. If a requested
 678          * resolution requires DSC to be enabled, priority is given to DSC
 679          * over PSR2.
 680          */
 681         if (crtc_state->dsc.compression_enable) {
 682                 drm_dbg_kms(&dev_priv->drm,
 683                             "PSR2 cannot be enabled since DSC is enabled\n");
 684                 return false;
 685         }
 686
 687         if (INTEL_GEN(dev_priv) >= 12) {
 688                 psr_max_h = 5120;
 689                 psr_max_v = 3200;
 690                 max_bpp = 30;
 691         } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 692                 psr_max_h = 4096;
 693                 psr_max_v = 2304;
 694                 max_bpp = 24;
 695         } else if (IS_GEN(dev_priv, 9)) {
 696                 psr_max_h = 3640;
 697                 psr_max_v = 2304;
 698                 max_bpp = 24;
 699         }
 700
 701         if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {
 702                 drm_dbg_kms(&dev_priv->drm,
 703                             "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 704                             crtc_hdisplay, crtc_vdisplay,
 705                             psr_max_h, psr_max_v);
 706                 return false;
 707         }
 708
 709         if (crtc_state->pipe_bpp > max_bpp) {
 710                 drm_dbg_kms(&dev_priv->drm,
 711                             "PSR2 not enabled, pipe bpp %d > max supported %d\n",
 712                             crtc_state->pipe_bpp, max_bpp);
 713                 return false;
 714         }
 715
 716         /*
 717          * HW sends SU blocks of size four scan lines, which means the starting
 718          * X coordinate and Y granularity requirements will always be met. We
 719          * only need to validate the SU block width is a multiple of
 720          * x granularity.
 721          */
 722         if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
 723                 drm_dbg_kms(&dev_priv->drm,
 724                             "PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
 725                             crtc_hdisplay, dev_priv->psr.su_x_granularity);
 726                 return false;
 727         }
 728
 729         if (crtc_state->crc_enabled) {
 730                 drm_dbg_kms(&dev_priv->drm,
 731                             "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
 732                 return false;
 733         }
 734
 735         tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 736         return true;
 737 }
 738
 739 void intel_psr_compute_config(struct intel_dp *intel_dp,
 740                               struct intel_crtc_state *crtc_state)
 741 {
 742         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 743         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 744         const struct drm_display_mode *adjusted_mode =
 745                 &crtc_state->hw.adjusted_mode;
 746         int psr_setup_time;
 747
 748         if (!CAN_PSR(dev_priv))
 749                 return;
 750
 751         if (intel_dp != dev_priv->psr.dp)
 752                 return;
 753
 754         /*
 755          * HSW spec explicitly says PSR is tied to port A.
 756          * BDW+ platforms have a instance of PSR registers per transcoder but
 757          * for now it only supports one instance of PSR, so lets keep it
 758          * hardcoded to PORT_A
 759          */
 760         if (dig_port->base.port != PORT_A) {
 761                 drm_dbg_kms(&dev_priv->drm,
 762                             "PSR condition failed: Port not supported\n");
 763                 return;
 764         }
 765
 766         if (dev_priv->psr.sink_not_reliable) {
 767                 drm_dbg_kms(&dev_priv->drm,
 768                             "PSR sink implementation is not reliable\n");
 769                 return;
 770         }
 771
 772         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 773                 drm_dbg_kms(&dev_priv->drm,
 774                             "PSR condition failed: Interlaced mode enabled\n");
 775                 return;
 776         }
 777
 778         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
 779         if (psr_setup_time < 0) {
 780                 drm_dbg_kms(&dev_priv->drm,
 781                             "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
 782                             intel_dp->psr_dpcd[1]);
 783                 return;
 784         }
 785
 786         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
 787             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
 788                 drm_dbg_kms(&dev_priv->drm,
 789                             "PSR condition failed: PSR setup time (%d us) too long\n",
 790                             psr_setup_time);
 791                 return;
 792         }
 793
 794         crtc_state->has_psr = true;
 795         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
 796 }
 797
 798 static void intel_psr_activate(struct intel_dp *intel_dp)
 799 {
 800         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 801
 802         if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
 803                 drm_WARN_ON(&dev_priv->drm,
 804                             intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
 805
 806         drm_WARN_ON(&dev_priv->drm,
 807                     intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
 808         drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active);
 809         lockdep_assert_held(&dev_priv->psr.lock);
 810
 811         /* psr1 and psr2 are mutually exclusive.*/
 812         if (dev_priv->psr.psr2_enabled)
 813                 hsw_activate_psr2(intel_dp);
 814         else
 815                 hsw_activate_psr1(intel_dp);
 816
 817         dev_priv->psr.active = true;
 818 }
 819
 820 static void intel_psr_enable_source(struct intel_dp *intel_dp,
 821                                     const struct intel_crtc_state *crtc_state)
 822 {
 823         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 824         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 825         u32 mask;
 826
 827         /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
 828          * use hardcoded values PSR AUX transactions
 829          */
 830         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 831                 hsw_psr_setup_aux(intel_dp);
 832
 833         if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
 834                                            !IS_GEMINILAKE(dev_priv))) {
 835                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
 836                 u32 chicken = intel_de_read(dev_priv, reg);
 837
 838                 chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
 839                            PSR2_ADD_VERTICAL_LINE_COUNT;
 840                 intel_de_write(dev_priv, reg, chicken);
 841         }
 842
 843         /*
 844          * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
 845          * mask LPSP to avoid dependency on other drivers that might block
 846          * runtime_pm besides preventing  other hw tracking issues now we
 847          * can rely on frontbuffer tracking.
 848          */
 849         mask = EDP_PSR_DEBUG_MASK_MEMUP |
 850                EDP_PSR_DEBUG_MASK_HPD |
 851                EDP_PSR_DEBUG_MASK_LPSP |
 852                EDP_PSR_DEBUG_MASK_MAX_SLEEP;
 853
 854         if (INTEL_GEN(dev_priv) < 11)
 855                 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
 856
 857         intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder),
 858                        mask);
 859
 860         psr_irq_control(dev_priv);
 861
 862         if (crtc_state->dc3co_exitline) {
 863                 u32 val;
 864
 865                 /*
 866                  * TODO: if future platforms supports DC3CO in more than one
 867                  * transcoder, EXITLINE will need to be unset when disabling PSR
 868                  */
 869                 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
 870                 val &= ~EXITLINE_MASK;
 871                 val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
 872                 val |= EXITLINE_ENABLE;
 873                 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
 874         }
 875 }
 876
 877 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 878                                     const struct intel_crtc_state *crtc_state)
 879 {
 880         struct intel_dp *intel_dp = dev_priv->psr.dp;
 881         u32 val;
 882
 883         drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
 884
 885         dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
 886         dev_priv->psr.busy_frontbuffer_bits = 0;
 887         dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 888         dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
 889         dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
 890         /* DC5/DC6 requires at least 6 idle frames */
 891         val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
 892         dev_priv->psr.dc3co_exit_delay = val;
 893
 894         /*
 895          * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
 896          * will still keep the error set even after the reset done in the
 897          * irq_preinstall and irq_uninstall hooks.
 898          * And enabling in this situation cause the screen to freeze in the
 899          * first time that PSR HW tries to activate so lets keep PSR disabled
 900          * to avoid any rendering problems.
 901          */
 902         if (INTEL_GEN(dev_priv) >= 12) {
 903                 val = intel_de_read(dev_priv,
 904                                     TRANS_PSR_IIR(dev_priv->psr.transcoder));
 905                 val &= EDP_PSR_ERROR(0);
 906         } else {
 907                 val = intel_de_read(dev_priv, EDP_PSR_IIR);
 908                 val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
 909         }
 910         if (val) {
 911                 dev_priv->psr.sink_not_reliable = true;
 912                 drm_dbg_kms(&dev_priv->drm,
 913                             "PSR interruption error set, not enabling PSR\n");
 914                 return;
 915         }
 916
 917         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
 918                     dev_priv->psr.psr2_enabled ? "2" : "1");
 919         intel_psr_setup_vsc(intel_dp, crtc_state);
 920         intel_psr_enable_sink(intel_dp);
 921         intel_psr_enable_source(intel_dp, crtc_state);
 922         dev_priv->psr.enabled = true;
 923
 924         intel_psr_activate(intel_dp);
 925 }
 926
 927 /**
 928  * intel_psr_enable - Enable PSR
 929  * @intel_dp: Intel DP
 930  * @crtc_state: new CRTC state
 931  *
 932  * This function can only be called after the pipe is fully trained and enabled.
 933  */
 934 void intel_psr_enable(struct intel_dp *intel_dp,
 935                       const struct intel_crtc_state *crtc_state)
 936 {
 937         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 938
 939         if (!crtc_state->has_psr)
 940                 return;
 941
 942         if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv)))
 943                 return;
 944
 945         drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
 946
 947         mutex_lock(&dev_priv->psr.lock);
 948
 949         if (!psr_global_enabled(dev_priv)) {
 950                 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
 951                 goto unlock;
 952         }
 953
 954         intel_psr_enable_locked(dev_priv, crtc_state);
 955
 956 unlock:
 957         mutex_unlock(&dev_priv->psr.lock);
 958 }
 959
 960 static void intel_psr_exit(struct drm_i915_private *dev_priv)
 961 {
 962         u32 val;
 963
 964         if (!dev_priv->psr.active) {
 965                 if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
 966                         val = intel_de_read(dev_priv,
 967                                             EDP_PSR2_CTL(dev_priv->psr.transcoder));
 968                         drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
 969                 }
 970
 971                 val = intel_de_read(dev_priv,
 972                                     EDP_PSR_CTL(dev_priv->psr.transcoder));
 973                 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
 974
 975                 return;
 976         }
 977
 978         if (dev_priv->psr.psr2_enabled) {
 979                 tgl_disallow_dc3co_on_psr2_exit(dev_priv);
 980                 val = intel_de_read(dev_priv,
 981                                     EDP_PSR2_CTL(dev_priv->psr.transcoder));
 982                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
 983                 val &= ~EDP_PSR2_ENABLE;
 984                 intel_de_write(dev_priv,
 985                                EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
 986         } else {
 987                 val = intel_de_read(dev_priv,
 988                                     EDP_PSR_CTL(dev_priv->psr.transcoder));
 989                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
 990                 val &= ~EDP_PSR_ENABLE;
 991                 intel_de_write(dev_priv,
 992                                EDP_PSR_CTL(dev_priv->psr.transcoder), val);
 993         }
 994         dev_priv->psr.active = false;
 995 }
 996
 997 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 998 {
 999         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1000         i915_reg_t psr_status;
1001         u32 psr_status_mask;
1002
1003         lockdep_assert_held(&dev_priv->psr.lock);
1004
1005         if (!dev_priv->psr.enabled)
1006                 return;
1007
1008         drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
1009                     dev_priv->psr.psr2_enabled ? "2" : "1");
1010
1011         intel_psr_exit(dev_priv);
1012
1013         if (dev_priv->psr.psr2_enabled) {
1014                 psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
1015                 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
1016         } else {
1017                 psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder);
1018                 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
1019         }
1020
1021         /* Wait till PSR is idle */
1022         if (intel_de_wait_for_clear(dev_priv, psr_status,
1023                                     psr_status_mask, 2000))
1024                 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
1025
1026         /* Disable PSR on Sink */
1027         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
1028
1029         if (dev_priv->psr.psr2_enabled)
1030                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
1031
1032         dev_priv->psr.enabled = false;
1033 }
1034
1035 /**
1036  * intel_psr_disable - Disable PSR
1037  * @intel_dp: Intel DP
1038  * @old_crtc_state: old CRTC state
1039  *
1040  * This function needs to be called before disabling pipe.
1041  */
1042 void intel_psr_disable(struct intel_dp *intel_dp,
1043                        const struct intel_crtc_state *old_crtc_state)
1044 {
1045         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1046
1047         if (!old_crtc_state->has_psr)
1048                 return;
1049
1050         if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv)))
1051                 return;
1052
1053         mutex_lock(&dev_priv->psr.lock);
1054
1055         intel_psr_disable_locked(intel_dp);
1056
1057         mutex_unlock(&dev_priv->psr.lock);
1058         cancel_work_sync(&dev_priv->psr.work);
1059         cancel_delayed_work_sync(&dev_priv->psr.dc3co_work);
1060 }
1061
1062 static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
1063 {
1064         if (INTEL_GEN(dev_priv) >= 9)
1065                 /*
1066                  * Display WA #0884: skl+
1067                  * This documented WA for bxt can be safely applied
1068                  * broadly so we can force HW tracking to exit PSR
1069                  * instead of disabling and re-enabling.
1070                  * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1071                  * but it makes more sense write to the current active
1072                  * pipe.
1073                  */
1074                 intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0);
1075         else
1076                 /*
1077                  * A write to CURSURFLIVE do not cause HW tracking to exit PSR
1078                  * on older gens so doing the manual exit instead.
1079                  */
1080                 intel_psr_exit(dev_priv);
1081 }
1082
1083 /**
1084  * intel_psr_update - Update PSR state
1085  * @intel_dp: Intel DP
1086  * @crtc_state: new CRTC state
1087  *
1088  * This functions will update PSR states, disabling, enabling or switching PSR
1089  * version when executing fastsets. For full modeset, intel_psr_disable() and
1090  * intel_psr_enable() should be called instead.
1091  */
1092 void intel_psr_update(struct intel_dp *intel_dp,
1093                       const struct intel_crtc_state *crtc_state)
1094 {
1095         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1096         struct i915_psr *psr = &dev_priv->psr;
1097         bool enable, psr2_enable;
1098
1099         if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
1100                 return;
1101
1102         mutex_lock(&dev_priv->psr.lock);
1103
1104         enable = crtc_state->has_psr && psr_global_enabled(dev_priv);
1105         psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
1106
1107         if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
1108                 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
1109                 if (crtc_state->crc_enabled && psr->enabled)
1110                         psr_force_hw_tracking_exit(dev_priv);
1111                 else if (INTEL_GEN(dev_priv) < 9 && psr->enabled) {
1112                         /*
1113                          * Activate PSR again after a force exit when enabling
1114                          * CRC in older gens
1115                          */
1116                         if (!dev_priv->psr.active &&
1117                             !dev_priv->psr.busy_frontbuffer_bits)
1118                                 schedule_work(&dev_priv->psr.work);
1119                 }
1120
1121                 goto unlock;
1122         }
1123
1124         if (psr->enabled)
1125                 intel_psr_disable_locked(intel_dp);
1126
1127         if (enable)
1128                 intel_psr_enable_locked(dev_priv, crtc_state);
1129
1130 unlock:
1131         mutex_unlock(&dev_priv->psr.lock);
1132 }
1133
1134 /**
1135  * intel_psr_wait_for_idle - wait for PSR1 to idle
1136  * @new_crtc_state: new CRTC state
1137  * @out_value: PSR status in case of failure
1138  *
1139  * This function is expected to be called from pipe_update_start() where it is
1140  * not expected to race with PSR enable or disable.
1141  *
1142  * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
1143  */
1144 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
1145                             u32 *out_value)
1146 {
1147         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1148         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1149
1150         if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
1151                 return 0;
1152
1153         /* FIXME: Update this for PSR2 if we need to wait for idle */
1154         if (READ_ONCE(dev_priv->psr.psr2_enabled))
1155                 return 0;
1156
1157         /*
1158          * From bspec: Panel Self Refresh (BDW+)
1159          * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
1160          * exit training time + 1.5 ms of aux channel handshake. 50 ms is
1161          * defensive enough to cover everything.
1162          */
1163
1164         return __intel_wait_for_register(&dev_priv->uncore,
1165                                          EDP_PSR_STATUS(dev_priv->psr.transcoder),
1166                                          EDP_PSR_STATUS_STATE_MASK,
1167                                          EDP_PSR_STATUS_STATE_IDLE, 2, 50,
1168                                          out_value);
1169 }
1170
1171 static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
1172 {
1173         i915_reg_t reg;
1174         u32 mask;
1175         int err;
1176
1177         if (!dev_priv->psr.enabled)
1178                 return false;
1179
1180         if (dev_priv->psr.psr2_enabled) {
1181                 reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
1182                 mask = EDP_PSR2_STATUS_STATE_MASK;
1183         } else {
1184                 reg = EDP_PSR_STATUS(dev_priv->psr.transcoder);
1185                 mask = EDP_PSR_STATUS_STATE_MASK;
1186         }
1187
1188         mutex_unlock(&dev_priv->psr.lock);
1189
1190         err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
1191         if (err)
1192                 drm_err(&dev_priv->drm,
1193                         "Timed out waiting for PSR Idle for re-enable\n");
1194
1195         /* After the unlocked wait, verify that PSR is still wanted! */
1196         mutex_lock(&dev_priv->psr.lock);
1197         return err == 0 && dev_priv->psr.enabled;
1198 }
1199
1200 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
1201 {
1202         struct drm_device *dev = &dev_priv->drm;
1203         struct drm_modeset_acquire_ctx ctx;
1204         struct drm_atomic_state *state;
1205         struct intel_crtc *crtc;
1206         int err;
1207
1208         state = drm_atomic_state_alloc(dev);
1209         if (!state)
1210                 return -ENOMEM;
1211
1212         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1213         state->acquire_ctx = &ctx;
1214
1215 retry:
1216         for_each_intel_crtc(dev, crtc) {
1217                 struct intel_crtc_state *crtc_state =
1218                         intel_atomic_get_crtc_state(state, crtc);
1219
1220                 if (IS_ERR(crtc_state)) {
1221                         err = PTR_ERR(crtc_state);
1222                         goto error;
1223                 }
1224
1225                 if (crtc_state->hw.active && crtc_state->has_psr) {
1226                         /* Mark mode as changed to trigger a pipe->update() */
1227                         crtc_state->uapi.mode_changed = true;
1228                         break;
1229                 }
1230         }
1231
1232         err = drm_atomic_commit(state);
1233
1234 error:
1235         if (err == -EDEADLK) {
1236                 drm_atomic_state_clear(state);
1237                 err = drm_modeset_backoff(&ctx);
1238                 if (!err)
1239                         goto retry;
1240         }
1241
1242         drm_modeset_drop_locks(&ctx);
1243         drm_modeset_acquire_fini(&ctx);
1244         drm_atomic_state_put(state);
1245
1246         return err;
1247 }
1248
1249 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
1250 {
1251         const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
1252         u32 old_mode;
1253         int ret;
1254
1255         if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
1256             mode > I915_PSR_DEBUG_FORCE_PSR1) {
1257                 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
1258                 return -EINVAL;
1259         }
1260
1261         ret = mutex_lock_interruptible(&dev_priv->psr.lock);
1262         if (ret)
1263                 return ret;
1264
1265         old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
1266         dev_priv->psr.debug = val;
1267
1268         /*
1269          * Do it right away if it's already enabled, otherwise it will be done
1270          * when enabling the source.
1271          */
1272         if (dev_priv->psr.enabled)
1273                 psr_irq_control(dev_priv);
1274
1275         mutex_unlock(&dev_priv->psr.lock);
1276
1277         if (old_mode != mode)
1278                 ret = intel_psr_fastset_force(dev_priv);
1279
1280         return ret;
1281 }
1282
1283 static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
1284 {
1285         struct i915_psr *psr = &dev_priv->psr;
1286
1287         intel_psr_disable_locked(psr->dp);
1288         psr->sink_not_reliable = true;
1289         /* let's make sure that sink is awaken */
1290         drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1291 }
1292
1293 static void intel_psr_work(struct work_struct *work)
1294 {
1295         struct drm_i915_private *dev_priv =
1296                 container_of(work, typeof(*dev_priv), psr.work);
1297
1298         mutex_lock(&dev_priv->psr.lock);
1299
1300         if (!dev_priv->psr.enabled)
1301                 goto unlock;
1302
1303         if (READ_ONCE(dev_priv->psr.irq_aux_error))
1304                 intel_psr_handle_irq(dev_priv);
1305
1306         /*
1307          * We have to make sure PSR is ready for re-enable
1308          * otherwise it keeps disabled until next full enable/disable cycle.
1309          * PSR might take some time to get fully disabled
1310          * and be ready for re-enable.
1311          */
1312         if (!__psr_wait_for_idle_locked(dev_priv))
1313                 goto unlock;
1314
1315         /*
1316          * The delayed work can race with an invalidate hence we need to
1317          * recheck. Since psr_flush first clears this and then reschedules we
1318          * won't ever miss a flush when bailing out here.
1319          */
1320         if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
1321                 goto unlock;
1322
1323         intel_psr_activate(dev_priv->psr.dp);
1324 unlock:
1325         mutex_unlock(&dev_priv->psr.lock);
1326 }
1327
1328 /**
1329  * intel_psr_invalidate - Invalidade PSR
1330  * @dev_priv: i915 device
1331  * @frontbuffer_bits: frontbuffer plane tracking bits
1332  * @origin: which operation caused the invalidate
1333  *
1334  * Since the hardware frontbuffer tracking has gaps we need to integrate
1335  * with the software frontbuffer tracking. This function gets called every
1336  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
1337  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
1338  *
1339  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
1340  */
1341 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1342                           unsigned frontbuffer_bits, enum fb_op_origin origin)
1343 {
1344         if (!CAN_PSR(dev_priv))
1345                 return;
1346
1347         if (origin == ORIGIN_FLIP)
1348                 return;
1349
1350         mutex_lock(&dev_priv->psr.lock);
1351         if (!dev_priv->psr.enabled) {
1352                 mutex_unlock(&dev_priv->psr.lock);
1353                 return;
1354         }
1355
1356         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
1357         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1358
1359         if (frontbuffer_bits)
1360                 intel_psr_exit(dev_priv);
1361
1362         mutex_unlock(&dev_priv->psr.lock);
1363 }
1364
1365 /*
1366  * When we will be completely rely on PSR2 S/W tracking in future,
1367  * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
1368  * event also therefore tgl_dc3co_flush() require to be changed
1369  * accordingly in future.
1370  */
1371 static void
1372 tgl_dc3co_flush(struct drm_i915_private *dev_priv,
1373                 unsigned int frontbuffer_bits, enum fb_op_origin origin)
1374 {
1375         mutex_lock(&dev_priv->psr.lock);
1376
1377         if (!dev_priv->psr.dc3co_enabled)
1378                 goto unlock;
1379
1380         if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
1381                 goto unlock;
1382
1383         /*
1384          * At every frontbuffer flush flip event modified delay of delayed work,
1385          * when delayed work schedules that means display has been idle.
1386          */
1387         if (!(frontbuffer_bits &
1388             INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)))
1389                 goto unlock;
1390
1391         tgl_psr2_enable_dc3co(dev_priv);
1392         mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work,
1393                          dev_priv->psr.dc3co_exit_delay);
1394
1395 unlock:
1396         mutex_unlock(&dev_priv->psr.lock);
1397 }
1398
1399 /**
1400  * intel_psr_flush - Flush PSR
1401  * @dev_priv: i915 device
1402  * @frontbuffer_bits: frontbuffer plane tracking bits
1403  * @origin: which operation caused the flush
1404  *
1405  * Since the hardware frontbuffer tracking has gaps we need to integrate
1406  * with the software frontbuffer tracking. This function gets called every
1407  * time frontbuffer rendering has completed and flushed out to memory. PSR
1408  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
1409  *
1410  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
1411  */
1412 void intel_psr_flush(struct drm_i915_private *dev_priv,
1413                      unsigned frontbuffer_bits, enum fb_op_origin origin)
1414 {
1415         if (!CAN_PSR(dev_priv))
1416                 return;
1417
1418         if (origin == ORIGIN_FLIP) {
1419                 tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin);
1420                 return;
1421         }
1422
1423         mutex_lock(&dev_priv->psr.lock);
1424         if (!dev_priv->psr.enabled) {
1425                 mutex_unlock(&dev_priv->psr.lock);
1426                 return;
1427         }
1428
1429         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
1430         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
1431
1432         /* By definition flush = invalidate + flush */
1433         if (frontbuffer_bits)
1434                 psr_force_hw_tracking_exit(dev_priv);
1435
1436         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
1437                 schedule_work(&dev_priv->psr.work);
1438         mutex_unlock(&dev_priv->psr.lock);
1439 }
1440
1441 /**
1442  * intel_psr_init - Init basic PSR work and mutex.
1443  * @dev_priv: i915 device private
1444  *
1445  * This function is  called only once at driver load to initialize basic
1446  * PSR stuff.
1447  */
1448 void intel_psr_init(struct drm_i915_private *dev_priv)
1449 {
1450         if (!HAS_PSR(dev_priv))
1451                 return;
1452
1453         if (!dev_priv->psr.sink_support)
1454                 return;
1455
1456         if (IS_HASWELL(dev_priv))
1457                 /*
1458                  * HSW don't have PSR registers on the same space as transcoder
1459                  * so set this to a value that when subtract to the register
1460                  * in transcoder space results in the right offset for HSW
1461                  */
1462                 dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
1463
1464         if (i915_modparams.enable_psr == -1)
1465                 if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
1466                         i915_modparams.enable_psr = 0;
1467
1468         /* Set link_standby x link_off defaults */
1469         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1470                 /* HSW and BDW require workarounds that we don't implement. */
1471                 dev_priv->psr.link_standby = false;
1472         else if (INTEL_GEN(dev_priv) < 12)
1473                 /* For new platforms up to TGL let's respect VBT back again */
1474                 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
1475
1476         INIT_WORK(&dev_priv->psr.work, intel_psr_work);
1477         INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work);
1478         mutex_init(&dev_priv->psr.lock);
1479 }
1480
1481 static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
1482                                            u8 *status, u8 *error_status)
1483 {
1484         struct drm_dp_aux *aux = &intel_dp->aux;
1485         int ret;
1486
1487         ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
1488         if (ret != 1)
1489                 return ret;
1490
1491         ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
1492         if (ret != 1)
1493                 return ret;
1494
1495         *status = *status & DP_PSR_SINK_STATE_MASK;
1496
1497         return 0;
1498 }
1499
1500 static void psr_alpm_check(struct intel_dp *intel_dp)
1501 {
1502         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1503         struct drm_dp_aux *aux = &intel_dp->aux;
1504         struct i915_psr *psr = &dev_priv->psr;
1505         u8 val;
1506         int r;
1507
1508         if (!psr->psr2_enabled)
1509                 return;
1510
1511         r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
1512         if (r != 1) {
1513                 drm_err(&dev_priv->drm, "Error reading ALPM status\n");
1514                 return;
1515         }
1516
1517         if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
1518                 intel_psr_disable_locked(intel_dp);
1519                 psr->sink_not_reliable = true;
1520                 drm_dbg_kms(&dev_priv->drm,
1521                             "ALPM lock timeout error, disabling PSR\n");
1522
1523                 /* Clearing error */
1524                 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
1525         }
1526 }
1527
1528 static void psr_capability_changed_check(struct intel_dp *intel_dp)
1529 {
1530         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1531         struct i915_psr *psr = &dev_priv->psr;
1532         u8 val;
1533         int r;
1534
1535         r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
1536         if (r != 1) {
1537                 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
1538                 return;
1539         }
1540
1541         if (val & DP_PSR_CAPS_CHANGE) {
1542                 intel_psr_disable_locked(intel_dp);
1543                 psr->sink_not_reliable = true;
1544                 drm_dbg_kms(&dev_priv->drm,
1545                             "Sink PSR capability changed, disabling PSR\n");
1546
1547                 /* Clearing it */
1548                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
1549         }
1550 }
1551
1552 void intel_psr_short_pulse(struct intel_dp *intel_dp)
1553 {
1554         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1555         struct i915_psr *psr = &dev_priv->psr;
1556         u8 status, error_status;
1557         const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
1558                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
1559                           DP_PSR_LINK_CRC_ERROR;
1560
1561         if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
1562                 return;
1563
1564         mutex_lock(&psr->lock);
1565
1566         if (!psr->enabled || psr->dp != intel_dp)
1567                 goto exit;
1568
1569         if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
1570                 drm_err(&dev_priv->drm,
1571                         "Error reading PSR status or error status\n");
1572                 goto exit;
1573         }
1574
1575         if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
1576                 intel_psr_disable_locked(intel_dp);
1577                 psr->sink_not_reliable = true;
1578         }
1579
1580         if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
1581                 drm_dbg_kms(&dev_priv->drm,
1582                             "PSR sink internal error, disabling PSR\n");
1583         if (error_status & DP_PSR_RFB_STORAGE_ERROR)
1584                 drm_dbg_kms(&dev_priv->drm,
1585                             "PSR RFB storage error, disabling PSR\n");
1586         if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
1587                 drm_dbg_kms(&dev_priv->drm,
1588                             "PSR VSC SDP uncorrectable error, disabling PSR\n");
1589         if (error_status & DP_PSR_LINK_CRC_ERROR)
1590                 drm_dbg_kms(&dev_priv->drm,
1591                             "PSR Link CRC error, disabling PSR\n");
1592
1593         if (error_status & ~errors)
1594                 drm_err(&dev_priv->drm,
1595                         "PSR_ERROR_STATUS unhandled errors %x\n",
1596                         error_status & ~errors);
1597         /* clear status register */
1598         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
1599
1600         psr_alpm_check(intel_dp);
1601         psr_capability_changed_check(intel_dp);
1602
1603 exit:
1604         mutex_unlock(&psr->lock);
1605 }
1606
1607 bool intel_psr_enabled(struct intel_dp *intel_dp)
1608 {
1609         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1610         bool ret;
1611
1612         if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
1613                 return false;
1614
1615         mutex_lock(&dev_priv->psr.lock);
1616         ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
1617         mutex_unlock(&dev_priv->psr.lock);
1618
1619         return ret;
1620 }
1621
1622 void intel_psr_atomic_check(struct drm_connector *connector,
1623                             struct drm_connector_state *old_state,
1624                             struct drm_connector_state *new_state)
1625 {
1626         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1627         struct intel_connector *intel_connector;
1628         struct intel_digital_port *dig_port;
1629         struct drm_crtc_state *crtc_state;
1630
1631         if (!CAN_PSR(dev_priv) || !new_state->crtc ||
1632             dev_priv->psr.initially_probed)
1633                 return;
1634
1635         intel_connector = to_intel_connector(connector);
1636         dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector));
1637         if (dev_priv->psr.dp != &dig_port->dp)
1638                 return;
1639
1640         crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
1641                                                    new_state->crtc);
1642         crtc_state->mode_changed = true;
1643         dev_priv->psr.initially_probed = true;
1644 }