drivers/gpu/drm/i915/display/intel_pps.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "intel_display_types.h"
   8 #include "intel_dp.h"
   9 #include "intel_pps.h"
  10
  11 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
  12                                       enum pipe pipe);
  13 static void
  14 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
  15 static void
  16 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
  17                                               bool force_disable_vdd);
  18
  19 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
  20 {
  21         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  22         intel_wakeref_t wakeref;
  23
  24         /*
  25          * See intel_power_sequencer_reset() why we need
  26          * a power domain reference here.
  27          */
  28         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
  29         mutex_lock(&dev_priv->pps_mutex);
  30
  31         return wakeref;
  32 }
  33
  34 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
  35                                  intel_wakeref_t wakeref)
  36 {
  37         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  38
  39         mutex_unlock(&dev_priv->pps_mutex);
  40         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
  41
  42         return 0;
  43 }
  44
  45 static void
  46 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
  47 {
  48         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  49         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  50         enum pipe pipe = intel_dp->pps_pipe;
  51         bool pll_enabled, release_cl_override = false;
  52         enum dpio_phy phy = DPIO_PHY(pipe);
  53         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
  54         u32 DP;
  55
  56         if (drm_WARN(&dev_priv->drm,
  57                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
  58                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
  59                      pipe_name(pipe), dig_port->base.base.base.id,
  60                      dig_port->base.base.name))
  61                 return;
  62
  63         drm_dbg_kms(&dev_priv->drm,
  64                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
  65                     pipe_name(pipe), dig_port->base.base.base.id,
  66                     dig_port->base.base.name);
  67
  68         /* Preserve the BIOS-computed detected bit. This is
  69          * supposed to be read-only.
  70          */
  71         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
  72         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  73         DP |= DP_PORT_WIDTH(1);
  74         DP |= DP_LINK_TRAIN_PAT_1;
  75
  76         if (IS_CHERRYVIEW(dev_priv))
  77                 DP |= DP_PIPE_SEL_CHV(pipe);
  78         else
  79                 DP |= DP_PIPE_SEL(pipe);
  80
  81         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
  82
  83         /*
  84          * The DPLL for the pipe must be enabled for this to work.
  85          * So enable temporarily it if it's not already enabled.
  86          */
  87         if (!pll_enabled) {
  88                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
  89                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
  90
  91                 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
  92                         drm_err(&dev_priv->drm,
  93                                 "Failed to force on pll for pipe %c!\n",
  94                                 pipe_name(pipe));
  95                         return;
  96                 }
  97         }
  98
  99         /*
 100          * Similar magic as in intel_dp_enable_port().
 101          * We _must_ do this port enable + disable trick
 102          * to make this power sequencer lock onto the port.
 103          * Otherwise even VDD force bit won't work.
 104          */
 105         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 106         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 107
 108         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 109         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 110
 111         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 112         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 113
 114         if (!pll_enabled) {
 115                 vlv_force_pll_off(dev_priv, pipe);
 116
 117                 if (release_cl_override)
 118                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 119         }
 120 }
 121
 122 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 123 {
 124         struct intel_encoder *encoder;
 125         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 126
 127         /*
 128          * We don't have power sequencer currently.
 129          * Pick one that's not used by other ports.
 130          */
 131         for_each_intel_dp(&dev_priv->drm, encoder) {
 132                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 133
 134                 if (encoder->type == INTEL_OUTPUT_EDP) {
 135                         drm_WARN_ON(&dev_priv->drm,
 136                                     intel_dp->active_pipe != INVALID_PIPE &&
 137                                     intel_dp->active_pipe !=
 138                                     intel_dp->pps_pipe);
 139
 140                         if (intel_dp->pps_pipe != INVALID_PIPE)
 141                                 pipes &= ~(1 << intel_dp->pps_pipe);
 142                 } else {
 143                         drm_WARN_ON(&dev_priv->drm,
 144                                     intel_dp->pps_pipe != INVALID_PIPE);
 145
 146                         if (intel_dp->active_pipe != INVALID_PIPE)
 147                                 pipes &= ~(1 << intel_dp->active_pipe);
 148                 }
 149         }
 150
 151         if (pipes == 0)
 152                 return INVALID_PIPE;
 153
 154         return ffs(pipes) - 1;
 155 }
 156
 157 static enum pipe
 158 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 159 {
 160         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 161         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 162         enum pipe pipe;
 163
 164         lockdep_assert_held(&dev_priv->pps_mutex);
 165
 166         /* We should never land here with regular DP ports */
 167         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 168
 169         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
 170                     intel_dp->active_pipe != intel_dp->pps_pipe);
 171
 172         if (intel_dp->pps_pipe != INVALID_PIPE)
 173                 return intel_dp->pps_pipe;
 174
 175         pipe = vlv_find_free_pps(dev_priv);
 176
 177         /*
 178          * Didn't find one. This should not happen since there
 179          * are two power sequencers and up to two eDP ports.
 180          */
 181         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
 182                 pipe = PIPE_A;
 183
 184         vlv_steal_power_sequencer(dev_priv, pipe);
 185         intel_dp->pps_pipe = pipe;
 186
 187         drm_dbg_kms(&dev_priv->drm,
 188                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 189                     pipe_name(intel_dp->pps_pipe),
 190                     dig_port->base.base.base.id,
 191                     dig_port->base.base.name);
 192
 193         /* init power sequencer on this pipe and port */
 194         intel_dp_init_panel_power_sequencer(intel_dp);
 195         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 196
 197         /*
 198          * Even vdd force doesn't work until we've made
 199          * the power sequencer lock in on the port.
 200          */
 201         vlv_power_sequencer_kick(intel_dp);
 202
 203         return intel_dp->pps_pipe;
 204 }
 205
 206 static int
 207 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 208 {
 209         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 210         int backlight_controller = dev_priv->vbt.backlight.controller;
 211
 212         lockdep_assert_held(&dev_priv->pps_mutex);
 213
 214         /* We should never land here with regular DP ports */
 215         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 216
 217         if (!intel_dp->pps_reset)
 218                 return backlight_controller;
 219
 220         intel_dp->pps_reset = false;
 221
 222         /*
 223          * Only the HW needs to be reprogrammed, the SW state is fixed and
 224          * has been setup during connector init.
 225          */
 226         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 227
 228         return backlight_controller;
 229 }
 230
 231 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 232                                enum pipe pipe);
 233
 234 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 235                                enum pipe pipe)
 236 {
 237         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
 238 }
 239
 240 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 241                                 enum pipe pipe)
 242 {
 243         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 244 }
 245
 246 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 247                          enum pipe pipe)
 248 {
 249         return true;
 250 }
 251
 252 static enum pipe
 253 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 254                      enum port port,
 255                      vlv_pipe_check pipe_check)
 256 {
 257         enum pipe pipe;
 258
 259         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 260                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
 261                         PANEL_PORT_SELECT_MASK;
 262
 263                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 264                         continue;
 265
 266                 if (!pipe_check(dev_priv, pipe))
 267                         continue;
 268
 269                 return pipe;
 270         }
 271
 272         return INVALID_PIPE;
 273 }
 274
 275 static void
 276 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 277 {
 278         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 279         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 280         enum port port = dig_port->base.port;
 281
 282         lockdep_assert_held(&dev_priv->pps_mutex);
 283
 284         /* try to find a pipe with this port selected */
 285         /* first pick one where the panel is on */
 286         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 287                                                   vlv_pipe_has_pp_on);
 288         /* didn't find one? pick one where vdd is on */
 289         if (intel_dp->pps_pipe == INVALID_PIPE)
 290                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 291                                                           vlv_pipe_has_vdd_on);
 292         /* didn't find one? pick one with just the correct port */
 293         if (intel_dp->pps_pipe == INVALID_PIPE)
 294                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 295                                                           vlv_pipe_any);
 296
 297         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 298         if (intel_dp->pps_pipe == INVALID_PIPE) {
 299                 drm_dbg_kms(&dev_priv->drm,
 300                             "no initial power sequencer for [ENCODER:%d:%s]\n",
 301                             dig_port->base.base.base.id,
 302                             dig_port->base.base.name);
 303                 return;
 304         }
 305
 306         drm_dbg_kms(&dev_priv->drm,
 307                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
 308                     dig_port->base.base.base.id,
 309                     dig_port->base.base.name,
 310                     pipe_name(intel_dp->pps_pipe));
 311
 312         intel_dp_init_panel_power_sequencer(intel_dp);
 313         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 314 }
 315
 316 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 317 {
 318         struct intel_encoder *encoder;
 319
 320         if (drm_WARN_ON(&dev_priv->drm,
 321                         !(IS_VALLEYVIEW(dev_priv) ||
 322                           IS_CHERRYVIEW(dev_priv) ||
 323                           IS_GEN9_LP(dev_priv))))
 324                 return;
 325
 326         /*
 327          * We can't grab pps_mutex here due to deadlock with power_domain
 328          * mutex when power_domain functions are called while holding pps_mutex.
 329          * That also means that in order to use pps_pipe the code needs to
 330          * hold both a power domain reference and pps_mutex, and the power domain
 331          * reference get/put must be done while _not_ holding pps_mutex.
 332          * pps_{lock,unlock}() do these steps in the correct order, so one
 333          * should use them always.
 334          */
 335
 336         for_each_intel_dp(&dev_priv->drm, encoder) {
 337                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 338
 339                 drm_WARN_ON(&dev_priv->drm,
 340                             intel_dp->active_pipe != INVALID_PIPE);
 341
 342                 if (encoder->type != INTEL_OUTPUT_EDP)
 343                         continue;
 344
 345                 if (IS_GEN9_LP(dev_priv))
 346                         intel_dp->pps_reset = true;
 347                 else
 348                         intel_dp->pps_pipe = INVALID_PIPE;
 349         }
 350 }
 351
 352 struct pps_registers {
 353         i915_reg_t pp_ctrl;
 354         i915_reg_t pp_stat;
 355         i915_reg_t pp_on;
 356         i915_reg_t pp_off;
 357         i915_reg_t pp_div;
 358 };
 359
 360 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 361                                     struct pps_registers *regs)
 362 {
 363         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 364         int pps_idx = 0;
 365
 366         memset(regs, 0, sizeof(*regs));
 367
 368         if (IS_GEN9_LP(dev_priv))
 369                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 370         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 371                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 372
 373         regs->pp_ctrl = PP_CONTROL(pps_idx);
 374         regs->pp_stat = PP_STATUS(pps_idx);
 375         regs->pp_on = PP_ON_DELAYS(pps_idx);
 376         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 377
 378         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 379         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 380                 regs->pp_div = INVALID_MMIO_REG;
 381         else
 382                 regs->pp_div = PP_DIVISOR(pps_idx);
 383 }
 384
 385 static i915_reg_t
 386 _pp_ctrl_reg(struct intel_dp *intel_dp)
 387 {
 388         struct pps_registers regs;
 389
 390         intel_pps_get_registers(intel_dp, &regs);
 391
 392         return regs.pp_ctrl;
 393 }
 394
 395 static i915_reg_t
 396 _pp_stat_reg(struct intel_dp *intel_dp)
 397 {
 398         struct pps_registers regs;
 399
 400         intel_pps_get_registers(intel_dp, &regs);
 401
 402         return regs.pp_stat;
 403 }
 404
 405 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 406 {
 407         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 408
 409         lockdep_assert_held(&dev_priv->pps_mutex);
 410
 411         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 412             intel_dp->pps_pipe == INVALID_PIPE)
 413                 return false;
 414
 415         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
 416 }
 417
 418 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 419 {
 420         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 421
 422         lockdep_assert_held(&dev_priv->pps_mutex);
 423
 424         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 425             intel_dp->pps_pipe == INVALID_PIPE)
 426                 return false;
 427
 428         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 429 }
 430
 431 void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
 432 {
 433         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 434
 435         if (!intel_dp_is_edp(intel_dp))
 436                 return;
 437
 438         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 439                 drm_WARN(&dev_priv->drm, 1,
 440                          "eDP powered off while attempting aux channel communication.\n");
 441                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
 442                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
 443                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
 444         }
 445 }
 446
 447 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 448 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 449
 450 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
 451 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
 452
 453 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 454 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 455
 456 static void intel_pps_verify_state(struct intel_dp *intel_dp);
 457
 458 static void wait_panel_status(struct intel_dp *intel_dp,
 459                                        u32 mask,
 460                                        u32 value)
 461 {
 462         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 463         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 464
 465         lockdep_assert_held(&dev_priv->pps_mutex);
 466
 467         intel_pps_verify_state(intel_dp);
 468
 469         pp_stat_reg = _pp_stat_reg(intel_dp);
 470         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 471
 472         drm_dbg_kms(&dev_priv->drm,
 473                     "mask %08x value %08x status %08x control %08x\n",
 474                     mask, value,
 475                     intel_de_read(dev_priv, pp_stat_reg),
 476                     intel_de_read(dev_priv, pp_ctrl_reg));
 477
 478         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
 479                                        mask, value, 5000))
 480                 drm_err(&dev_priv->drm,
 481                         "Panel status timeout: status %08x control %08x\n",
 482                         intel_de_read(dev_priv, pp_stat_reg),
 483                         intel_de_read(dev_priv, pp_ctrl_reg));
 484
 485         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
 486 }
 487
 488 static void wait_panel_on(struct intel_dp *intel_dp)
 489 {
 490         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 491
 492         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
 493         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 494 }
 495
 496 static void wait_panel_off(struct intel_dp *intel_dp)
 497 {
 498         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 499
 500         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
 501         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 502 }
 503
 504 void wait_panel_power_cycle(struct intel_dp *intel_dp)
 505 {
 506         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 507         ktime_t panel_power_on_time;
 508         s64 panel_power_off_duration;
 509
 510         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
 511
 512         /* take the difference of currrent time and panel power off time
 513          * and then make panel wait for t11_t12 if needed. */
 514         panel_power_on_time = ktime_get_boottime();
 515         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
 516
 517         /* When we disable the VDD override bit last we have to do the manual
 518          * wait. */
 519         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
 520                 wait_remaining_ms_from_jiffies(jiffies,
 521                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
 522
 523         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 524 }
 525
 526 static void wait_backlight_on(struct intel_dp *intel_dp)
 527 {
 528         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
 529                                        intel_dp->backlight_on_delay);
 530 }
 531
 532 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
 533 {
 534         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
 535                                        intel_dp->backlight_off_delay);
 536 }
 537
 538 /* Read the current pp_control value, unlocking the register if it
 539  * is locked
 540  */
 541
 542 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
 543 {
 544         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 545         u32 control;
 546
 547         lockdep_assert_held(&dev_priv->pps_mutex);
 548
 549         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
 550         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
 551                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
 552                 control &= ~PANEL_UNLOCK_MASK;
 553                 control |= PANEL_UNLOCK_REGS;
 554         }
 555         return control;
 556 }
 557
 558 /*
 559  * Must be paired with intel_pps_vdd_off_unlocked().
 560  * Must hold pps_mutex around the whole on/off sequence.
 561  * Can be nested with intel_pps_vdd_{on,off}() calls.
 562  */
 563 bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
 564 {
 565         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 566         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 567         u32 pp;
 568         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 569         bool need_to_disable = !intel_dp->want_panel_vdd;
 570
 571         lockdep_assert_held(&dev_priv->pps_mutex);
 572
 573         if (!intel_dp_is_edp(intel_dp))
 574                 return false;
 575
 576         cancel_delayed_work(&intel_dp->panel_vdd_work);
 577         intel_dp->want_panel_vdd = true;
 578
 579         if (edp_have_panel_vdd(intel_dp))
 580                 return need_to_disable;
 581
 582         drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
 583         intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
 584                                                         intel_aux_power_domain(dig_port));
 585
 586         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
 587                     dig_port->base.base.base.id,
 588                     dig_port->base.base.name);
 589
 590         if (!edp_have_panel_power(intel_dp))
 591                 wait_panel_power_cycle(intel_dp);
 592
 593         pp = ilk_get_pp_control(intel_dp);
 594         pp |= EDP_FORCE_VDD;
 595
 596         pp_stat_reg = _pp_stat_reg(intel_dp);
 597         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 598
 599         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 600         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 601         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 602                     intel_de_read(dev_priv, pp_stat_reg),
 603                     intel_de_read(dev_priv, pp_ctrl_reg));
 604         /*
 605          * If the panel wasn't on, delay before accessing aux channel
 606          */
 607         if (!edp_have_panel_power(intel_dp)) {
 608                 drm_dbg_kms(&dev_priv->drm,
 609                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
 610                             dig_port->base.base.base.id,
 611                             dig_port->base.base.name);
 612                 msleep(intel_dp->panel_power_up_delay);
 613         }
 614
 615         return need_to_disable;
 616 }
 617
 618 /*
 619  * Must be paired with intel_pps_off().
 620  * Nested calls to these functions are not allowed since
 621  * we drop the lock. Caller must use some higher level
 622  * locking to prevent nested calls from other threads.
 623  */
 624 void intel_pps_vdd_on(struct intel_dp *intel_dp)
 625 {
 626         intel_wakeref_t wakeref;
 627         bool vdd;
 628
 629         if (!intel_dp_is_edp(intel_dp))
 630                 return;
 631
 632         vdd = false;
 633         with_intel_pps_lock(intel_dp, wakeref)
 634                 vdd = intel_pps_vdd_on_unlocked(intel_dp);
 635         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
 636                         dp_to_dig_port(intel_dp)->base.base.base.id,
 637                         dp_to_dig_port(intel_dp)->base.base.name);
 638 }
 639
 640 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
 641 {
 642         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 643         struct intel_digital_port *dig_port =
 644                 dp_to_dig_port(intel_dp);
 645         u32 pp;
 646         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 647
 648         lockdep_assert_held(&dev_priv->pps_mutex);
 649
 650         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
 651
 652         if (!edp_have_panel_vdd(intel_dp))
 653                 return;
 654
 655         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
 656                     dig_port->base.base.base.id,
 657                     dig_port->base.base.name);
 658
 659         pp = ilk_get_pp_control(intel_dp);
 660         pp &= ~EDP_FORCE_VDD;
 661
 662         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 663         pp_stat_reg = _pp_stat_reg(intel_dp);
 664
 665         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 666         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 667
 668         /* Make sure sequencer is idle before allowing subsequent activity */
 669         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 670                     intel_de_read(dev_priv, pp_stat_reg),
 671                     intel_de_read(dev_priv, pp_ctrl_reg));
 672
 673         if ((pp & PANEL_POWER_ON) == 0)
 674                 intel_dp->panel_power_off_time = ktime_get_boottime();
 675
 676         intel_display_power_put(dev_priv,
 677                                 intel_aux_power_domain(dig_port),
 678                                 fetch_and_zero(&intel_dp->vdd_wakeref));
 679 }
 680
 681 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
 682 {
 683         intel_wakeref_t wakeref;
 684
 685         if (!intel_dp_is_edp(intel_dp))
 686                 return;
 687
 688         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
 689         /*
 690          * vdd might still be enabled due to the delayed vdd off.
 691          * Make sure vdd is actually turned off here.
 692          */
 693         with_intel_pps_lock(intel_dp, wakeref)
 694                 intel_pps_vdd_off_sync_unlocked(intel_dp);
 695 }
 696
 697 static void edp_panel_vdd_work(struct work_struct *__work)
 698 {
 699         struct intel_dp *intel_dp =
 700                 container_of(to_delayed_work(__work),
 701                              struct intel_dp, panel_vdd_work);
 702         intel_wakeref_t wakeref;
 703
 704         with_intel_pps_lock(intel_dp, wakeref) {
 705                 if (!intel_dp->want_panel_vdd)
 706                         intel_pps_vdd_off_sync_unlocked(intel_dp);
 707         }
 708 }
 709
 710 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
 711 {
 712         unsigned long delay;
 713
 714         /*
 715          * Queue the timer to fire a long time from now (relative to the power
 716          * down delay) to keep the panel power up across a sequence of
 717          * operations.
 718          */
 719         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
 720         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
 721 }
 722
 723 /*
 724  * Must be paired with edp_panel_vdd_on().
 725  * Must hold pps_mutex around the whole on/off sequence.
 726  * Can be nested with intel_pps_vdd_{on,off}() calls.
 727  */
 728 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
 729 {
 730         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 731
 732         lockdep_assert_held(&dev_priv->pps_mutex);
 733
 734         if (!intel_dp_is_edp(intel_dp))
 735                 return;
 736
 737         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
 738                         dp_to_dig_port(intel_dp)->base.base.base.id,
 739                         dp_to_dig_port(intel_dp)->base.base.name);
 740
 741         intel_dp->want_panel_vdd = false;
 742
 743         if (sync)
 744                 intel_pps_vdd_off_sync_unlocked(intel_dp);
 745         else
 746                 edp_panel_vdd_schedule_off(intel_dp);
 747 }
 748
 749 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
 750 {
 751         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 752         u32 pp;
 753         i915_reg_t pp_ctrl_reg;
 754
 755         lockdep_assert_held(&dev_priv->pps_mutex);
 756
 757         if (!intel_dp_is_edp(intel_dp))
 758                 return;
 759
 760         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
 761                     dp_to_dig_port(intel_dp)->base.base.base.id,
 762                     dp_to_dig_port(intel_dp)->base.base.name);
 763
 764         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
 765                      "[ENCODER:%d:%s] panel power already on\n",
 766                      dp_to_dig_port(intel_dp)->base.base.base.id,
 767                      dp_to_dig_port(intel_dp)->base.base.name))
 768                 return;
 769
 770         wait_panel_power_cycle(intel_dp);
 771
 772         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 773         pp = ilk_get_pp_control(intel_dp);
 774         if (IS_GEN(dev_priv, 5)) {
 775                 /* ILK workaround: disable reset around power sequence */
 776                 pp &= ~PANEL_POWER_RESET;
 777                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 778                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 779         }
 780
 781         pp |= PANEL_POWER_ON;
 782         if (!IS_GEN(dev_priv, 5))
 783                 pp |= PANEL_POWER_RESET;
 784
 785         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 786         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 787
 788         wait_panel_on(intel_dp);
 789         intel_dp->last_power_on = jiffies;
 790
 791         if (IS_GEN(dev_priv, 5)) {
 792                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 793                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 794                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 795         }
 796 }
 797
 798 void intel_pps_on(struct intel_dp *intel_dp)
 799 {
 800         intel_wakeref_t wakeref;
 801
 802         if (!intel_dp_is_edp(intel_dp))
 803                 return;
 804
 805         with_intel_pps_lock(intel_dp, wakeref)
 806                 intel_pps_on_unlocked(intel_dp);
 807 }
 808
 809 void intel_pps_off_unlocked(struct intel_dp *intel_dp)
 810 {
 811         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 812         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 813         u32 pp;
 814         i915_reg_t pp_ctrl_reg;
 815
 816         lockdep_assert_held(&dev_priv->pps_mutex);
 817
 818         if (!intel_dp_is_edp(intel_dp))
 819                 return;
 820
 821         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
 822                     dig_port->base.base.base.id, dig_port->base.base.name);
 823
 824         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
 825                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
 826                  dig_port->base.base.base.id, dig_port->base.base.name);
 827
 828         pp = ilk_get_pp_control(intel_dp);
 829         /* We need to switch off panel power _and_ force vdd, for otherwise some
 830          * panels get very unhappy and cease to work. */
 831         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
 832                 EDP_BLC_ENABLE);
 833
 834         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 835
 836         intel_dp->want_panel_vdd = false;
 837
 838         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 839         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 840
 841         wait_panel_off(intel_dp);
 842         intel_dp->panel_power_off_time = ktime_get_boottime();
 843
 844         /* We got a reference when we enabled the VDD. */
 845         intel_display_power_put(dev_priv,
 846                                 intel_aux_power_domain(dig_port),
 847                                 fetch_and_zero(&intel_dp->vdd_wakeref));
 848 }
 849
 850 void intel_pps_off(struct intel_dp *intel_dp)
 851 {
 852         intel_wakeref_t wakeref;
 853
 854         if (!intel_dp_is_edp(intel_dp))
 855                 return;
 856
 857         with_intel_pps_lock(intel_dp, wakeref)
 858                 intel_pps_off_unlocked(intel_dp);
 859 }
 860
 861 /* Enable backlight in the panel power control. */
 862 void intel_pps_backlight_on(struct intel_dp *intel_dp)
 863 {
 864         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 865         intel_wakeref_t wakeref;
 866
 867         /*
 868          * If we enable the backlight right away following a panel power
 869          * on, we may see slight flicker as the panel syncs with the eDP
 870          * link.  So delay a bit to make sure the image is solid before
 871          * allowing it to appear.
 872          */
 873         wait_backlight_on(intel_dp);
 874
 875         with_intel_pps_lock(intel_dp, wakeref) {
 876                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 877                 u32 pp;
 878
 879                 pp = ilk_get_pp_control(intel_dp);
 880                 pp |= EDP_BLC_ENABLE;
 881
 882                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 883                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 884         }
 885 }
 886
 887 /* Disable backlight in the panel power control. */
 888 void intel_pps_backlight_off(struct intel_dp *intel_dp)
 889 {
 890         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 891         intel_wakeref_t wakeref;
 892
 893         if (!intel_dp_is_edp(intel_dp))
 894                 return;
 895
 896         with_intel_pps_lock(intel_dp, wakeref) {
 897                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 898                 u32 pp;
 899
 900                 pp = ilk_get_pp_control(intel_dp);
 901                 pp &= ~EDP_BLC_ENABLE;
 902
 903                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 904                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 905         }
 906
 907         intel_dp->last_backlight_off = jiffies;
 908         edp_wait_backlight_off(intel_dp);
 909 }
 910
 911 /*
 912  * Hook for controlling the panel power control backlight through the bl_power
 913  * sysfs attribute. Take care to handle multiple calls.
 914  */
 915 void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
 916 {
 917         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 918         struct intel_dp *intel_dp = intel_attached_dp(connector);
 919         intel_wakeref_t wakeref;
 920         bool is_enabled;
 921
 922         is_enabled = false;
 923         with_intel_pps_lock(intel_dp, wakeref)
 924                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
 925         if (is_enabled == enable)
 926                 return;
 927
 928         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
 929                     enable ? "enable" : "disable");
 930
 931         if (enable)
 932                 intel_pps_backlight_on(intel_dp);
 933         else
 934                 intel_pps_backlight_off(intel_dp);
 935 }
 936
 937 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
 938 {
 939         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 940         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 941         enum pipe pipe = intel_dp->pps_pipe;
 942         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
 943
 944         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
 945
 946         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
 947                 return;
 948
 949         intel_pps_vdd_off_sync_unlocked(intel_dp);
 950
 951         /*
 952          * VLV seems to get confused when multiple power sequencers
 953          * have the same port selected (even if only one has power/vdd
 954          * enabled). The failure manifests as vlv_wait_port_ready() failing
 955          * CHV on the other hand doesn't seem to mind having the same port
 956          * selected in multiple power sequencers, but let's clear the
 957          * port select always when logically disconnecting a power sequencer
 958          * from a port.
 959          */
 960         drm_dbg_kms(&dev_priv->drm,
 961                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
 962                     pipe_name(pipe), dig_port->base.base.base.id,
 963                     dig_port->base.base.name);
 964         intel_de_write(dev_priv, pp_on_reg, 0);
 965         intel_de_posting_read(dev_priv, pp_on_reg);
 966
 967         intel_dp->pps_pipe = INVALID_PIPE;
 968 }
 969
 970 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 971                                       enum pipe pipe)
 972 {
 973         struct intel_encoder *encoder;
 974
 975         lockdep_assert_held(&dev_priv->pps_mutex);
 976
 977         for_each_intel_dp(&dev_priv->drm, encoder) {
 978                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 979
 980                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
 981                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
 982                          pipe_name(pipe), encoder->base.base.id,
 983                          encoder->base.name);
 984
 985                 if (intel_dp->pps_pipe != pipe)
 986                         continue;
 987
 988                 drm_dbg_kms(&dev_priv->drm,
 989                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
 990                             pipe_name(pipe), encoder->base.base.id,
 991                             encoder->base.name);
 992
 993                 /* make sure vdd is off before we steal it */
 994                 vlv_detach_power_sequencer(intel_dp);
 995         }
 996 }
 997
 998 void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 999                                     const struct intel_crtc_state *crtc_state)
1000 {
1001         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1002         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1003         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1004
1005         lockdep_assert_held(&dev_priv->pps_mutex);
1006
1007         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
1008
1009         if (intel_dp->pps_pipe != INVALID_PIPE &&
1010             intel_dp->pps_pipe != crtc->pipe) {
1011                 /*
1012                  * If another power sequencer was being used on this
1013                  * port previously make sure to turn off vdd there while
1014                  * we still have control of it.
1015                  */
1016                 vlv_detach_power_sequencer(intel_dp);
1017         }
1018
1019         /*
1020          * We may be stealing the power
1021          * sequencer from another port.
1022          */
1023         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
1024
1025         intel_dp->active_pipe = crtc->pipe;
1026
1027         if (!intel_dp_is_edp(intel_dp))
1028                 return;
1029
1030         /* now it's all ours */
1031         intel_dp->pps_pipe = crtc->pipe;
1032
1033         drm_dbg_kms(&dev_priv->drm,
1034                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
1035                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
1036                     encoder->base.name);
1037
1038         /* init power sequencer on this pipe and port */
1039         intel_dp_init_panel_power_sequencer(intel_dp);
1040         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
1041 }
1042
1043 static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
1044 {
1045         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1046         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1047
1048         lockdep_assert_held(&dev_priv->pps_mutex);
1049
1050         if (!edp_have_panel_vdd(intel_dp))
1051                 return;
1052
1053         /*
1054          * The VDD bit needs a power domain reference, so if the bit is
1055          * already enabled when we boot or resume, grab this reference and
1056          * schedule a vdd off, so we don't hold on to the reference
1057          * indefinitely.
1058          */
1059         drm_dbg_kms(&dev_priv->drm,
1060                     "VDD left on by BIOS, adjusting state tracking\n");
1061         drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
1062         intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
1063                                                         intel_aux_power_domain(dig_port));
1064
1065         edp_panel_vdd_schedule_off(intel_dp);
1066 }
1067
1068 bool intel_pps_have_power(struct intel_dp *intel_dp)
1069 {
1070         intel_wakeref_t wakeref;
1071         bool have_power = false;
1072
1073         with_intel_pps_lock(intel_dp, wakeref) {
1074                 have_power = edp_have_panel_power(intel_dp) &&
1075                                                   edp_have_panel_vdd(intel_dp);
1076         }
1077
1078         return have_power;
1079 }
1080
1081 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
1082 {
1083         intel_dp->panel_power_off_time = ktime_get_boottime();
1084         intel_dp->last_power_on = jiffies;
1085         intel_dp->last_backlight_off = jiffies;
1086 }
1087
1088 static void
1089 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
1090 {
1091         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1092         u32 pp_on, pp_off, pp_ctl;
1093         struct pps_registers regs;
1094
1095         intel_pps_get_registers(intel_dp, &regs);
1096
1097         pp_ctl = ilk_get_pp_control(intel_dp);
1098
1099         /* Ensure PPS is unlocked */
1100         if (!HAS_DDI(dev_priv))
1101                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1102
1103         pp_on = intel_de_read(dev_priv, regs.pp_on);
1104         pp_off = intel_de_read(dev_priv, regs.pp_off);
1105
1106         /* Pull timing values out of registers */
1107         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1108         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1109         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1110         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1111
1112         if (i915_mmio_reg_valid(regs.pp_div)) {
1113                 u32 pp_div;
1114
1115                 pp_div = intel_de_read(dev_priv, regs.pp_div);
1116
1117                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
1118         } else {
1119                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
1120         }
1121 }
1122
1123 static void
1124 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
1125 {
1126         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1127                       state_name,
1128                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
1129 }
1130
1131 static void
1132 intel_pps_verify_state(struct intel_dp *intel_dp)
1133 {
1134         struct edp_power_seq hw;
1135         struct edp_power_seq *sw = &intel_dp->pps_delays;
1136
1137         intel_pps_readout_hw_state(intel_dp, &hw);
1138
1139         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
1140             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
1141                 DRM_ERROR("PPS state mismatch\n");
1142                 intel_pps_dump_state("sw", sw);
1143                 intel_pps_dump_state("hw", &hw);
1144         }
1145 }
1146
1147 static void
1148 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
1149 {
1150         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1151         struct edp_power_seq cur, vbt, spec,
1152                 *final = &intel_dp->pps_delays;
1153
1154         lockdep_assert_held(&dev_priv->pps_mutex);
1155
1156         /* already initialized? */
1157         if (final->t11_t12 != 0)
1158                 return;
1159
1160         intel_pps_readout_hw_state(intel_dp, &cur);
1161
1162         intel_pps_dump_state("cur", &cur);
1163
1164         vbt = dev_priv->vbt.edp.pps;
1165         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
1166          * of 500ms appears to be too short. Ocassionally the panel
1167          * just fails to power back on. Increasing the delay to 800ms
1168          * seems sufficient to avoid this problem.
1169          */
1170         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
1171                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
1172                 drm_dbg_kms(&dev_priv->drm,
1173                             "Increasing T12 panel delay as per the quirk to %d\n",
1174                             vbt.t11_t12);
1175         }
1176         /* T11_T12 delay is special and actually in units of 100ms, but zero
1177          * based in the hw (so we need to add 100 ms). But the sw vbt
1178          * table multiplies it with 1000 to make it in units of 100usec,
1179          * too. */
1180         vbt.t11_t12 += 100 * 10;
1181
1182         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
1183          * our hw here, which are all in 100usec. */
1184         spec.t1_t3 = 210 * 10;
1185         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
1186         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
1187         spec.t10 = 500 * 10;
1188         /* This one is special and actually in units of 100ms, but zero
1189          * based in the hw (so we need to add 100 ms). But the sw vbt
1190          * table multiplies it with 1000 to make it in units of 100usec,
1191          * too. */
1192         spec.t11_t12 = (510 + 100) * 10;
1193
1194         intel_pps_dump_state("vbt", &vbt);
1195
1196         /* Use the max of the register settings and vbt. If both are
1197          * unset, fall back to the spec limits. */
1198 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
1199                                        spec.field : \
1200                                        max(cur.field, vbt.field))
1201         assign_final(t1_t3);
1202         assign_final(t8);
1203         assign_final(t9);
1204         assign_final(t10);
1205         assign_final(t11_t12);
1206 #undef assign_final
1207
1208 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
1209         intel_dp->panel_power_up_delay = get_delay(t1_t3);
1210         intel_dp->backlight_on_delay = get_delay(t8);
1211         intel_dp->backlight_off_delay = get_delay(t9);
1212         intel_dp->panel_power_down_delay = get_delay(t10);
1213         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
1214 #undef get_delay
1215
1216         drm_dbg_kms(&dev_priv->drm,
1217                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1218                     intel_dp->panel_power_up_delay,
1219                     intel_dp->panel_power_down_delay,
1220                     intel_dp->panel_power_cycle_delay);
1221
1222         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
1223                     intel_dp->backlight_on_delay,
1224                     intel_dp->backlight_off_delay);
1225
1226         /*
1227          * We override the HW backlight delays to 1 because we do manual waits
1228          * on them. For T8, even BSpec recommends doing it. For T9, if we
1229          * don't do this, we'll end up waiting for the backlight off delay
1230          * twice: once when we do the manual sleep, and once when we disable
1231          * the panel and wait for the PP_STATUS bit to become zero.
1232          */
1233         final->t8 = 1;
1234         final->t9 = 1;
1235
1236         /*
1237          * HW has only a 100msec granularity for t11_t12 so round it up
1238          * accordingly.
1239          */
1240         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
1241 }
1242
1243 static void
1244 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
1245                                               bool force_disable_vdd)
1246 {
1247         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1248         u32 pp_on, pp_off, port_sel = 0;
1249         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
1250         struct pps_registers regs;
1251         enum port port = dp_to_dig_port(intel_dp)->base.port;
1252         const struct edp_power_seq *seq = &intel_dp->pps_delays;
1253
1254         lockdep_assert_held(&dev_priv->pps_mutex);
1255
1256         intel_pps_get_registers(intel_dp, &regs);
1257
1258         /*
1259          * On some VLV machines the BIOS can leave the VDD
1260          * enabled even on power sequencers which aren't
1261          * hooked up to any port. This would mess up the
1262          * power domain tracking the first time we pick
1263          * one of these power sequencers for use since
1264          * intel_pps_vdd_on_unlocked() would notice that the VDD was
1265          * already on and therefore wouldn't grab the power
1266          * domain reference. Disable VDD first to avoid this.
1267          * This also avoids spuriously turning the VDD on as
1268          * soon as the new power sequencer gets initialized.
1269          */
1270         if (force_disable_vdd) {
1271                 u32 pp = ilk_get_pp_control(intel_dp);
1272
1273                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
1274                          "Panel power already on\n");
1275
1276                 if (pp & EDP_FORCE_VDD)
1277                         drm_dbg_kms(&dev_priv->drm,
1278                                     "VDD already on, disabling first\n");
1279
1280                 pp &= ~EDP_FORCE_VDD;
1281
1282                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
1283         }
1284
1285         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
1286                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
1287         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
1288                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
1289
1290         /* Haswell doesn't have any port selection bits for the panel
1291          * power sequencer any more. */
1292         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1293                 port_sel = PANEL_PORT_SELECT_VLV(port);
1294         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1295                 switch (port) {
1296                 case PORT_A:
1297                         port_sel = PANEL_PORT_SELECT_DPA;
1298                         break;
1299                 case PORT_C:
1300                         port_sel = PANEL_PORT_SELECT_DPC;
1301                         break;
1302                 case PORT_D:
1303                         port_sel = PANEL_PORT_SELECT_DPD;
1304                         break;
1305                 default:
1306                         MISSING_CASE(port);
1307                         break;
1308                 }
1309         }
1310
1311         pp_on |= port_sel;
1312
1313         intel_de_write(dev_priv, regs.pp_on, pp_on);
1314         intel_de_write(dev_priv, regs.pp_off, pp_off);
1315
1316         /*
1317          * Compute the divisor for the pp clock, simply match the Bspec formula.
1318          */
1319         if (i915_mmio_reg_valid(regs.pp_div)) {
1320                 intel_de_write(dev_priv, regs.pp_div,
1321                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
1322         } else {
1323                 u32 pp_ctl;
1324
1325                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
1326                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
1327                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
1328                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1329         }
1330
1331         drm_dbg_kms(&dev_priv->drm,
1332                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1333                     intel_de_read(dev_priv, regs.pp_on),
1334                     intel_de_read(dev_priv, regs.pp_off),
1335                     i915_mmio_reg_valid(regs.pp_div) ?
1336                     intel_de_read(dev_priv, regs.pp_div) :
1337                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1338 }
1339
1340 static void intel_dp_pps_init(struct intel_dp *intel_dp)
1341 {
1342         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1343
1344         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1345                 vlv_initial_power_sequencer_setup(intel_dp);
1346         } else {
1347                 intel_dp_init_panel_power_sequencer(intel_dp);
1348                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1349         }
1350 }
1351
1352 void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1353 {
1354         intel_wakeref_t wakeref;
1355
1356         if (!intel_dp_is_edp(intel_dp))
1357                 return;
1358
1359         with_intel_pps_lock(intel_dp, wakeref) {
1360                 /*
1361                  * Reinit the power sequencer, in case BIOS did something nasty
1362                  * with it.
1363                  */
1364                 intel_dp_pps_init(intel_dp);
1365                 intel_pps_vdd_sanitize(intel_dp);
1366         }
1367 }
1368
1369 void intel_pps_init(struct intel_dp *intel_dp)
1370 {
1371         intel_wakeref_t wakeref;
1372
1373         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
1374
1375         with_intel_pps_lock(intel_dp, wakeref) {
1376                 intel_dp_init_panel_power_timestamps(intel_dp);
1377                 intel_dp_pps_init(intel_dp);
1378                 intel_pps_vdd_sanitize(intel_dp);
1379         }
1380 }