drivers/gpu/drm/i915/display/intel_pps.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include "g4x_dp.h"
   7 #include "i915_drv.h"
   8 #include "intel_display_types.h"
   9 #include "intel_dp.h"
  10 #include "intel_dpll.h"
  11 #include "intel_pps.h"
  12
  13 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
  14                                       enum pipe pipe);
  15
  16 static void pps_init_delays(struct intel_dp *intel_dp);
  17 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd);
  18
  19 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
  20 {
  21         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  22         intel_wakeref_t wakeref;
  23
  24         /*
  25          * See intel_pps_reset_all() why we need a power domain reference here.
  26          */
  27         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
  28         mutex_lock(&dev_priv->pps_mutex);
  29
  30         return wakeref;
  31 }
  32
  33 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
  34                                  intel_wakeref_t wakeref)
  35 {
  36         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  37
  38         mutex_unlock(&dev_priv->pps_mutex);
  39         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
  40
  41         return 0;
  42 }
  43
  44 static void
  45 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
  46 {
  47         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  48         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  49         enum pipe pipe = intel_dp->pps.pps_pipe;
  50         bool pll_enabled, release_cl_override = false;
  51         enum dpio_phy phy = DPIO_PHY(pipe);
  52         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
  53         u32 DP;
  54
  55         if (drm_WARN(&dev_priv->drm,
  56                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
  57                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
  58                      pipe_name(pipe), dig_port->base.base.base.id,
  59                      dig_port->base.base.name))
  60                 return;
  61
  62         drm_dbg_kms(&dev_priv->drm,
  63                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
  64                     pipe_name(pipe), dig_port->base.base.base.id,
  65                     dig_port->base.base.name);
  66
  67         /* Preserve the BIOS-computed detected bit. This is
  68          * supposed to be read-only.
  69          */
  70         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
  71         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  72         DP |= DP_PORT_WIDTH(1);
  73         DP |= DP_LINK_TRAIN_PAT_1;
  74
  75         if (IS_CHERRYVIEW(dev_priv))
  76                 DP |= DP_PIPE_SEL_CHV(pipe);
  77         else
  78                 DP |= DP_PIPE_SEL(pipe);
  79
  80         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
  81
  82         /*
  83          * The DPLL for the pipe must be enabled for this to work.
  84          * So enable temporarily it if it's not already enabled.
  85          */
  86         if (!pll_enabled) {
  87                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
  88                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
  89
  90                 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
  91                         drm_err(&dev_priv->drm,
  92                                 "Failed to force on pll for pipe %c!\n",
  93                                 pipe_name(pipe));
  94                         return;
  95                 }
  96         }
  97
  98         /*
  99          * Similar magic as in intel_dp_enable_port().
 100          * We _must_ do this port enable + disable trick
 101          * to make this power sequencer lock onto the port.
 102          * Otherwise even VDD force bit won't work.
 103          */
 104         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 105         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 106
 107         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 108         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 109
 110         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 111         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 112
 113         if (!pll_enabled) {
 114                 vlv_force_pll_off(dev_priv, pipe);
 115
 116                 if (release_cl_override)
 117                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 118         }
 119 }
 120
 121 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 122 {
 123         struct intel_encoder *encoder;
 124         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 125
 126         /*
 127          * We don't have power sequencer currently.
 128          * Pick one that's not used by other ports.
 129          */
 130         for_each_intel_dp(&dev_priv->drm, encoder) {
 131                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 132
 133                 if (encoder->type == INTEL_OUTPUT_EDP) {
 134                         drm_WARN_ON(&dev_priv->drm,
 135                                     intel_dp->pps.active_pipe != INVALID_PIPE &&
 136                                     intel_dp->pps.active_pipe !=
 137                                     intel_dp->pps.pps_pipe);
 138
 139                         if (intel_dp->pps.pps_pipe != INVALID_PIPE)
 140                                 pipes &= ~(1 << intel_dp->pps.pps_pipe);
 141                 } else {
 142                         drm_WARN_ON(&dev_priv->drm,
 143                                     intel_dp->pps.pps_pipe != INVALID_PIPE);
 144
 145                         if (intel_dp->pps.active_pipe != INVALID_PIPE)
 146                                 pipes &= ~(1 << intel_dp->pps.active_pipe);
 147                 }
 148         }
 149
 150         if (pipes == 0)
 151                 return INVALID_PIPE;
 152
 153         return ffs(pipes) - 1;
 154 }
 155
 156 static enum pipe
 157 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 158 {
 159         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 160         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 161         enum pipe pipe;
 162
 163         lockdep_assert_held(&dev_priv->pps_mutex);
 164
 165         /* We should never land here with regular DP ports */
 166         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 167
 168         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&
 169                     intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe);
 170
 171         if (intel_dp->pps.pps_pipe != INVALID_PIPE)
 172                 return intel_dp->pps.pps_pipe;
 173
 174         pipe = vlv_find_free_pps(dev_priv);
 175
 176         /*
 177          * Didn't find one. This should not happen since there
 178          * are two power sequencers and up to two eDP ports.
 179          */
 180         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
 181                 pipe = PIPE_A;
 182
 183         vlv_steal_power_sequencer(dev_priv, pipe);
 184         intel_dp->pps.pps_pipe = pipe;
 185
 186         drm_dbg_kms(&dev_priv->drm,
 187                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 188                     pipe_name(intel_dp->pps.pps_pipe),
 189                     dig_port->base.base.base.id,
 190                     dig_port->base.base.name);
 191
 192         /* init power sequencer on this pipe and port */
 193         pps_init_delays(intel_dp);
 194         pps_init_registers(intel_dp, true);
 195
 196         /*
 197          * Even vdd force doesn't work until we've made
 198          * the power sequencer lock in on the port.
 199          */
 200         vlv_power_sequencer_kick(intel_dp);
 201
 202         return intel_dp->pps.pps_pipe;
 203 }
 204
 205 static int
 206 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 207 {
 208         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 209         int backlight_controller = dev_priv->vbt.backlight.controller;
 210
 211         lockdep_assert_held(&dev_priv->pps_mutex);
 212
 213         /* We should never land here with regular DP ports */
 214         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 215
 216         if (!intel_dp->pps.pps_reset)
 217                 return backlight_controller;
 218
 219         intel_dp->pps.pps_reset = false;
 220
 221         /*
 222          * Only the HW needs to be reprogrammed, the SW state is fixed and
 223          * has been setup during connector init.
 224          */
 225         pps_init_registers(intel_dp, false);
 226
 227         return backlight_controller;
 228 }
 229
 230 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 231                                enum pipe pipe);
 232
 233 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 234                                enum pipe pipe)
 235 {
 236         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
 237 }
 238
 239 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 240                                 enum pipe pipe)
 241 {
 242         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 243 }
 244
 245 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 246                          enum pipe pipe)
 247 {
 248         return true;
 249 }
 250
 251 static enum pipe
 252 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 253                      enum port port,
 254                      vlv_pipe_check pipe_check)
 255 {
 256         enum pipe pipe;
 257
 258         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 259                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
 260                         PANEL_PORT_SELECT_MASK;
 261
 262                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 263                         continue;
 264
 265                 if (!pipe_check(dev_priv, pipe))
 266                         continue;
 267
 268                 return pipe;
 269         }
 270
 271         return INVALID_PIPE;
 272 }
 273
 274 static void
 275 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 276 {
 277         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 278         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 279         enum port port = dig_port->base.port;
 280
 281         lockdep_assert_held(&dev_priv->pps_mutex);
 282
 283         /* try to find a pipe with this port selected */
 284         /* first pick one where the panel is on */
 285         intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 286                                                       vlv_pipe_has_pp_on);
 287         /* didn't find one? pick one where vdd is on */
 288         if (intel_dp->pps.pps_pipe == INVALID_PIPE)
 289                 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 290                                                               vlv_pipe_has_vdd_on);
 291         /* didn't find one? pick one with just the correct port */
 292         if (intel_dp->pps.pps_pipe == INVALID_PIPE)
 293                 intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 294                                                               vlv_pipe_any);
 295
 296         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 297         if (intel_dp->pps.pps_pipe == INVALID_PIPE) {
 298                 drm_dbg_kms(&dev_priv->drm,
 299                             "no initial power sequencer for [ENCODER:%d:%s]\n",
 300                             dig_port->base.base.base.id,
 301                             dig_port->base.base.name);
 302                 return;
 303         }
 304
 305         drm_dbg_kms(&dev_priv->drm,
 306                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
 307                     dig_port->base.base.base.id,
 308                     dig_port->base.base.name,
 309                     pipe_name(intel_dp->pps.pps_pipe));
 310 }
 311
 312 void intel_pps_reset_all(struct drm_i915_private *dev_priv)
 313 {
 314         struct intel_encoder *encoder;
 315
 316         if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv)))
 317                 return;
 318
 319         /*
 320          * We can't grab pps_mutex here due to deadlock with power_domain
 321          * mutex when power_domain functions are called while holding pps_mutex.
 322          * That also means that in order to use pps_pipe the code needs to
 323          * hold both a power domain reference and pps_mutex, and the power domain
 324          * reference get/put must be done while _not_ holding pps_mutex.
 325          * pps_{lock,unlock}() do these steps in the correct order, so one
 326          * should use them always.
 327          */
 328
 329         for_each_intel_dp(&dev_priv->drm, encoder) {
 330                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 331
 332                 drm_WARN_ON(&dev_priv->drm,
 333                             intel_dp->pps.active_pipe != INVALID_PIPE);
 334
 335                 if (encoder->type != INTEL_OUTPUT_EDP)
 336                         continue;
 337
 338                 if (DISPLAY_VER(dev_priv) >= 9)
 339                         intel_dp->pps.pps_reset = true;
 340                 else
 341                         intel_dp->pps.pps_pipe = INVALID_PIPE;
 342         }
 343 }
 344
 345 struct pps_registers {
 346         i915_reg_t pp_ctrl;
 347         i915_reg_t pp_stat;
 348         i915_reg_t pp_on;
 349         i915_reg_t pp_off;
 350         i915_reg_t pp_div;
 351 };
 352
 353 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 354                                     struct pps_registers *regs)
 355 {
 356         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 357         int pps_idx = 0;
 358
 359         memset(regs, 0, sizeof(*regs));
 360
 361         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 362                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 363         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 364                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 365
 366         regs->pp_ctrl = PP_CONTROL(pps_idx);
 367         regs->pp_stat = PP_STATUS(pps_idx);
 368         regs->pp_on = PP_ON_DELAYS(pps_idx);
 369         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 370
 371         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 372         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
 373             INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 374                 regs->pp_div = INVALID_MMIO_REG;
 375         else
 376                 regs->pp_div = PP_DIVISOR(pps_idx);
 377 }
 378
 379 static i915_reg_t
 380 _pp_ctrl_reg(struct intel_dp *intel_dp)
 381 {
 382         struct pps_registers regs;
 383
 384         intel_pps_get_registers(intel_dp, &regs);
 385
 386         return regs.pp_ctrl;
 387 }
 388
 389 static i915_reg_t
 390 _pp_stat_reg(struct intel_dp *intel_dp)
 391 {
 392         struct pps_registers regs;
 393
 394         intel_pps_get_registers(intel_dp, &regs);
 395
 396         return regs.pp_stat;
 397 }
 398
 399 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 400 {
 401         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 402
 403         lockdep_assert_held(&dev_priv->pps_mutex);
 404
 405         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 406             intel_dp->pps.pps_pipe == INVALID_PIPE)
 407                 return false;
 408
 409         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
 410 }
 411
 412 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 413 {
 414         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 415
 416         lockdep_assert_held(&dev_priv->pps_mutex);
 417
 418         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 419             intel_dp->pps.pps_pipe == INVALID_PIPE)
 420                 return false;
 421
 422         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 423 }
 424
 425 void intel_pps_check_power_unlocked(struct intel_dp *intel_dp)
 426 {
 427         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 428
 429         if (!intel_dp_is_edp(intel_dp))
 430                 return;
 431
 432         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 433                 drm_WARN(&dev_priv->drm, 1,
 434                          "eDP powered off while attempting aux channel communication.\n");
 435                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
 436                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
 437                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
 438         }
 439 }
 440
 441 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 442 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 443
 444 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
 445 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
 446
 447 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 448 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 449
 450 static void intel_pps_verify_state(struct intel_dp *intel_dp);
 451
 452 static void wait_panel_status(struct intel_dp *intel_dp,
 453                                        u32 mask,
 454                                        u32 value)
 455 {
 456         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 457         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 458
 459         lockdep_assert_held(&dev_priv->pps_mutex);
 460
 461         intel_pps_verify_state(intel_dp);
 462
 463         pp_stat_reg = _pp_stat_reg(intel_dp);
 464         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 465
 466         drm_dbg_kms(&dev_priv->drm,
 467                     "mask %08x value %08x status %08x control %08x\n",
 468                     mask, value,
 469                     intel_de_read(dev_priv, pp_stat_reg),
 470                     intel_de_read(dev_priv, pp_ctrl_reg));
 471
 472         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
 473                                        mask, value, 5000))
 474                 drm_err(&dev_priv->drm,
 475                         "Panel status timeout: status %08x control %08x\n",
 476                         intel_de_read(dev_priv, pp_stat_reg),
 477                         intel_de_read(dev_priv, pp_ctrl_reg));
 478
 479         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
 480 }
 481
 482 static void wait_panel_on(struct intel_dp *intel_dp)
 483 {
 484         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 485
 486         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
 487         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 488 }
 489
 490 static void wait_panel_off(struct intel_dp *intel_dp)
 491 {
 492         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 493
 494         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
 495         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 496 }
 497
 498 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
 499 {
 500         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 501         ktime_t panel_power_on_time;
 502         s64 panel_power_off_duration;
 503
 504         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
 505
 506         /* take the difference of currrent time and panel power off time
 507          * and then make panel wait for t11_t12 if needed. */
 508         panel_power_on_time = ktime_get_boottime();
 509         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time);
 510
 511         /* When we disable the VDD override bit last we have to do the manual
 512          * wait. */
 513         if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay)
 514                 wait_remaining_ms_from_jiffies(jiffies,
 515                                        intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration);
 516
 517         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 518 }
 519
 520 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp)
 521 {
 522         intel_wakeref_t wakeref;
 523
 524         if (!intel_dp_is_edp(intel_dp))
 525                 return;
 526
 527         with_intel_pps_lock(intel_dp, wakeref)
 528                 wait_panel_power_cycle(intel_dp);
 529 }
 530
 531 static void wait_backlight_on(struct intel_dp *intel_dp)
 532 {
 533         wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on,
 534                                        intel_dp->pps.backlight_on_delay);
 535 }
 536
 537 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
 538 {
 539         wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off,
 540                                        intel_dp->pps.backlight_off_delay);
 541 }
 542
 543 /* Read the current pp_control value, unlocking the register if it
 544  * is locked
 545  */
 546
 547 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
 548 {
 549         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 550         u32 control;
 551
 552         lockdep_assert_held(&dev_priv->pps_mutex);
 553
 554         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
 555         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
 556                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
 557                 control &= ~PANEL_UNLOCK_MASK;
 558                 control |= PANEL_UNLOCK_REGS;
 559         }
 560         return control;
 561 }
 562
 563 /*
 564  * Must be paired with intel_pps_vdd_off_unlocked().
 565  * Must hold pps_mutex around the whole on/off sequence.
 566  * Can be nested with intel_pps_vdd_{on,off}() calls.
 567  */
 568 bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
 569 {
 570         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 571         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 572         u32 pp;
 573         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 574         bool need_to_disable = !intel_dp->pps.want_panel_vdd;
 575
 576         lockdep_assert_held(&dev_priv->pps_mutex);
 577
 578         if (!intel_dp_is_edp(intel_dp))
 579                 return false;
 580
 581         cancel_delayed_work(&intel_dp->pps.panel_vdd_work);
 582         intel_dp->pps.want_panel_vdd = true;
 583
 584         if (edp_have_panel_vdd(intel_dp))
 585                 return need_to_disable;
 586
 587         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
 588         intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
 589                                                             intel_aux_power_domain(dig_port));
 590
 591         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
 592                     dig_port->base.base.base.id,
 593                     dig_port->base.base.name);
 594
 595         if (!edp_have_panel_power(intel_dp))
 596                 wait_panel_power_cycle(intel_dp);
 597
 598         pp = ilk_get_pp_control(intel_dp);
 599         pp |= EDP_FORCE_VDD;
 600
 601         pp_stat_reg = _pp_stat_reg(intel_dp);
 602         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 603
 604         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 605         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 606         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 607                     intel_de_read(dev_priv, pp_stat_reg),
 608                     intel_de_read(dev_priv, pp_ctrl_reg));
 609         /*
 610          * If the panel wasn't on, delay before accessing aux channel
 611          */
 612         if (!edp_have_panel_power(intel_dp)) {
 613                 drm_dbg_kms(&dev_priv->drm,
 614                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
 615                             dig_port->base.base.base.id,
 616                             dig_port->base.base.name);
 617                 msleep(intel_dp->pps.panel_power_up_delay);
 618         }
 619
 620         return need_to_disable;
 621 }
 622
 623 /*
 624  * Must be paired with intel_pps_off().
 625  * Nested calls to these functions are not allowed since
 626  * we drop the lock. Caller must use some higher level
 627  * locking to prevent nested calls from other threads.
 628  */
 629 void intel_pps_vdd_on(struct intel_dp *intel_dp)
 630 {
 631         intel_wakeref_t wakeref;
 632         bool vdd;
 633
 634         if (!intel_dp_is_edp(intel_dp))
 635                 return;
 636
 637         vdd = false;
 638         with_intel_pps_lock(intel_dp, wakeref)
 639                 vdd = intel_pps_vdd_on_unlocked(intel_dp);
 640         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
 641                         dp_to_dig_port(intel_dp)->base.base.base.id,
 642                         dp_to_dig_port(intel_dp)->base.base.name);
 643 }
 644
 645 static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
 646 {
 647         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 648         struct intel_digital_port *dig_port =
 649                 dp_to_dig_port(intel_dp);
 650         u32 pp;
 651         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 652
 653         lockdep_assert_held(&dev_priv->pps_mutex);
 654
 655         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
 656
 657         if (!edp_have_panel_vdd(intel_dp))
 658                 return;
 659
 660         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
 661                     dig_port->base.base.base.id,
 662                     dig_port->base.base.name);
 663
 664         pp = ilk_get_pp_control(intel_dp);
 665         pp &= ~EDP_FORCE_VDD;
 666
 667         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 668         pp_stat_reg = _pp_stat_reg(intel_dp);
 669
 670         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 671         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 672
 673         /* Make sure sequencer is idle before allowing subsequent activity */
 674         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 675                     intel_de_read(dev_priv, pp_stat_reg),
 676                     intel_de_read(dev_priv, pp_ctrl_reg));
 677
 678         if ((pp & PANEL_POWER_ON) == 0)
 679                 intel_dp->pps.panel_power_off_time = ktime_get_boottime();
 680
 681         intel_display_power_put(dev_priv,
 682                                 intel_aux_power_domain(dig_port),
 683                                 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
 684 }
 685
 686 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp)
 687 {
 688         intel_wakeref_t wakeref;
 689
 690         if (!intel_dp_is_edp(intel_dp))
 691                 return;
 692
 693         cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work);
 694         /*
 695          * vdd might still be enabled due to the delayed vdd off.
 696          * Make sure vdd is actually turned off here.
 697          */
 698         with_intel_pps_lock(intel_dp, wakeref)
 699                 intel_pps_vdd_off_sync_unlocked(intel_dp);
 700 }
 701
 702 static void edp_panel_vdd_work(struct work_struct *__work)
 703 {
 704         struct intel_pps *pps = container_of(to_delayed_work(__work),
 705                                              struct intel_pps, panel_vdd_work);
 706         struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps);
 707         intel_wakeref_t wakeref;
 708
 709         with_intel_pps_lock(intel_dp, wakeref) {
 710                 if (!intel_dp->pps.want_panel_vdd)
 711                         intel_pps_vdd_off_sync_unlocked(intel_dp);
 712         }
 713 }
 714
 715 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
 716 {
 717         unsigned long delay;
 718
 719         /*
 720          * Queue the timer to fire a long time from now (relative to the power
 721          * down delay) to keep the panel power up across a sequence of
 722          * operations.
 723          */
 724         delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5);
 725         schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay);
 726 }
 727
 728 /*
 729  * Must be paired with edp_panel_vdd_on().
 730  * Must hold pps_mutex around the whole on/off sequence.
 731  * Can be nested with intel_pps_vdd_{on,off}() calls.
 732  */
 733 void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
 734 {
 735         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 736
 737         lockdep_assert_held(&dev_priv->pps_mutex);
 738
 739         if (!intel_dp_is_edp(intel_dp))
 740                 return;
 741
 742         I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
 743                         dp_to_dig_port(intel_dp)->base.base.base.id,
 744                         dp_to_dig_port(intel_dp)->base.base.name);
 745
 746         intel_dp->pps.want_panel_vdd = false;
 747
 748         if (sync)
 749                 intel_pps_vdd_off_sync_unlocked(intel_dp);
 750         else
 751                 edp_panel_vdd_schedule_off(intel_dp);
 752 }
 753
 754 void intel_pps_on_unlocked(struct intel_dp *intel_dp)
 755 {
 756         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 757         u32 pp;
 758         i915_reg_t pp_ctrl_reg;
 759
 760         lockdep_assert_held(&dev_priv->pps_mutex);
 761
 762         if (!intel_dp_is_edp(intel_dp))
 763                 return;
 764
 765         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
 766                     dp_to_dig_port(intel_dp)->base.base.base.id,
 767                     dp_to_dig_port(intel_dp)->base.base.name);
 768
 769         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
 770                      "[ENCODER:%d:%s] panel power already on\n",
 771                      dp_to_dig_port(intel_dp)->base.base.base.id,
 772                      dp_to_dig_port(intel_dp)->base.base.name))
 773                 return;
 774
 775         wait_panel_power_cycle(intel_dp);
 776
 777         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 778         pp = ilk_get_pp_control(intel_dp);
 779         if (IS_IRONLAKE(dev_priv)) {
 780                 /* ILK workaround: disable reset around power sequence */
 781                 pp &= ~PANEL_POWER_RESET;
 782                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 783                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 784         }
 785
 786         pp |= PANEL_POWER_ON;
 787         if (!IS_IRONLAKE(dev_priv))
 788                 pp |= PANEL_POWER_RESET;
 789
 790         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 791         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 792
 793         wait_panel_on(intel_dp);
 794         intel_dp->pps.last_power_on = jiffies;
 795
 796         if (IS_IRONLAKE(dev_priv)) {
 797                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 798                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 799                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 800         }
 801 }
 802
 803 void intel_pps_on(struct intel_dp *intel_dp)
 804 {
 805         intel_wakeref_t wakeref;
 806
 807         if (!intel_dp_is_edp(intel_dp))
 808                 return;
 809
 810         with_intel_pps_lock(intel_dp, wakeref)
 811                 intel_pps_on_unlocked(intel_dp);
 812 }
 813
 814 void intel_pps_off_unlocked(struct intel_dp *intel_dp)
 815 {
 816         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 817         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 818         u32 pp;
 819         i915_reg_t pp_ctrl_reg;
 820
 821         lockdep_assert_held(&dev_priv->pps_mutex);
 822
 823         if (!intel_dp_is_edp(intel_dp))
 824                 return;
 825
 826         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
 827                     dig_port->base.base.base.id, dig_port->base.base.name);
 828
 829         drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,
 830                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
 831                  dig_port->base.base.base.id, dig_port->base.base.name);
 832
 833         pp = ilk_get_pp_control(intel_dp);
 834         /* We need to switch off panel power _and_ force vdd, for otherwise some
 835          * panels get very unhappy and cease to work. */
 836         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
 837                 EDP_BLC_ENABLE);
 838
 839         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 840
 841         intel_dp->pps.want_panel_vdd = false;
 842
 843         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 844         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 845
 846         wait_panel_off(intel_dp);
 847         intel_dp->pps.panel_power_off_time = ktime_get_boottime();
 848
 849         /* We got a reference when we enabled the VDD. */
 850         intel_display_power_put(dev_priv,
 851                                 intel_aux_power_domain(dig_port),
 852                                 fetch_and_zero(&intel_dp->pps.vdd_wakeref));
 853 }
 854
 855 void intel_pps_off(struct intel_dp *intel_dp)
 856 {
 857         intel_wakeref_t wakeref;
 858
 859         if (!intel_dp_is_edp(intel_dp))
 860                 return;
 861
 862         with_intel_pps_lock(intel_dp, wakeref)
 863                 intel_pps_off_unlocked(intel_dp);
 864 }
 865
 866 /* Enable backlight in the panel power control. */
 867 void intel_pps_backlight_on(struct intel_dp *intel_dp)
 868 {
 869         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 870         intel_wakeref_t wakeref;
 871
 872         /*
 873          * If we enable the backlight right away following a panel power
 874          * on, we may see slight flicker as the panel syncs with the eDP
 875          * link.  So delay a bit to make sure the image is solid before
 876          * allowing it to appear.
 877          */
 878         wait_backlight_on(intel_dp);
 879
 880         with_intel_pps_lock(intel_dp, wakeref) {
 881                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 882                 u32 pp;
 883
 884                 pp = ilk_get_pp_control(intel_dp);
 885                 pp |= EDP_BLC_ENABLE;
 886
 887                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 888                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 889         }
 890 }
 891
 892 /* Disable backlight in the panel power control. */
 893 void intel_pps_backlight_off(struct intel_dp *intel_dp)
 894 {
 895         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 896         intel_wakeref_t wakeref;
 897
 898         if (!intel_dp_is_edp(intel_dp))
 899                 return;
 900
 901         with_intel_pps_lock(intel_dp, wakeref) {
 902                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 903                 u32 pp;
 904
 905                 pp = ilk_get_pp_control(intel_dp);
 906                 pp &= ~EDP_BLC_ENABLE;
 907
 908                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 909                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 910         }
 911
 912         intel_dp->pps.last_backlight_off = jiffies;
 913         edp_wait_backlight_off(intel_dp);
 914 }
 915
 916 /*
 917  * Hook for controlling the panel power control backlight through the bl_power
 918  * sysfs attribute. Take care to handle multiple calls.
 919  */
 920 void intel_pps_backlight_power(struct intel_connector *connector, bool enable)
 921 {
 922         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 923         struct intel_dp *intel_dp = intel_attached_dp(connector);
 924         intel_wakeref_t wakeref;
 925         bool is_enabled;
 926
 927         is_enabled = false;
 928         with_intel_pps_lock(intel_dp, wakeref)
 929                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
 930         if (is_enabled == enable)
 931                 return;
 932
 933         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
 934                     enable ? "enable" : "disable");
 935
 936         if (enable)
 937                 intel_pps_backlight_on(intel_dp);
 938         else
 939                 intel_pps_backlight_off(intel_dp);
 940 }
 941
 942 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
 943 {
 944         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 945         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 946         enum pipe pipe = intel_dp->pps.pps_pipe;
 947         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
 948
 949         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
 950
 951         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
 952                 return;
 953
 954         intel_pps_vdd_off_sync_unlocked(intel_dp);
 955
 956         /*
 957          * VLV seems to get confused when multiple power sequencers
 958          * have the same port selected (even if only one has power/vdd
 959          * enabled). The failure manifests as vlv_wait_port_ready() failing
 960          * CHV on the other hand doesn't seem to mind having the same port
 961          * selected in multiple power sequencers, but let's clear the
 962          * port select always when logically disconnecting a power sequencer
 963          * from a port.
 964          */
 965         drm_dbg_kms(&dev_priv->drm,
 966                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
 967                     pipe_name(pipe), dig_port->base.base.base.id,
 968                     dig_port->base.base.name);
 969         intel_de_write(dev_priv, pp_on_reg, 0);
 970         intel_de_posting_read(dev_priv, pp_on_reg);
 971
 972         intel_dp->pps.pps_pipe = INVALID_PIPE;
 973 }
 974
 975 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 976                                       enum pipe pipe)
 977 {
 978         struct intel_encoder *encoder;
 979
 980         lockdep_assert_held(&dev_priv->pps_mutex);
 981
 982         for_each_intel_dp(&dev_priv->drm, encoder) {
 983                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 984
 985                 drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,
 986                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
 987                          pipe_name(pipe), encoder->base.base.id,
 988                          encoder->base.name);
 989
 990                 if (intel_dp->pps.pps_pipe != pipe)
 991                         continue;
 992
 993                 drm_dbg_kms(&dev_priv->drm,
 994                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
 995                             pipe_name(pipe), encoder->base.base.id,
 996                             encoder->base.name);
 997
 998                 /* make sure vdd is off before we steal it */
 999                 vlv_detach_power_sequencer(intel_dp);
1000         }
1001 }
1002
1003 void vlv_pps_init(struct intel_encoder *encoder,
1004                   const struct intel_crtc_state *crtc_state)
1005 {
1006         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1007         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1008         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1009
1010         lockdep_assert_held(&dev_priv->pps_mutex);
1011
1012         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
1013
1014         if (intel_dp->pps.pps_pipe != INVALID_PIPE &&
1015             intel_dp->pps.pps_pipe != crtc->pipe) {
1016                 /*
1017                  * If another power sequencer was being used on this
1018                  * port previously make sure to turn off vdd there while
1019                  * we still have control of it.
1020                  */
1021                 vlv_detach_power_sequencer(intel_dp);
1022         }
1023
1024         /*
1025          * We may be stealing the power
1026          * sequencer from another port.
1027          */
1028         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
1029
1030         intel_dp->pps.active_pipe = crtc->pipe;
1031
1032         if (!intel_dp_is_edp(intel_dp))
1033                 return;
1034
1035         /* now it's all ours */
1036         intel_dp->pps.pps_pipe = crtc->pipe;
1037
1038         drm_dbg_kms(&dev_priv->drm,
1039                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
1040                     pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,
1041                     encoder->base.name);
1042
1043         /* init power sequencer on this pipe and port */
1044         pps_init_delays(intel_dp);
1045         pps_init_registers(intel_dp, true);
1046 }
1047
1048 static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
1049 {
1050         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1051         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1052
1053         lockdep_assert_held(&dev_priv->pps_mutex);
1054
1055         if (!edp_have_panel_vdd(intel_dp))
1056                 return;
1057
1058         /*
1059          * The VDD bit needs a power domain reference, so if the bit is
1060          * already enabled when we boot or resume, grab this reference and
1061          * schedule a vdd off, so we don't hold on to the reference
1062          * indefinitely.
1063          */
1064         drm_dbg_kms(&dev_priv->drm,
1065                     "VDD left on by BIOS, adjusting state tracking\n");
1066         drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref);
1067         intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv,
1068                                                             intel_aux_power_domain(dig_port));
1069
1070         edp_panel_vdd_schedule_off(intel_dp);
1071 }
1072
1073 bool intel_pps_have_power(struct intel_dp *intel_dp)
1074 {
1075         intel_wakeref_t wakeref;
1076         bool have_power = false;
1077
1078         with_intel_pps_lock(intel_dp, wakeref) {
1079                 have_power = edp_have_panel_power(intel_dp) &&
1080                                                   edp_have_panel_vdd(intel_dp);
1081         }
1082
1083         return have_power;
1084 }
1085
1086 static void pps_init_timestamps(struct intel_dp *intel_dp)
1087 {
1088         intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1089         intel_dp->pps.last_power_on = jiffies;
1090         intel_dp->pps.last_backlight_off = jiffies;
1091 }
1092
1093 static void
1094 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
1095 {
1096         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1097         u32 pp_on, pp_off, pp_ctl;
1098         struct pps_registers regs;
1099
1100         intel_pps_get_registers(intel_dp, &regs);
1101
1102         pp_ctl = ilk_get_pp_control(intel_dp);
1103
1104         /* Ensure PPS is unlocked */
1105         if (!HAS_DDI(dev_priv))
1106                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1107
1108         pp_on = intel_de_read(dev_priv, regs.pp_on);
1109         pp_off = intel_de_read(dev_priv, regs.pp_off);
1110
1111         /* Pull timing values out of registers */
1112         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1113         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1114         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1115         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1116
1117         if (i915_mmio_reg_valid(regs.pp_div)) {
1118                 u32 pp_div;
1119
1120                 pp_div = intel_de_read(dev_priv, regs.pp_div);
1121
1122                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
1123         } else {
1124                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
1125         }
1126 }
1127
1128 static void
1129 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
1130 {
1131         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1132                       state_name,
1133                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
1134 }
1135
1136 static void
1137 intel_pps_verify_state(struct intel_dp *intel_dp)
1138 {
1139         struct edp_power_seq hw;
1140         struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
1141
1142         intel_pps_readout_hw_state(intel_dp, &hw);
1143
1144         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
1145             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
1146                 DRM_ERROR("PPS state mismatch\n");
1147                 intel_pps_dump_state("sw", sw);
1148                 intel_pps_dump_state("hw", &hw);
1149         }
1150 }
1151
1152 static void pps_init_delays(struct intel_dp *intel_dp)
1153 {
1154         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1155         struct edp_power_seq cur, vbt, spec,
1156                 *final = &intel_dp->pps.pps_delays;
1157
1158         lockdep_assert_held(&dev_priv->pps_mutex);
1159
1160         /* already initialized? */
1161         if (final->t11_t12 != 0)
1162                 return;
1163
1164         intel_pps_readout_hw_state(intel_dp, &cur);
1165
1166         intel_pps_dump_state("cur", &cur);
1167
1168         vbt = dev_priv->vbt.edp.pps;
1169         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
1170          * of 500ms appears to be too short. Ocassionally the panel
1171          * just fails to power back on. Increasing the delay to 800ms
1172          * seems sufficient to avoid this problem.
1173          */
1174         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
1175                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
1176                 drm_dbg_kms(&dev_priv->drm,
1177                             "Increasing T12 panel delay as per the quirk to %d\n",
1178                             vbt.t11_t12);
1179         }
1180         /* T11_T12 delay is special and actually in units of 100ms, but zero
1181          * based in the hw (so we need to add 100 ms). But the sw vbt
1182          * table multiplies it with 1000 to make it in units of 100usec,
1183          * too. */
1184         vbt.t11_t12 += 100 * 10;
1185
1186         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
1187          * our hw here, which are all in 100usec. */
1188         spec.t1_t3 = 210 * 10;
1189         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
1190         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
1191         spec.t10 = 500 * 10;
1192         /* This one is special and actually in units of 100ms, but zero
1193          * based in the hw (so we need to add 100 ms). But the sw vbt
1194          * table multiplies it with 1000 to make it in units of 100usec,
1195          * too. */
1196         spec.t11_t12 = (510 + 100) * 10;
1197
1198         intel_pps_dump_state("vbt", &vbt);
1199
1200         /* Use the max of the register settings and vbt. If both are
1201          * unset, fall back to the spec limits. */
1202 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
1203                                        spec.field : \
1204                                        max(cur.field, vbt.field))
1205         assign_final(t1_t3);
1206         assign_final(t8);
1207         assign_final(t9);
1208         assign_final(t10);
1209         assign_final(t11_t12);
1210 #undef assign_final
1211
1212 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
1213         intel_dp->pps.panel_power_up_delay = get_delay(t1_t3);
1214         intel_dp->pps.backlight_on_delay = get_delay(t8);
1215         intel_dp->pps.backlight_off_delay = get_delay(t9);
1216         intel_dp->pps.panel_power_down_delay = get_delay(t10);
1217         intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12);
1218 #undef get_delay
1219
1220         drm_dbg_kms(&dev_priv->drm,
1221                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1222                     intel_dp->pps.panel_power_up_delay,
1223                     intel_dp->pps.panel_power_down_delay,
1224                     intel_dp->pps.panel_power_cycle_delay);
1225
1226         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
1227                     intel_dp->pps.backlight_on_delay,
1228                     intel_dp->pps.backlight_off_delay);
1229
1230         /*
1231          * We override the HW backlight delays to 1 because we do manual waits
1232          * on them. For T8, even BSpec recommends doing it. For T9, if we
1233          * don't do this, we'll end up waiting for the backlight off delay
1234          * twice: once when we do the manual sleep, and once when we disable
1235          * the panel and wait for the PP_STATUS bit to become zero.
1236          */
1237         final->t8 = 1;
1238         final->t9 = 1;
1239
1240         /*
1241          * HW has only a 100msec granularity for t11_t12 so round it up
1242          * accordingly.
1243          */
1244         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
1245 }
1246
1247 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd)
1248 {
1249         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1250         u32 pp_on, pp_off, port_sel = 0;
1251         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
1252         struct pps_registers regs;
1253         enum port port = dp_to_dig_port(intel_dp)->base.port;
1254         const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
1255
1256         lockdep_assert_held(&dev_priv->pps_mutex);
1257
1258         intel_pps_get_registers(intel_dp, &regs);
1259
1260         /*
1261          * On some VLV machines the BIOS can leave the VDD
1262          * enabled even on power sequencers which aren't
1263          * hooked up to any port. This would mess up the
1264          * power domain tracking the first time we pick
1265          * one of these power sequencers for use since
1266          * intel_pps_vdd_on_unlocked() would notice that the VDD was
1267          * already on and therefore wouldn't grab the power
1268          * domain reference. Disable VDD first to avoid this.
1269          * This also avoids spuriously turning the VDD on as
1270          * soon as the new power sequencer gets initialized.
1271          */
1272         if (force_disable_vdd) {
1273                 u32 pp = ilk_get_pp_control(intel_dp);
1274
1275                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
1276                          "Panel power already on\n");
1277
1278                 if (pp & EDP_FORCE_VDD)
1279                         drm_dbg_kms(&dev_priv->drm,
1280                                     "VDD already on, disabling first\n");
1281
1282                 pp &= ~EDP_FORCE_VDD;
1283
1284                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
1285         }
1286
1287         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
1288                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
1289         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
1290                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
1291
1292         /* Haswell doesn't have any port selection bits for the panel
1293          * power sequencer any more. */
1294         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1295                 port_sel = PANEL_PORT_SELECT_VLV(port);
1296         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1297                 switch (port) {
1298                 case PORT_A:
1299                         port_sel = PANEL_PORT_SELECT_DPA;
1300                         break;
1301                 case PORT_C:
1302                         port_sel = PANEL_PORT_SELECT_DPC;
1303                         break;
1304                 case PORT_D:
1305                         port_sel = PANEL_PORT_SELECT_DPD;
1306                         break;
1307                 default:
1308                         MISSING_CASE(port);
1309                         break;
1310                 }
1311         }
1312
1313         pp_on |= port_sel;
1314
1315         intel_de_write(dev_priv, regs.pp_on, pp_on);
1316         intel_de_write(dev_priv, regs.pp_off, pp_off);
1317
1318         /*
1319          * Compute the divisor for the pp clock, simply match the Bspec formula.
1320          */
1321         if (i915_mmio_reg_valid(regs.pp_div)) {
1322                 intel_de_write(dev_priv, regs.pp_div,
1323                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
1324         } else {
1325                 u32 pp_ctl;
1326
1327                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
1328                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
1329                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
1330                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1331         }
1332
1333         drm_dbg_kms(&dev_priv->drm,
1334                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1335                     intel_de_read(dev_priv, regs.pp_on),
1336                     intel_de_read(dev_priv, regs.pp_off),
1337                     i915_mmio_reg_valid(regs.pp_div) ?
1338                     intel_de_read(dev_priv, regs.pp_div) :
1339                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1340 }
1341
1342 void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1343 {
1344         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1345         intel_wakeref_t wakeref;
1346
1347         if (!intel_dp_is_edp(intel_dp))
1348                 return;
1349
1350         with_intel_pps_lock(intel_dp, wakeref) {
1351                 /*
1352                  * Reinit the power sequencer also on the resume path, in case
1353                  * BIOS did something nasty with it.
1354                  */
1355                 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1356                         vlv_initial_power_sequencer_setup(intel_dp);
1357
1358                 pps_init_delays(intel_dp);
1359                 pps_init_registers(intel_dp, false);
1360
1361                 intel_pps_vdd_sanitize(intel_dp);
1362         }
1363 }
1364
1365 void intel_pps_init(struct intel_dp *intel_dp)
1366 {
1367         INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work);
1368
1369         pps_init_timestamps(intel_dp);
1370
1371         intel_pps_encoder_reset(intel_dp);
1372 }
1373
1374 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
1375 {
1376         int pps_num;
1377         int pps_idx;
1378
1379         if (HAS_DDI(dev_priv))
1380                 return;
1381         /*
1382          * This w/a is needed at least on CPT/PPT, but to be sure apply it
1383          * everywhere where registers can be write protected.
1384          */
1385         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1386                 pps_num = 2;
1387         else
1388                 pps_num = 1;
1389
1390         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
1391                 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
1392
1393                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
1394                 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
1395         }
1396 }
1397
1398 void intel_pps_setup(struct drm_i915_private *i915)
1399 {
1400         if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1401                 i915->pps_mmio_base = PCH_PPS_BASE;
1402         else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1403                 i915->pps_mmio_base = VLV_PPS_BASE;
1404         else
1405                 i915->pps_mmio_base = PPS_BASE;
1406 }