drivers/gpu/drm/i915/display/intel_pps.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "intel_display_types.h"
   8 #include "intel_dp.h"
   9 #include "intel_pps.h"
  10
  11 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
  12                                       enum pipe pipe);
  13 static void
  14 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
  15 static void
  16 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
  17                                               bool force_disable_vdd);
  18
  19 intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
  20 {
  21         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  22         intel_wakeref_t wakeref;
  23
  24         /*
  25          * See intel_power_sequencer_reset() why we need
  26          * a power domain reference here.
  27          */
  28         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
  29         mutex_lock(&dev_priv->pps_mutex);
  30
  31         return wakeref;
  32 }
  33
  34 intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
  35                                  intel_wakeref_t wakeref)
  36 {
  37         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  38
  39         mutex_unlock(&dev_priv->pps_mutex);
  40         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
  41
  42         return 0;
  43 }
  44
  45 static void
  46 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
  47 {
  48         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
  49         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  50         enum pipe pipe = intel_dp->pps_pipe;
  51         bool pll_enabled, release_cl_override = false;
  52         enum dpio_phy phy = DPIO_PHY(pipe);
  53         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
  54         u32 DP;
  55
  56         if (drm_WARN(&dev_priv->drm,
  57                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
  58                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
  59                      pipe_name(pipe), dig_port->base.base.base.id,
  60                      dig_port->base.base.name))
  61                 return;
  62
  63         drm_dbg_kms(&dev_priv->drm,
  64                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
  65                     pipe_name(pipe), dig_port->base.base.base.id,
  66                     dig_port->base.base.name);
  67
  68         /* Preserve the BIOS-computed detected bit. This is
  69          * supposed to be read-only.
  70          */
  71         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
  72         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  73         DP |= DP_PORT_WIDTH(1);
  74         DP |= DP_LINK_TRAIN_PAT_1;
  75
  76         if (IS_CHERRYVIEW(dev_priv))
  77                 DP |= DP_PIPE_SEL_CHV(pipe);
  78         else
  79                 DP |= DP_PIPE_SEL(pipe);
  80
  81         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
  82
  83         /*
  84          * The DPLL for the pipe must be enabled for this to work.
  85          * So enable temporarily it if it's not already enabled.
  86          */
  87         if (!pll_enabled) {
  88                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
  89                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
  90
  91                 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
  92                         drm_err(&dev_priv->drm,
  93                                 "Failed to force on pll for pipe %c!\n",
  94                                 pipe_name(pipe));
  95                         return;
  96                 }
  97         }
  98
  99         /*
 100          * Similar magic as in intel_dp_enable_port().
 101          * We _must_ do this port enable + disable trick
 102          * to make this power sequencer lock onto the port.
 103          * Otherwise even VDD force bit won't work.
 104          */
 105         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 106         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 107
 108         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 109         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 110
 111         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 112         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 113
 114         if (!pll_enabled) {
 115                 vlv_force_pll_off(dev_priv, pipe);
 116
 117                 if (release_cl_override)
 118                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 119         }
 120 }
 121
 122 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 123 {
 124         struct intel_encoder *encoder;
 125         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 126
 127         /*
 128          * We don't have power sequencer currently.
 129          * Pick one that's not used by other ports.
 130          */
 131         for_each_intel_dp(&dev_priv->drm, encoder) {
 132                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 133
 134                 if (encoder->type == INTEL_OUTPUT_EDP) {
 135                         drm_WARN_ON(&dev_priv->drm,
 136                                     intel_dp->active_pipe != INVALID_PIPE &&
 137                                     intel_dp->active_pipe !=
 138                                     intel_dp->pps_pipe);
 139
 140                         if (intel_dp->pps_pipe != INVALID_PIPE)
 141                                 pipes &= ~(1 << intel_dp->pps_pipe);
 142                 } else {
 143                         drm_WARN_ON(&dev_priv->drm,
 144                                     intel_dp->pps_pipe != INVALID_PIPE);
 145
 146                         if (intel_dp->active_pipe != INVALID_PIPE)
 147                                 pipes &= ~(1 << intel_dp->active_pipe);
 148                 }
 149         }
 150
 151         if (pipes == 0)
 152                 return INVALID_PIPE;
 153
 154         return ffs(pipes) - 1;
 155 }
 156
 157 static enum pipe
 158 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 159 {
 160         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 161         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 162         enum pipe pipe;
 163
 164         lockdep_assert_held(&dev_priv->pps_mutex);
 165
 166         /* We should never land here with regular DP ports */
 167         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 168
 169         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
 170                     intel_dp->active_pipe != intel_dp->pps_pipe);
 171
 172         if (intel_dp->pps_pipe != INVALID_PIPE)
 173                 return intel_dp->pps_pipe;
 174
 175         pipe = vlv_find_free_pps(dev_priv);
 176
 177         /*
 178          * Didn't find one. This should not happen since there
 179          * are two power sequencers and up to two eDP ports.
 180          */
 181         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
 182                 pipe = PIPE_A;
 183
 184         vlv_steal_power_sequencer(dev_priv, pipe);
 185         intel_dp->pps_pipe = pipe;
 186
 187         drm_dbg_kms(&dev_priv->drm,
 188                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 189                     pipe_name(intel_dp->pps_pipe),
 190                     dig_port->base.base.base.id,
 191                     dig_port->base.base.name);
 192
 193         /* init power sequencer on this pipe and port */
 194         intel_dp_init_panel_power_sequencer(intel_dp);
 195         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 196
 197         /*
 198          * Even vdd force doesn't work until we've made
 199          * the power sequencer lock in on the port.
 200          */
 201         vlv_power_sequencer_kick(intel_dp);
 202
 203         return intel_dp->pps_pipe;
 204 }
 205
 206 static int
 207 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 208 {
 209         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 210         int backlight_controller = dev_priv->vbt.backlight.controller;
 211
 212         lockdep_assert_held(&dev_priv->pps_mutex);
 213
 214         /* We should never land here with regular DP ports */
 215         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 216
 217         if (!intel_dp->pps_reset)
 218                 return backlight_controller;
 219
 220         intel_dp->pps_reset = false;
 221
 222         /*
 223          * Only the HW needs to be reprogrammed, the SW state is fixed and
 224          * has been setup during connector init.
 225          */
 226         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 227
 228         return backlight_controller;
 229 }
 230
 231 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 232                                enum pipe pipe);
 233
 234 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 235                                enum pipe pipe)
 236 {
 237         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
 238 }
 239
 240 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 241                                 enum pipe pipe)
 242 {
 243         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 244 }
 245
 246 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 247                          enum pipe pipe)
 248 {
 249         return true;
 250 }
 251
 252 static enum pipe
 253 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 254                      enum port port,
 255                      vlv_pipe_check pipe_check)
 256 {
 257         enum pipe pipe;
 258
 259         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 260                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
 261                         PANEL_PORT_SELECT_MASK;
 262
 263                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 264                         continue;
 265
 266                 if (!pipe_check(dev_priv, pipe))
 267                         continue;
 268
 269                 return pipe;
 270         }
 271
 272         return INVALID_PIPE;
 273 }
 274
 275 static void
 276 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 277 {
 278         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 279         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 280         enum port port = dig_port->base.port;
 281
 282         lockdep_assert_held(&dev_priv->pps_mutex);
 283
 284         /* try to find a pipe with this port selected */
 285         /* first pick one where the panel is on */
 286         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 287                                                   vlv_pipe_has_pp_on);
 288         /* didn't find one? pick one where vdd is on */
 289         if (intel_dp->pps_pipe == INVALID_PIPE)
 290                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 291                                                           vlv_pipe_has_vdd_on);
 292         /* didn't find one? pick one with just the correct port */
 293         if (intel_dp->pps_pipe == INVALID_PIPE)
 294                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 295                                                           vlv_pipe_any);
 296
 297         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 298         if (intel_dp->pps_pipe == INVALID_PIPE) {
 299                 drm_dbg_kms(&dev_priv->drm,
 300                             "no initial power sequencer for [ENCODER:%d:%s]\n",
 301                             dig_port->base.base.base.id,
 302                             dig_port->base.base.name);
 303                 return;
 304         }
 305
 306         drm_dbg_kms(&dev_priv->drm,
 307                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
 308                     dig_port->base.base.base.id,
 309                     dig_port->base.base.name,
 310                     pipe_name(intel_dp->pps_pipe));
 311
 312         intel_dp_init_panel_power_sequencer(intel_dp);
 313         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 314 }
 315
 316 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 317 {
 318         struct intel_encoder *encoder;
 319
 320         if (drm_WARN_ON(&dev_priv->drm,
 321                         !(IS_VALLEYVIEW(dev_priv) ||
 322                           IS_CHERRYVIEW(dev_priv) ||
 323                           IS_GEN9_LP(dev_priv))))
 324                 return;
 325
 326         /*
 327          * We can't grab pps_mutex here due to deadlock with power_domain
 328          * mutex when power_domain functions are called while holding pps_mutex.
 329          * That also means that in order to use pps_pipe the code needs to
 330          * hold both a power domain reference and pps_mutex, and the power domain
 331          * reference get/put must be done while _not_ holding pps_mutex.
 332          * pps_{lock,unlock}() do these steps in the correct order, so one
 333          * should use them always.
 334          */
 335
 336         for_each_intel_dp(&dev_priv->drm, encoder) {
 337                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 338
 339                 drm_WARN_ON(&dev_priv->drm,
 340                             intel_dp->active_pipe != INVALID_PIPE);
 341
 342                 if (encoder->type != INTEL_OUTPUT_EDP)
 343                         continue;
 344
 345                 if (IS_GEN9_LP(dev_priv))
 346                         intel_dp->pps_reset = true;
 347                 else
 348                         intel_dp->pps_pipe = INVALID_PIPE;
 349         }
 350 }
 351
 352 struct pps_registers {
 353         i915_reg_t pp_ctrl;
 354         i915_reg_t pp_stat;
 355         i915_reg_t pp_on;
 356         i915_reg_t pp_off;
 357         i915_reg_t pp_div;
 358 };
 359
 360 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 361                                     struct pps_registers *regs)
 362 {
 363         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 364         int pps_idx = 0;
 365
 366         memset(regs, 0, sizeof(*regs));
 367
 368         if (IS_GEN9_LP(dev_priv))
 369                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 370         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 371                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 372
 373         regs->pp_ctrl = PP_CONTROL(pps_idx);
 374         regs->pp_stat = PP_STATUS(pps_idx);
 375         regs->pp_on = PP_ON_DELAYS(pps_idx);
 376         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 377
 378         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 379         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 380                 regs->pp_div = INVALID_MMIO_REG;
 381         else
 382                 regs->pp_div = PP_DIVISOR(pps_idx);
 383 }
 384
 385 static i915_reg_t
 386 _pp_ctrl_reg(struct intel_dp *intel_dp)
 387 {
 388         struct pps_registers regs;
 389
 390         intel_pps_get_registers(intel_dp, &regs);
 391
 392         return regs.pp_ctrl;
 393 }
 394
 395 static i915_reg_t
 396 _pp_stat_reg(struct intel_dp *intel_dp)
 397 {
 398         struct pps_registers regs;
 399
 400         intel_pps_get_registers(intel_dp, &regs);
 401
 402         return regs.pp_stat;
 403 }
 404
 405 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 406 {
 407         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 408
 409         lockdep_assert_held(&dev_priv->pps_mutex);
 410
 411         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 412             intel_dp->pps_pipe == INVALID_PIPE)
 413                 return false;
 414
 415         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
 416 }
 417
 418 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 419 {
 420         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 421
 422         lockdep_assert_held(&dev_priv->pps_mutex);
 423
 424         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 425             intel_dp->pps_pipe == INVALID_PIPE)
 426                 return false;
 427
 428         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 429 }
 430
 431 void intel_dp_check_edp(struct intel_dp *intel_dp)
 432 {
 433         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 434
 435         if (!intel_dp_is_edp(intel_dp))
 436                 return;
 437
 438         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 439                 drm_WARN(&dev_priv->drm, 1,
 440                          "eDP powered off while attempting aux channel communication.\n");
 441                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
 442                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
 443                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
 444         }
 445 }
 446
 447 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 448 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 449
 450 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
 451 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
 452
 453 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 454 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 455
 456 static void intel_pps_verify_state(struct intel_dp *intel_dp);
 457
 458 static void wait_panel_status(struct intel_dp *intel_dp,
 459                                        u32 mask,
 460                                        u32 value)
 461 {
 462         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 463         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 464
 465         lockdep_assert_held(&dev_priv->pps_mutex);
 466
 467         intel_pps_verify_state(intel_dp);
 468
 469         pp_stat_reg = _pp_stat_reg(intel_dp);
 470         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 471
 472         drm_dbg_kms(&dev_priv->drm,
 473                     "mask %08x value %08x status %08x control %08x\n",
 474                     mask, value,
 475                     intel_de_read(dev_priv, pp_stat_reg),
 476                     intel_de_read(dev_priv, pp_ctrl_reg));
 477
 478         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
 479                                        mask, value, 5000))
 480                 drm_err(&dev_priv->drm,
 481                         "Panel status timeout: status %08x control %08x\n",
 482                         intel_de_read(dev_priv, pp_stat_reg),
 483                         intel_de_read(dev_priv, pp_ctrl_reg));
 484
 485         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
 486 }
 487
 488 static void wait_panel_on(struct intel_dp *intel_dp)
 489 {
 490         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 491
 492         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
 493         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 494 }
 495
 496 static void wait_panel_off(struct intel_dp *intel_dp)
 497 {
 498         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 499
 500         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
 501         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 502 }
 503
 504 void wait_panel_power_cycle(struct intel_dp *intel_dp)
 505 {
 506         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 507         ktime_t panel_power_on_time;
 508         s64 panel_power_off_duration;
 509
 510         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
 511
 512         /* take the difference of currrent time and panel power off time
 513          * and then make panel wait for t11_t12 if needed. */
 514         panel_power_on_time = ktime_get_boottime();
 515         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
 516
 517         /* When we disable the VDD override bit last we have to do the manual
 518          * wait. */
 519         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
 520                 wait_remaining_ms_from_jiffies(jiffies,
 521                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
 522
 523         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 524 }
 525
 526 static void wait_backlight_on(struct intel_dp *intel_dp)
 527 {
 528         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
 529                                        intel_dp->backlight_on_delay);
 530 }
 531
 532 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
 533 {
 534         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
 535                                        intel_dp->backlight_off_delay);
 536 }
 537
 538 /* Read the current pp_control value, unlocking the register if it
 539  * is locked
 540  */
 541
 542 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
 543 {
 544         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 545         u32 control;
 546
 547         lockdep_assert_held(&dev_priv->pps_mutex);
 548
 549         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
 550         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
 551                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
 552                 control &= ~PANEL_UNLOCK_MASK;
 553                 control |= PANEL_UNLOCK_REGS;
 554         }
 555         return control;
 556 }
 557
 558 /*
 559  * Must be paired with edp_panel_vdd_off().
 560  * Must hold pps_mutex around the whole on/off sequence.
 561  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 562  */
 563 bool edp_panel_vdd_on(struct intel_dp *intel_dp)
 564 {
 565         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 566         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 567         u32 pp;
 568         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 569         bool need_to_disable = !intel_dp->want_panel_vdd;
 570
 571         lockdep_assert_held(&dev_priv->pps_mutex);
 572
 573         if (!intel_dp_is_edp(intel_dp))
 574                 return false;
 575
 576         cancel_delayed_work(&intel_dp->panel_vdd_work);
 577         intel_dp->want_panel_vdd = true;
 578
 579         if (edp_have_panel_vdd(intel_dp))
 580                 return need_to_disable;
 581
 582         drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
 583         intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
 584                                                         intel_aux_power_domain(dig_port));
 585
 586         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
 587                     dig_port->base.base.base.id,
 588                     dig_port->base.base.name);
 589
 590         if (!edp_have_panel_power(intel_dp))
 591                 wait_panel_power_cycle(intel_dp);
 592
 593         pp = ilk_get_pp_control(intel_dp);
 594         pp |= EDP_FORCE_VDD;
 595
 596         pp_stat_reg = _pp_stat_reg(intel_dp);
 597         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 598
 599         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 600         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 601         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 602                     intel_de_read(dev_priv, pp_stat_reg),
 603                     intel_de_read(dev_priv, pp_ctrl_reg));
 604         /*
 605          * If the panel wasn't on, delay before accessing aux channel
 606          */
 607         if (!edp_have_panel_power(intel_dp)) {
 608                 drm_dbg_kms(&dev_priv->drm,
 609                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
 610                             dig_port->base.base.base.id,
 611                             dig_port->base.base.name);
 612                 msleep(intel_dp->panel_power_up_delay);
 613         }
 614
 615         return need_to_disable;
 616 }
 617
 618 /*
 619  * Must be paired with intel_edp_panel_vdd_off() or
 620  * intel_edp_panel_off().
 621  * Nested calls to these functions are not allowed since
 622  * we drop the lock. Caller must use some higher level
 623  * locking to prevent nested calls from other threads.
 624  */
 625 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
 626 {
 627         intel_wakeref_t wakeref;
 628         bool vdd;
 629
 630         if (!intel_dp_is_edp(intel_dp))
 631                 return;
 632
 633         vdd = false;
 634         with_intel_pps_lock(intel_dp, wakeref)
 635                 vdd = edp_panel_vdd_on(intel_dp);
 636         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
 637                         dp_to_dig_port(intel_dp)->base.base.base.id,
 638                         dp_to_dig_port(intel_dp)->base.base.name);
 639 }
 640
 641 void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
 642 {
 643         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 644         struct intel_digital_port *dig_port =
 645                 dp_to_dig_port(intel_dp);
 646         u32 pp;
 647         i915_reg_t pp_stat_reg, pp_ctrl_reg;
 648
 649         lockdep_assert_held(&dev_priv->pps_mutex);
 650
 651         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
 652
 653         if (!edp_have_panel_vdd(intel_dp))
 654                 return;
 655
 656         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
 657                     dig_port->base.base.base.id,
 658                     dig_port->base.base.name);
 659
 660         pp = ilk_get_pp_control(intel_dp);
 661         pp &= ~EDP_FORCE_VDD;
 662
 663         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 664         pp_stat_reg = _pp_stat_reg(intel_dp);
 665
 666         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 667         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 668
 669         /* Make sure sequencer is idle before allowing subsequent activity */
 670         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
 671                     intel_de_read(dev_priv, pp_stat_reg),
 672                     intel_de_read(dev_priv, pp_ctrl_reg));
 673
 674         if ((pp & PANEL_POWER_ON) == 0)
 675                 intel_dp->panel_power_off_time = ktime_get_boottime();
 676
 677         intel_display_power_put(dev_priv,
 678                                 intel_aux_power_domain(dig_port),
 679                                 fetch_and_zero(&intel_dp->vdd_wakeref));
 680 }
 681
 682 void edp_panel_vdd_work(struct work_struct *__work)
 683 {
 684         struct intel_dp *intel_dp =
 685                 container_of(to_delayed_work(__work),
 686                              struct intel_dp, panel_vdd_work);
 687         intel_wakeref_t wakeref;
 688
 689         with_intel_pps_lock(intel_dp, wakeref) {
 690                 if (!intel_dp->want_panel_vdd)
 691                         edp_panel_vdd_off_sync(intel_dp);
 692         }
 693 }
 694
 695 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
 696 {
 697         unsigned long delay;
 698
 699         /*
 700          * Queue the timer to fire a long time from now (relative to the power
 701          * down delay) to keep the panel power up across a sequence of
 702          * operations.
 703          */
 704         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
 705         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
 706 }
 707
 708 /*
 709  * Must be paired with edp_panel_vdd_on().
 710  * Must hold pps_mutex around the whole on/off sequence.
 711  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 712  */
 713 void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
 714 {
 715         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 716
 717         lockdep_assert_held(&dev_priv->pps_mutex);
 718
 719         if (!intel_dp_is_edp(intel_dp))
 720                 return;
 721
 722         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
 723                         dp_to_dig_port(intel_dp)->base.base.base.id,
 724                         dp_to_dig_port(intel_dp)->base.base.name);
 725
 726         intel_dp->want_panel_vdd = false;
 727
 728         if (sync)
 729                 edp_panel_vdd_off_sync(intel_dp);
 730         else
 731                 edp_panel_vdd_schedule_off(intel_dp);
 732 }
 733
 734 void edp_panel_on(struct intel_dp *intel_dp)
 735 {
 736         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 737         u32 pp;
 738         i915_reg_t pp_ctrl_reg;
 739
 740         lockdep_assert_held(&dev_priv->pps_mutex);
 741
 742         if (!intel_dp_is_edp(intel_dp))
 743                 return;
 744
 745         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
 746                     dp_to_dig_port(intel_dp)->base.base.base.id,
 747                     dp_to_dig_port(intel_dp)->base.base.name);
 748
 749         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
 750                      "[ENCODER:%d:%s] panel power already on\n",
 751                      dp_to_dig_port(intel_dp)->base.base.base.id,
 752                      dp_to_dig_port(intel_dp)->base.base.name))
 753                 return;
 754
 755         wait_panel_power_cycle(intel_dp);
 756
 757         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 758         pp = ilk_get_pp_control(intel_dp);
 759         if (IS_GEN(dev_priv, 5)) {
 760                 /* ILK workaround: disable reset around power sequence */
 761                 pp &= ~PANEL_POWER_RESET;
 762                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 763                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 764         }
 765
 766         pp |= PANEL_POWER_ON;
 767         if (!IS_GEN(dev_priv, 5))
 768                 pp |= PANEL_POWER_RESET;
 769
 770         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 771         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 772
 773         wait_panel_on(intel_dp);
 774         intel_dp->last_power_on = jiffies;
 775
 776         if (IS_GEN(dev_priv, 5)) {
 777                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 778                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 779                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 780         }
 781 }
 782
 783 void intel_edp_panel_on(struct intel_dp *intel_dp)
 784 {
 785         intel_wakeref_t wakeref;
 786
 787         if (!intel_dp_is_edp(intel_dp))
 788                 return;
 789
 790         with_intel_pps_lock(intel_dp, wakeref)
 791                 edp_panel_on(intel_dp);
 792 }
 793
 794 void edp_panel_off(struct intel_dp *intel_dp)
 795 {
 796         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 797         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 798         u32 pp;
 799         i915_reg_t pp_ctrl_reg;
 800
 801         lockdep_assert_held(&dev_priv->pps_mutex);
 802
 803         if (!intel_dp_is_edp(intel_dp))
 804                 return;
 805
 806         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
 807                     dig_port->base.base.base.id, dig_port->base.base.name);
 808
 809         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
 810                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
 811                  dig_port->base.base.base.id, dig_port->base.base.name);
 812
 813         pp = ilk_get_pp_control(intel_dp);
 814         /* We need to switch off panel power _and_ force vdd, for otherwise some
 815          * panels get very unhappy and cease to work. */
 816         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
 817                 EDP_BLC_ENABLE);
 818
 819         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 820
 821         intel_dp->want_panel_vdd = false;
 822
 823         intel_de_write(dev_priv, pp_ctrl_reg, pp);
 824         intel_de_posting_read(dev_priv, pp_ctrl_reg);
 825
 826         wait_panel_off(intel_dp);
 827         intel_dp->panel_power_off_time = ktime_get_boottime();
 828
 829         /* We got a reference when we enabled the VDD. */
 830         intel_display_power_put(dev_priv,
 831                                 intel_aux_power_domain(dig_port),
 832                                 fetch_and_zero(&intel_dp->vdd_wakeref));
 833 }
 834
 835 void intel_edp_panel_off(struct intel_dp *intel_dp)
 836 {
 837         intel_wakeref_t wakeref;
 838
 839         if (!intel_dp_is_edp(intel_dp))
 840                 return;
 841
 842         with_intel_pps_lock(intel_dp, wakeref)
 843                 edp_panel_off(intel_dp);
 844 }
 845
 846 /* Enable backlight in the panel power control. */
 847 void _intel_edp_backlight_on(struct intel_dp *intel_dp)
 848 {
 849         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 850         intel_wakeref_t wakeref;
 851
 852         /*
 853          * If we enable the backlight right away following a panel power
 854          * on, we may see slight flicker as the panel syncs with the eDP
 855          * link.  So delay a bit to make sure the image is solid before
 856          * allowing it to appear.
 857          */
 858         wait_backlight_on(intel_dp);
 859
 860         with_intel_pps_lock(intel_dp, wakeref) {
 861                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 862                 u32 pp;
 863
 864                 pp = ilk_get_pp_control(intel_dp);
 865                 pp |= EDP_BLC_ENABLE;
 866
 867                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 868                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 869         }
 870 }
 871
 872 /* Disable backlight in the panel power control. */
 873 void _intel_edp_backlight_off(struct intel_dp *intel_dp)
 874 {
 875         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 876         intel_wakeref_t wakeref;
 877
 878         if (!intel_dp_is_edp(intel_dp))
 879                 return;
 880
 881         with_intel_pps_lock(intel_dp, wakeref) {
 882                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
 883                 u32 pp;
 884
 885                 pp = ilk_get_pp_control(intel_dp);
 886                 pp &= ~EDP_BLC_ENABLE;
 887
 888                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
 889                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
 890         }
 891
 892         intel_dp->last_backlight_off = jiffies;
 893         edp_wait_backlight_off(intel_dp);
 894 }
 895
 896 /*
 897  * Hook for controlling the panel power control backlight through the bl_power
 898  * sysfs attribute. Take care to handle multiple calls.
 899  */
 900 void intel_edp_backlight_power(struct intel_connector *connector, bool enable)
 901 {
 902         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 903         struct intel_dp *intel_dp = intel_attached_dp(connector);
 904         intel_wakeref_t wakeref;
 905         bool is_enabled;
 906
 907         is_enabled = false;
 908         with_intel_pps_lock(intel_dp, wakeref)
 909                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
 910         if (is_enabled == enable)
 911                 return;
 912
 913         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
 914                     enable ? "enable" : "disable");
 915
 916         if (enable)
 917                 _intel_edp_backlight_on(intel_dp);
 918         else
 919                 _intel_edp_backlight_off(intel_dp);
 920 }
 921
 922 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
 923 {
 924         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 925         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 926         enum pipe pipe = intel_dp->pps_pipe;
 927         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
 928
 929         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
 930
 931         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
 932                 return;
 933
 934         edp_panel_vdd_off_sync(intel_dp);
 935
 936         /*
 937          * VLV seems to get confused when multiple power sequencers
 938          * have the same port selected (even if only one has power/vdd
 939          * enabled). The failure manifests as vlv_wait_port_ready() failing
 940          * CHV on the other hand doesn't seem to mind having the same port
 941          * selected in multiple power sequencers, but let's clear the
 942          * port select always when logically disconnecting a power sequencer
 943          * from a port.
 944          */
 945         drm_dbg_kms(&dev_priv->drm,
 946                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
 947                     pipe_name(pipe), dig_port->base.base.base.id,
 948                     dig_port->base.base.name);
 949         intel_de_write(dev_priv, pp_on_reg, 0);
 950         intel_de_posting_read(dev_priv, pp_on_reg);
 951
 952         intel_dp->pps_pipe = INVALID_PIPE;
 953 }
 954
 955 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 956                                       enum pipe pipe)
 957 {
 958         struct intel_encoder *encoder;
 959
 960         lockdep_assert_held(&dev_priv->pps_mutex);
 961
 962         for_each_intel_dp(&dev_priv->drm, encoder) {
 963                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 964
 965                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
 966                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
 967                          pipe_name(pipe), encoder->base.base.id,
 968                          encoder->base.name);
 969
 970                 if (intel_dp->pps_pipe != pipe)
 971                         continue;
 972
 973                 drm_dbg_kms(&dev_priv->drm,
 974                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
 975                             pipe_name(pipe), encoder->base.base.id,
 976                             encoder->base.name);
 977
 978                 /* make sure vdd is off before we steal it */
 979                 vlv_detach_power_sequencer(intel_dp);
 980         }
 981 }
 982
 983 void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 984                                     const struct intel_crtc_state *crtc_state)
 985 {
 986         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 987         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 988         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 989
 990         lockdep_assert_held(&dev_priv->pps_mutex);
 991
 992         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
 993
 994         if (intel_dp->pps_pipe != INVALID_PIPE &&
 995             intel_dp->pps_pipe != crtc->pipe) {
 996                 /*
 997                  * If another power sequencer was being used on this
 998                  * port previously make sure to turn off vdd there while
 999                  * we still have control of it.
1000                  */
1001                 vlv_detach_power_sequencer(intel_dp);
1002         }
1003
1004         /*
1005          * We may be stealing the power
1006          * sequencer from another port.
1007          */
1008         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
1009
1010         intel_dp->active_pipe = crtc->pipe;
1011
1012         if (!intel_dp_is_edp(intel_dp))
1013                 return;
1014
1015         /* now it's all ours */
1016         intel_dp->pps_pipe = crtc->pipe;
1017
1018         drm_dbg_kms(&dev_priv->drm,
1019                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
1020                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
1021                     encoder->base.name);
1022
1023         /* init power sequencer on this pipe and port */
1024         intel_dp_init_panel_power_sequencer(intel_dp);
1025         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
1026 }
1027
1028 void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
1029 {
1030         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1031         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1032
1033         lockdep_assert_held(&dev_priv->pps_mutex);
1034
1035         if (!edp_have_panel_vdd(intel_dp))
1036                 return;
1037
1038         /*
1039          * The VDD bit needs a power domain reference, so if the bit is
1040          * already enabled when we boot or resume, grab this reference and
1041          * schedule a vdd off, so we don't hold on to the reference
1042          * indefinitely.
1043          */
1044         drm_dbg_kms(&dev_priv->drm,
1045                     "VDD left on by BIOS, adjusting state tracking\n");
1046         drm_WARN_ON(&dev_priv->drm, intel_dp->vdd_wakeref);
1047         intel_dp->vdd_wakeref = intel_display_power_get(dev_priv,
1048                                                         intel_aux_power_domain(dig_port));
1049
1050         edp_panel_vdd_schedule_off(intel_dp);
1051 }
1052
1053 bool intel_edp_have_power(struct intel_dp *intel_dp)
1054 {
1055         intel_wakeref_t wakeref;
1056         bool have_power = false;
1057
1058         with_intel_pps_lock(intel_dp, wakeref) {
1059                 have_power = edp_have_panel_power(intel_dp) &&
1060                                                   edp_have_panel_vdd(intel_dp);
1061         }
1062
1063         return have_power;
1064 }
1065
1066 void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
1067 {
1068         intel_dp->panel_power_off_time = ktime_get_boottime();
1069         intel_dp->last_power_on = jiffies;
1070         intel_dp->last_backlight_off = jiffies;
1071 }
1072
1073 static void
1074 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
1075 {
1076         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1077         u32 pp_on, pp_off, pp_ctl;
1078         struct pps_registers regs;
1079
1080         intel_pps_get_registers(intel_dp, &regs);
1081
1082         pp_ctl = ilk_get_pp_control(intel_dp);
1083
1084         /* Ensure PPS is unlocked */
1085         if (!HAS_DDI(dev_priv))
1086                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1087
1088         pp_on = intel_de_read(dev_priv, regs.pp_on);
1089         pp_off = intel_de_read(dev_priv, regs.pp_off);
1090
1091         /* Pull timing values out of registers */
1092         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
1093         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
1094         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
1095         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
1096
1097         if (i915_mmio_reg_valid(regs.pp_div)) {
1098                 u32 pp_div;
1099
1100                 pp_div = intel_de_read(dev_priv, regs.pp_div);
1101
1102                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
1103         } else {
1104                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
1105         }
1106 }
1107
1108 static void
1109 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
1110 {
1111         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1112                       state_name,
1113                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
1114 }
1115
1116 static void
1117 intel_pps_verify_state(struct intel_dp *intel_dp)
1118 {
1119         struct edp_power_seq hw;
1120         struct edp_power_seq *sw = &intel_dp->pps_delays;
1121
1122         intel_pps_readout_hw_state(intel_dp, &hw);
1123
1124         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
1125             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
1126                 DRM_ERROR("PPS state mismatch\n");
1127                 intel_pps_dump_state("sw", sw);
1128                 intel_pps_dump_state("hw", &hw);
1129         }
1130 }
1131
1132 static void
1133 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
1134 {
1135         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1136         struct edp_power_seq cur, vbt, spec,
1137                 *final = &intel_dp->pps_delays;
1138
1139         lockdep_assert_held(&dev_priv->pps_mutex);
1140
1141         /* already initialized? */
1142         if (final->t11_t12 != 0)
1143                 return;
1144
1145         intel_pps_readout_hw_state(intel_dp, &cur);
1146
1147         intel_pps_dump_state("cur", &cur);
1148
1149         vbt = dev_priv->vbt.edp.pps;
1150         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
1151          * of 500ms appears to be too short. Ocassionally the panel
1152          * just fails to power back on. Increasing the delay to 800ms
1153          * seems sufficient to avoid this problem.
1154          */
1155         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
1156                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
1157                 drm_dbg_kms(&dev_priv->drm,
1158                             "Increasing T12 panel delay as per the quirk to %d\n",
1159                             vbt.t11_t12);
1160         }
1161         /* T11_T12 delay is special and actually in units of 100ms, but zero
1162          * based in the hw (so we need to add 100 ms). But the sw vbt
1163          * table multiplies it with 1000 to make it in units of 100usec,
1164          * too. */
1165         vbt.t11_t12 += 100 * 10;
1166
1167         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
1168          * our hw here, which are all in 100usec. */
1169         spec.t1_t3 = 210 * 10;
1170         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
1171         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
1172         spec.t10 = 500 * 10;
1173         /* This one is special and actually in units of 100ms, but zero
1174          * based in the hw (so we need to add 100 ms). But the sw vbt
1175          * table multiplies it with 1000 to make it in units of 100usec,
1176          * too. */
1177         spec.t11_t12 = (510 + 100) * 10;
1178
1179         intel_pps_dump_state("vbt", &vbt);
1180
1181         /* Use the max of the register settings and vbt. If both are
1182          * unset, fall back to the spec limits. */
1183 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
1184                                        spec.field : \
1185                                        max(cur.field, vbt.field))
1186         assign_final(t1_t3);
1187         assign_final(t8);
1188         assign_final(t9);
1189         assign_final(t10);
1190         assign_final(t11_t12);
1191 #undef assign_final
1192
1193 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
1194         intel_dp->panel_power_up_delay = get_delay(t1_t3);
1195         intel_dp->backlight_on_delay = get_delay(t8);
1196         intel_dp->backlight_off_delay = get_delay(t9);
1197         intel_dp->panel_power_down_delay = get_delay(t10);
1198         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
1199 #undef get_delay
1200
1201         drm_dbg_kms(&dev_priv->drm,
1202                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
1203                     intel_dp->panel_power_up_delay,
1204                     intel_dp->panel_power_down_delay,
1205                     intel_dp->panel_power_cycle_delay);
1206
1207         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
1208                     intel_dp->backlight_on_delay,
1209                     intel_dp->backlight_off_delay);
1210
1211         /*
1212          * We override the HW backlight delays to 1 because we do manual waits
1213          * on them. For T8, even BSpec recommends doing it. For T9, if we
1214          * don't do this, we'll end up waiting for the backlight off delay
1215          * twice: once when we do the manual sleep, and once when we disable
1216          * the panel and wait for the PP_STATUS bit to become zero.
1217          */
1218         final->t8 = 1;
1219         final->t9 = 1;
1220
1221         /*
1222          * HW has only a 100msec granularity for t11_t12 so round it up
1223          * accordingly.
1224          */
1225         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
1226 }
1227
1228 static void
1229 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
1230                                               bool force_disable_vdd)
1231 {
1232         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1233         u32 pp_on, pp_off, port_sel = 0;
1234         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
1235         struct pps_registers regs;
1236         enum port port = dp_to_dig_port(intel_dp)->base.port;
1237         const struct edp_power_seq *seq = &intel_dp->pps_delays;
1238
1239         lockdep_assert_held(&dev_priv->pps_mutex);
1240
1241         intel_pps_get_registers(intel_dp, &regs);
1242
1243         /*
1244          * On some VLV machines the BIOS can leave the VDD
1245          * enabled even on power sequencers which aren't
1246          * hooked up to any port. This would mess up the
1247          * power domain tracking the first time we pick
1248          * one of these power sequencers for use since
1249          * edp_panel_vdd_on() would notice that the VDD was
1250          * already on and therefore wouldn't grab the power
1251          * domain reference. Disable VDD first to avoid this.
1252          * This also avoids spuriously turning the VDD on as
1253          * soon as the new power sequencer gets initialized.
1254          */
1255         if (force_disable_vdd) {
1256                 u32 pp = ilk_get_pp_control(intel_dp);
1257
1258                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
1259                          "Panel power already on\n");
1260
1261                 if (pp & EDP_FORCE_VDD)
1262                         drm_dbg_kms(&dev_priv->drm,
1263                                     "VDD already on, disabling first\n");
1264
1265                 pp &= ~EDP_FORCE_VDD;
1266
1267                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
1268         }
1269
1270         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
1271                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
1272         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
1273                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
1274
1275         /* Haswell doesn't have any port selection bits for the panel
1276          * power sequencer any more. */
1277         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1278                 port_sel = PANEL_PORT_SELECT_VLV(port);
1279         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1280                 switch (port) {
1281                 case PORT_A:
1282                         port_sel = PANEL_PORT_SELECT_DPA;
1283                         break;
1284                 case PORT_C:
1285                         port_sel = PANEL_PORT_SELECT_DPC;
1286                         break;
1287                 case PORT_D:
1288                         port_sel = PANEL_PORT_SELECT_DPD;
1289                         break;
1290                 default:
1291                         MISSING_CASE(port);
1292                         break;
1293                 }
1294         }
1295
1296         pp_on |= port_sel;
1297
1298         intel_de_write(dev_priv, regs.pp_on, pp_on);
1299         intel_de_write(dev_priv, regs.pp_off, pp_off);
1300
1301         /*
1302          * Compute the divisor for the pp clock, simply match the Bspec formula.
1303          */
1304         if (i915_mmio_reg_valid(regs.pp_div)) {
1305                 intel_de_write(dev_priv, regs.pp_div,
1306                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
1307         } else {
1308                 u32 pp_ctl;
1309
1310                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
1311                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
1312                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
1313                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
1314         }
1315
1316         drm_dbg_kms(&dev_priv->drm,
1317                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
1318                     intel_de_read(dev_priv, regs.pp_on),
1319                     intel_de_read(dev_priv, regs.pp_off),
1320                     i915_mmio_reg_valid(regs.pp_div) ?
1321                     intel_de_read(dev_priv, regs.pp_div) :
1322                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
1323 }
1324
1325 void intel_dp_pps_init(struct intel_dp *intel_dp)
1326 {
1327         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1328
1329         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1330                 vlv_initial_power_sequencer_setup(intel_dp);
1331         } else {
1332                 intel_dp_init_panel_power_sequencer(intel_dp);
1333                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1334         }
1335 }