drivers/gpu/drm/i915/display/intel_pipe_crc.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Author: Damien Lespiau <damien.lespiau@intel.com>
  24  *
  25  */
  26
  27 #include <linux/circ_buf.h>
  28 #include <linux/ctype.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/seq_file.h>
  31
  32 #include "intel_atomic.h"
  33 #include "intel_display_types.h"
  34 #include "intel_pipe_crc.h"
  35
  36 static const char * const pipe_crc_sources[] = {
  37         [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
  38         [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
  39         [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
  40         [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
  41         [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
  42         [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
  43         [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
  44         [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
  45         [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
  46         [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
  47         [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
  48         [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
  49         [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
  50         [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
  51 };
  52
  53 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
  54                                  u32 *val)
  55 {
  56         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
  57                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
  58
  59         switch (*source) {
  60         case INTEL_PIPE_CRC_SOURCE_PIPE:
  61                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
  62                 break;
  63         case INTEL_PIPE_CRC_SOURCE_NONE:
  64                 *val = 0;
  65                 break;
  66         default:
  67                 return -EINVAL;
  68         }
  69
  70         return 0;
  71 }
  72
  73 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
  74                                      enum pipe pipe,
  75                                      enum intel_pipe_crc_source *source)
  76 {
  77         struct drm_device *dev = &dev_priv->drm;
  78         struct intel_encoder *encoder;
  79         struct intel_crtc *crtc;
  80         struct intel_digital_port *dig_port;
  81         int ret = 0;
  82
  83         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
  84
  85         drm_modeset_lock_all(dev);
  86         for_each_intel_encoder(dev, encoder) {
  87                 if (!encoder->base.crtc)
  88                         continue;
  89
  90                 crtc = to_intel_crtc(encoder->base.crtc);
  91
  92                 if (crtc->pipe != pipe)
  93                         continue;
  94
  95                 switch (encoder->type) {
  96                 case INTEL_OUTPUT_TVOUT:
  97                         *source = INTEL_PIPE_CRC_SOURCE_TV;
  98                         break;
  99                 case INTEL_OUTPUT_DP:
 100                 case INTEL_OUTPUT_EDP:
 101                         dig_port = enc_to_dig_port(encoder);
 102                         switch (dig_port->base.port) {
 103                         case PORT_B:
 104                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
 105                                 break;
 106                         case PORT_C:
 107                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
 108                                 break;
 109                         case PORT_D:
 110                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
 111                                 break;
 112                         default:
 113                                 drm_WARN(dev, 1, "nonexisting DP port %c\n",
 114                                          port_name(dig_port->base.port));
 115                                 break;
 116                         }
 117                         break;
 118                 default:
 119                         break;
 120                 }
 121         }
 122         drm_modeset_unlock_all(dev);
 123
 124         return ret;
 125 }
 126
 127 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 128                                 enum pipe pipe,
 129                                 enum intel_pipe_crc_source *source,
 130                                 u32 *val)
 131 {
 132         bool need_stable_symbols = false;
 133
 134         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
 135                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
 136                 if (ret)
 137                         return ret;
 138         }
 139
 140         switch (*source) {
 141         case INTEL_PIPE_CRC_SOURCE_PIPE:
 142                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
 143                 break;
 144         case INTEL_PIPE_CRC_SOURCE_DP_B:
 145                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
 146                 need_stable_symbols = true;
 147                 break;
 148         case INTEL_PIPE_CRC_SOURCE_DP_C:
 149                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
 150                 need_stable_symbols = true;
 151                 break;
 152         case INTEL_PIPE_CRC_SOURCE_DP_D:
 153                 if (!IS_CHERRYVIEW(dev_priv))
 154                         return -EINVAL;
 155                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
 156                 need_stable_symbols = true;
 157                 break;
 158         case INTEL_PIPE_CRC_SOURCE_NONE:
 159                 *val = 0;
 160                 break;
 161         default:
 162                 return -EINVAL;
 163         }
 164
 165         /*
 166          * When the pipe CRC tap point is after the transcoders we need
 167          * to tweak symbol-level features to produce a deterministic series of
 168          * symbols for a given frame. We need to reset those features only once
 169          * a frame (instead of every nth symbol):
 170          *   - DC-balance: used to ensure a better clock recovery from the data
 171          *     link (SDVO)
 172          *   - DisplayPort scrambling: used for EMI reduction
 173          */
 174         if (need_stable_symbols) {
 175                 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
 176
 177                 tmp |= DC_BALANCE_RESET_VLV;
 178                 switch (pipe) {
 179                 case PIPE_A:
 180                         tmp |= PIPE_A_SCRAMBLE_RESET;
 181                         break;
 182                 case PIPE_B:
 183                         tmp |= PIPE_B_SCRAMBLE_RESET;
 184                         break;
 185                 case PIPE_C:
 186                         tmp |= PIPE_C_SCRAMBLE_RESET;
 187                         break;
 188                 default:
 189                         return -EINVAL;
 190                 }
 191                 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
 192         }
 193
 194         return 0;
 195 }
 196
 197 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 198                                  enum pipe pipe,
 199                                  enum intel_pipe_crc_source *source,
 200                                  u32 *val)
 201 {
 202         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
 203                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
 204                 if (ret)
 205                         return ret;
 206         }
 207
 208         switch (*source) {
 209         case INTEL_PIPE_CRC_SOURCE_PIPE:
 210                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
 211                 break;
 212         case INTEL_PIPE_CRC_SOURCE_TV:
 213                 if (!SUPPORTS_TV(dev_priv))
 214                         return -EINVAL;
 215                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
 216                 break;
 217         case INTEL_PIPE_CRC_SOURCE_NONE:
 218                 *val = 0;
 219                 break;
 220         default:
 221                 /*
 222                  * The DP CRC source doesn't work on g4x.
 223                  * It can be made to work to some degree by selecting
 224                  * the correct CRC source before the port is enabled,
 225                  * and not touching the CRC source bits again until
 226                  * the port is disabled. But even then the bits
 227                  * eventually get stuck and a reboot is needed to get
 228                  * working CRCs on the pipe again. Let's simply
 229                  * refuse to use DP CRCs on g4x.
 230                  */
 231                 return -EINVAL;
 232         }
 233
 234         return 0;
 235 }
 236
 237 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
 238                                          enum pipe pipe)
 239 {
 240         u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
 241
 242         switch (pipe) {
 243         case PIPE_A:
 244                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
 245                 break;
 246         case PIPE_B:
 247                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
 248                 break;
 249         case PIPE_C:
 250                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
 251                 break;
 252         default:
 253                 return;
 254         }
 255         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
 256                 tmp &= ~DC_BALANCE_RESET_VLV;
 257         intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
 258 }
 259
 260 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
 261                                 u32 *val)
 262 {
 263         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 264                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
 265
 266         switch (*source) {
 267         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 268                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
 269                 break;
 270         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 271                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
 272                 break;
 273         case INTEL_PIPE_CRC_SOURCE_PIPE:
 274                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
 275                 break;
 276         case INTEL_PIPE_CRC_SOURCE_NONE:
 277                 *val = 0;
 278                 break;
 279         default:
 280                 return -EINVAL;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static void
 287 intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
 288 {
 289         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 290         struct intel_crtc_state *pipe_config;
 291         struct drm_atomic_state *state;
 292         struct drm_modeset_acquire_ctx ctx;
 293         int ret;
 294
 295         drm_modeset_acquire_init(&ctx, 0);
 296
 297         state = drm_atomic_state_alloc(&dev_priv->drm);
 298         if (!state) {
 299                 ret = -ENOMEM;
 300                 goto unlock;
 301         }
 302
 303         state->acquire_ctx = &ctx;
 304
 305 retry:
 306         pipe_config = intel_atomic_get_crtc_state(state, crtc);
 307         if (IS_ERR(pipe_config)) {
 308                 ret = PTR_ERR(pipe_config);
 309                 goto put_state;
 310         }
 311
 312         pipe_config->uapi.mode_changed = pipe_config->has_psr;
 313         pipe_config->crc_enabled = enable;
 314
 315         if (IS_HASWELL(dev_priv) &&
 316             pipe_config->hw.active && crtc->pipe == PIPE_A &&
 317             pipe_config->cpu_transcoder == TRANSCODER_EDP)
 318                 pipe_config->uapi.mode_changed = true;
 319
 320         ret = drm_atomic_commit(state);
 321
 322 put_state:
 323         if (ret == -EDEADLK) {
 324                 drm_atomic_state_clear(state);
 325                 drm_modeset_backoff(&ctx);
 326                 goto retry;
 327         }
 328
 329         drm_atomic_state_put(state);
 330 unlock:
 331         drm_WARN(&dev_priv->drm, ret,
 332                  "Toggling workaround to %i returns %i\n", enable, ret);
 333         drm_modeset_drop_locks(&ctx);
 334         drm_modeset_acquire_fini(&ctx);
 335 }
 336
 337 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 338                                 enum pipe pipe,
 339                                 enum intel_pipe_crc_source *source,
 340                                 u32 *val)
 341 {
 342         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 343                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
 344
 345         switch (*source) {
 346         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 347                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
 348                 break;
 349         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 350                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
 351                 break;
 352         case INTEL_PIPE_CRC_SOURCE_PIPE:
 353                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
 354                 break;
 355         case INTEL_PIPE_CRC_SOURCE_NONE:
 356                 *val = 0;
 357                 break;
 358         default:
 359                 return -EINVAL;
 360         }
 361
 362         return 0;
 363 }
 364
 365 static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 366                                 enum pipe pipe,
 367                                 enum intel_pipe_crc_source *source,
 368                                 u32 *val)
 369 {
 370         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 371                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
 372
 373         switch (*source) {
 374         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 375                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
 376                 break;
 377         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 378                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
 379                 break;
 380         case INTEL_PIPE_CRC_SOURCE_PLANE3:
 381                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
 382                 break;
 383         case INTEL_PIPE_CRC_SOURCE_PLANE4:
 384                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
 385                 break;
 386         case INTEL_PIPE_CRC_SOURCE_PLANE5:
 387                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
 388                 break;
 389         case INTEL_PIPE_CRC_SOURCE_PLANE6:
 390                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
 391                 break;
 392         case INTEL_PIPE_CRC_SOURCE_PLANE7:
 393                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
 394                 break;
 395         case INTEL_PIPE_CRC_SOURCE_PIPE:
 396                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
 397                 break;
 398         case INTEL_PIPE_CRC_SOURCE_NONE:
 399                 *val = 0;
 400                 break;
 401         default:
 402                 return -EINVAL;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
 409                                enum pipe pipe,
 410                                enum intel_pipe_crc_source *source, u32 *val)
 411 {
 412         if (IS_GEN(dev_priv, 2))
 413                 return i8xx_pipe_crc_ctl_reg(source, val);
 414         else if (INTEL_GEN(dev_priv) < 5)
 415                 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 416         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 417                 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 418         else if (IS_GEN_RANGE(dev_priv, 5, 6))
 419                 return ilk_pipe_crc_ctl_reg(source, val);
 420         else if (INTEL_GEN(dev_priv) < 9)
 421                 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 422         else
 423                 return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 424 }
 425
 426 static int
 427 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
 428 {
 429         int i;
 430
 431         if (!buf) {
 432                 *s = INTEL_PIPE_CRC_SOURCE_NONE;
 433                 return 0;
 434         }
 435
 436         i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
 437         if (i < 0)
 438                 return i;
 439
 440         *s = i;
 441         return 0;
 442 }
 443
 444 void intel_crtc_crc_init(struct intel_crtc *crtc)
 445 {
 446         struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
 447
 448         spin_lock_init(&pipe_crc->lock);
 449 }
 450
 451 static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
 452                                  const enum intel_pipe_crc_source source)
 453 {
 454         switch (source) {
 455         case INTEL_PIPE_CRC_SOURCE_PIPE:
 456         case INTEL_PIPE_CRC_SOURCE_NONE:
 457                 return 0;
 458         default:
 459                 return -EINVAL;
 460         }
 461 }
 462
 463 static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
 464                                  const enum intel_pipe_crc_source source)
 465 {
 466         switch (source) {
 467         case INTEL_PIPE_CRC_SOURCE_PIPE:
 468         case INTEL_PIPE_CRC_SOURCE_TV:
 469         case INTEL_PIPE_CRC_SOURCE_NONE:
 470                 return 0;
 471         default:
 472                 return -EINVAL;
 473         }
 474 }
 475
 476 static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
 477                                 const enum intel_pipe_crc_source source)
 478 {
 479         switch (source) {
 480         case INTEL_PIPE_CRC_SOURCE_PIPE:
 481         case INTEL_PIPE_CRC_SOURCE_DP_B:
 482         case INTEL_PIPE_CRC_SOURCE_DP_C:
 483         case INTEL_PIPE_CRC_SOURCE_DP_D:
 484         case INTEL_PIPE_CRC_SOURCE_NONE:
 485                 return 0;
 486         default:
 487                 return -EINVAL;
 488         }
 489 }
 490
 491 static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
 492                                 const enum intel_pipe_crc_source source)
 493 {
 494         switch (source) {
 495         case INTEL_PIPE_CRC_SOURCE_PIPE:
 496         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 497         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 498         case INTEL_PIPE_CRC_SOURCE_NONE:
 499                 return 0;
 500         default:
 501                 return -EINVAL;
 502         }
 503 }
 504
 505 static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
 506                                 const enum intel_pipe_crc_source source)
 507 {
 508         switch (source) {
 509         case INTEL_PIPE_CRC_SOURCE_PIPE:
 510         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 511         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 512         case INTEL_PIPE_CRC_SOURCE_NONE:
 513                 return 0;
 514         default:
 515                 return -EINVAL;
 516         }
 517 }
 518
 519 static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
 520                                 const enum intel_pipe_crc_source source)
 521 {
 522         switch (source) {
 523         case INTEL_PIPE_CRC_SOURCE_PIPE:
 524         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 525         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 526         case INTEL_PIPE_CRC_SOURCE_PLANE3:
 527         case INTEL_PIPE_CRC_SOURCE_PLANE4:
 528         case INTEL_PIPE_CRC_SOURCE_PLANE5:
 529         case INTEL_PIPE_CRC_SOURCE_PLANE6:
 530         case INTEL_PIPE_CRC_SOURCE_PLANE7:
 531         case INTEL_PIPE_CRC_SOURCE_NONE:
 532                 return 0;
 533         default:
 534                 return -EINVAL;
 535         }
 536 }
 537
 538 static int
 539 intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
 540                           const enum intel_pipe_crc_source source)
 541 {
 542         if (IS_GEN(dev_priv, 2))
 543                 return i8xx_crc_source_valid(dev_priv, source);
 544         else if (INTEL_GEN(dev_priv) < 5)
 545                 return i9xx_crc_source_valid(dev_priv, source);
 546         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 547                 return vlv_crc_source_valid(dev_priv, source);
 548         else if (IS_GEN_RANGE(dev_priv, 5, 6))
 549                 return ilk_crc_source_valid(dev_priv, source);
 550         else if (INTEL_GEN(dev_priv) < 9)
 551                 return ivb_crc_source_valid(dev_priv, source);
 552         else
 553                 return skl_crc_source_valid(dev_priv, source);
 554 }
 555
 556 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
 557                                               size_t *count)
 558 {
 559         *count = ARRAY_SIZE(pipe_crc_sources);
 560         return pipe_crc_sources;
 561 }
 562
 563 int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
 564                                  size_t *values_cnt)
 565 {
 566         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 567         enum intel_pipe_crc_source source;
 568
 569         if (display_crc_ctl_parse_source(source_name, &source) < 0) {
 570                 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
 571                 return -EINVAL;
 572         }
 573
 574         if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
 575             intel_is_valid_crc_source(dev_priv, source) == 0) {
 576                 *values_cnt = 5;
 577                 return 0;
 578         }
 579
 580         return -EINVAL;
 581 }
 582
 583 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name)
 584 {
 585         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 587         struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc;
 588         enum intel_display_power_domain power_domain;
 589         enum intel_pipe_crc_source source;
 590         intel_wakeref_t wakeref;
 591         u32 val = 0; /* shut up gcc */
 592         int ret = 0;
 593         bool enable;
 594
 595         if (display_crc_ctl_parse_source(source_name, &source) < 0) {
 596                 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
 597                 return -EINVAL;
 598         }
 599
 600         power_domain = POWER_DOMAIN_PIPE(crtc->index);
 601         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 602         if (!wakeref) {
 603                 drm_dbg_kms(&dev_priv->drm,
 604                             "Trying to capture CRC while pipe is off\n");
 605                 return -EIO;
 606         }
 607
 608         enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
 609         if (enable)
 610                 intel_crtc_crc_setup_workarounds(to_intel_crtc(crtc), true);
 611
 612         ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val);
 613         if (ret != 0)
 614                 goto out;
 615
 616         pipe_crc->source = source;
 617         intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val);
 618         intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index));
 619
 620         if (!source) {
 621                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 622                         vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
 623         }
 624
 625         pipe_crc->skipped = 0;
 626
 627 out:
 628         if (!enable)
 629                 intel_crtc_crc_setup_workarounds(to_intel_crtc(crtc), false);
 630
 631         intel_display_power_put(dev_priv, power_domain, wakeref);
 632
 633         return ret;
 634 }
 635
 636 void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
 637 {
 638         struct drm_crtc *crtc = &intel_crtc->base;
 639         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 640         struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc;
 641         u32 val = 0;
 642
 643         if (!crtc->crc.opened)
 644                 return;
 645
 646         if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val) < 0)
 647                 return;
 648
 649         /* Don't need pipe_crc->lock here, IRQs are not generated. */
 650         pipe_crc->skipped = 0;
 651
 652         intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val);
 653         intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index));
 654 }
 655
 656 void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
 657 {
 658         struct drm_crtc *crtc = &intel_crtc->base;
 659         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 660         struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc;
 661
 662         /* Swallow crc's until we stop generating them. */
 663         spin_lock_irq(&pipe_crc->lock);
 664         pipe_crc->skipped = INT_MIN;
 665         spin_unlock_irq(&pipe_crc->lock);
 666
 667         intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), 0);
 668         intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index));
 669         intel_synchronize_irq(dev_priv);
 670 }