drivers/gpu/drm/i915/display/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28
  29 #include <drm/drm_fourcc.h>
  30
  31 #include "gem/i915_gem_pm.h"
  32 #include "gt/intel_ring.h"
  33
  34 #include "i915_drv.h"
  35 #include "i915_reg.h"
  36 #include "intel_display_types.h"
  37 #include "intel_frontbuffer.h"
  38 #include "intel_overlay.h"
  39
  40 /* Limits for overlay size. According to intel doc, the real limits are:
  41  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  42  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  43  * the mininum of both.  */
  44 #define IMAGE_MAX_WIDTH         2048
  45 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  46 /* on 830 and 845 these large limits result in the card hanging */
  47 #define IMAGE_MAX_WIDTH_LEGACY  1024
  48 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  49
  50 /* overlay register definitions */
  51 /* OCMD register */
  52 #define OCMD_TILED_SURFACE      (0x1<<19)
  53 #define OCMD_MIRROR_MASK        (0x3<<17)
  54 #define OCMD_MIRROR_MODE        (0x3<<17)
  55 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  56 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  57 #define OCMD_MIRROR_BOTH        (0x3<<17)
  58 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  59 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  60 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  61 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  62 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  63 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  64 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  65 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  66 #define OCMD_YUV_422_PACKED     (0x8<<10)
  67 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  68 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  69 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  70 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  71 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  72 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  73 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  74 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  75 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  76 #define OCMD_TEST_MODE          (0x1<<4)
  77 #define OCMD_BUFFER_SELECT      (0x3<<2)
  78 #define OCMD_BUFFER0            (0x0<<2)
  79 #define OCMD_BUFFER1            (0x1<<2)
  80 #define OCMD_FIELD_SELECT       (0x1<<2)
  81 #define OCMD_FIELD0             (0x0<<1)
  82 #define OCMD_FIELD1             (0x1<<1)
  83 #define OCMD_ENABLE             (0x1<<0)
  84
  85 /* OCONFIG register */
  86 #define OCONF_PIPE_MASK         (0x1<<18)
  87 #define OCONF_PIPE_A            (0x0<<18)
  88 #define OCONF_PIPE_B            (0x1<<18)
  89 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  90 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  91 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  92 #define OCONF_CSC_BYPASS        (0x1<<4)
  93 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  94 #define OCONF_TEST_MODE         (0x1<<2)
  95 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  96 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  97
  98 /* DCLRKM (dst-key) register */
  99 #define DST_KEY_ENABLE          (0x1<<31)
 100 #define CLK_RGB24_MASK          0x0
 101 #define CLK_RGB16_MASK          0x070307
 102 #define CLK_RGB15_MASK          0x070707
 103 #define CLK_RGB8I_MASK          0xffffff
 104
 105 #define RGB16_TO_COLORKEY(c) \
 106         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 107 #define RGB15_TO_COLORKEY(c) \
 108         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 109
 110 /* overlay flip addr flag */
 111 #define OFC_UPDATE              0x1
 112
 113 /* polyphase filter coefficients */
 114 #define N_HORIZ_Y_TAPS          5
 115 #define N_VERT_Y_TAPS           3
 116 #define N_HORIZ_UV_TAPS         3
 117 #define N_VERT_UV_TAPS          3
 118 #define N_PHASES                17
 119 #define MAX_TAPS                5
 120
 121 /* memory bufferd overlay registers */
 122 struct overlay_registers {
 123         u32 OBUF_0Y;
 124         u32 OBUF_1Y;
 125         u32 OBUF_0U;
 126         u32 OBUF_0V;
 127         u32 OBUF_1U;
 128         u32 OBUF_1V;
 129         u32 OSTRIDE;
 130         u32 YRGB_VPH;
 131         u32 UV_VPH;
 132         u32 HORZ_PH;
 133         u32 INIT_PHS;
 134         u32 DWINPOS;
 135         u32 DWINSZ;
 136         u32 SWIDTH;
 137         u32 SWIDTHSW;
 138         u32 SHEIGHT;
 139         u32 YRGBSCALE;
 140         u32 UVSCALE;
 141         u32 OCLRC0;
 142         u32 OCLRC1;
 143         u32 DCLRKV;
 144         u32 DCLRKM;
 145         u32 SCLRKVH;
 146         u32 SCLRKVL;
 147         u32 SCLRKEN;
 148         u32 OCONFIG;
 149         u32 OCMD;
 150         u32 RESERVED1; /* 0x6C */
 151         u32 OSTART_0Y;
 152         u32 OSTART_1Y;
 153         u32 OSTART_0U;
 154         u32 OSTART_0V;
 155         u32 OSTART_1U;
 156         u32 OSTART_1V;
 157         u32 OTILEOFF_0Y;
 158         u32 OTILEOFF_1Y;
 159         u32 OTILEOFF_0U;
 160         u32 OTILEOFF_0V;
 161         u32 OTILEOFF_1U;
 162         u32 OTILEOFF_1V;
 163         u32 FASTHSCALE; /* 0xA0 */
 164         u32 UVSCALEV; /* 0xA4 */
 165         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 166         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 167         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 168         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 169         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 170         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 171         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 172         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 173         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 174 };
 175
 176 struct intel_overlay {
 177         struct drm_i915_private *i915;
 178         struct intel_context *context;
 179         struct intel_crtc *crtc;
 180         struct i915_vma *vma;
 181         struct i915_vma *old_vma;
 182         bool active;
 183         bool pfit_active;
 184         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 185         u32 color_key:24;
 186         u32 color_key_enabled:1;
 187         u32 brightness, contrast, saturation;
 188         u32 old_xscale, old_yscale;
 189         /* register access */
 190         struct drm_i915_gem_object *reg_bo;
 191         struct overlay_registers __iomem *regs;
 192         u32 flip_addr;
 193         /* flip handling */
 194         struct i915_active last_flip;
 195         void (*flip_complete)(struct intel_overlay *ovl);
 196 };
 197
 198 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
 199                                       bool enable)
 200 {
 201         struct pci_dev *pdev = dev_priv->drm.pdev;
 202         u8 val;
 203
 204         /* WA_OVERLAY_CLKGATE:alm */
 205         if (enable)
 206                 intel_de_write(dev_priv, DSPCLK_GATE_D, 0);
 207         else
 208                 intel_de_write(dev_priv, DSPCLK_GATE_D,
 209                                OVRUNIT_CLOCK_GATE_DISABLE);
 210
 211         /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
 212         pci_bus_read_config_byte(pdev->bus,
 213                                  PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
 214         if (enable)
 215                 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
 216         else
 217                 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
 218         pci_bus_write_config_byte(pdev->bus,
 219                                   PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
 220 }
 221
 222 static struct i915_request *
 223 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *))
 224 {
 225         struct i915_request *rq;
 226         int err;
 227
 228         overlay->flip_complete = fn;
 229
 230         rq = i915_request_create(overlay->context);
 231         if (IS_ERR(rq))
 232                 return rq;
 233
 234         err = i915_active_add_request(&overlay->last_flip, rq);
 235         if (err) {
 236                 i915_request_add(rq);
 237                 return ERR_PTR(err);
 238         }
 239
 240         return rq;
 241 }
 242
 243 /* overlay needs to be disable in OCMD reg */
 244 static int intel_overlay_on(struct intel_overlay *overlay)
 245 {
 246         struct drm_i915_private *dev_priv = overlay->i915;
 247         struct i915_request *rq;
 248         u32 *cs;
 249
 250         drm_WARN_ON(&dev_priv->drm, overlay->active);
 251
 252         rq = alloc_request(overlay, NULL);
 253         if (IS_ERR(rq))
 254                 return PTR_ERR(rq);
 255
 256         cs = intel_ring_begin(rq, 4);
 257         if (IS_ERR(cs)) {
 258                 i915_request_add(rq);
 259                 return PTR_ERR(cs);
 260         }
 261
 262         overlay->active = true;
 263
 264         if (IS_I830(dev_priv))
 265                 i830_overlay_clock_gating(dev_priv, false);
 266
 267         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
 268         *cs++ = overlay->flip_addr | OFC_UPDATE;
 269         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 270         *cs++ = MI_NOOP;
 271         intel_ring_advance(rq, cs);
 272
 273         i915_request_add(rq);
 274
 275         return i915_active_wait(&overlay->last_flip);
 276 }
 277
 278 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 279                                        struct i915_vma *vma)
 280 {
 281         enum pipe pipe = overlay->crtc->pipe;
 282         struct intel_frontbuffer *from = NULL, *to = NULL;
 283
 284         WARN_ON(overlay->old_vma);
 285
 286         if (overlay->vma)
 287                 from = intel_frontbuffer_get(overlay->vma->obj);
 288         if (vma)
 289                 to = intel_frontbuffer_get(vma->obj);
 290
 291         intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe));
 292
 293         if (to)
 294                 intel_frontbuffer_put(to);
 295         if (from)
 296                 intel_frontbuffer_put(from);
 297
 298         intel_frontbuffer_flip_prepare(overlay->i915,
 299                                        INTEL_FRONTBUFFER_OVERLAY(pipe));
 300
 301         overlay->old_vma = overlay->vma;
 302         if (vma)
 303                 overlay->vma = i915_vma_get(vma);
 304         else
 305                 overlay->vma = NULL;
 306 }
 307
 308 /* overlay needs to be enabled in OCMD reg */
 309 static int intel_overlay_continue(struct intel_overlay *overlay,
 310                                   struct i915_vma *vma,
 311                                   bool load_polyphase_filter)
 312 {
 313         struct drm_i915_private *dev_priv = overlay->i915;
 314         struct i915_request *rq;
 315         u32 flip_addr = overlay->flip_addr;
 316         u32 tmp, *cs;
 317
 318         drm_WARN_ON(&dev_priv->drm, !overlay->active);
 319
 320         if (load_polyphase_filter)
 321                 flip_addr |= OFC_UPDATE;
 322
 323         /* check for underruns */
 324         tmp = intel_de_read(dev_priv, DOVSTA);
 325         if (tmp & (1 << 17))
 326                 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp);
 327
 328         rq = alloc_request(overlay, NULL);
 329         if (IS_ERR(rq))
 330                 return PTR_ERR(rq);
 331
 332         cs = intel_ring_begin(rq, 2);
 333         if (IS_ERR(cs)) {
 334                 i915_request_add(rq);
 335                 return PTR_ERR(cs);
 336         }
 337
 338         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 339         *cs++ = flip_addr;
 340         intel_ring_advance(rq, cs);
 341
 342         intel_overlay_flip_prepare(overlay, vma);
 343         i915_request_add(rq);
 344
 345         return 0;
 346 }
 347
 348 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 349 {
 350         struct i915_vma *vma;
 351
 352         vma = fetch_and_zero(&overlay->old_vma);
 353         if (WARN_ON(!vma))
 354                 return;
 355
 356         intel_frontbuffer_flip_complete(overlay->i915,
 357                                         INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 358
 359         i915_gem_object_unpin_from_display_plane(vma);
 360         i915_vma_put(vma);
 361 }
 362
 363 static void
 364 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
 365 {
 366         intel_overlay_release_old_vma(overlay);
 367 }
 368
 369 static void intel_overlay_off_tail(struct intel_overlay *overlay)
 370 {
 371         struct drm_i915_private *dev_priv = overlay->i915;
 372
 373         intel_overlay_release_old_vma(overlay);
 374
 375         overlay->crtc->overlay = NULL;
 376         overlay->crtc = NULL;
 377         overlay->active = false;
 378
 379         if (IS_I830(dev_priv))
 380                 i830_overlay_clock_gating(dev_priv, true);
 381 }
 382
 383 static void
 384 intel_overlay_last_flip_retire(struct i915_active *active)
 385 {
 386         struct intel_overlay *overlay =
 387                 container_of(active, typeof(*overlay), last_flip);
 388
 389         if (overlay->flip_complete)
 390                 overlay->flip_complete(overlay);
 391 }
 392
 393 /* overlay needs to be disabled in OCMD reg */
 394 static int intel_overlay_off(struct intel_overlay *overlay)
 395 {
 396         struct i915_request *rq;
 397         u32 *cs, flip_addr = overlay->flip_addr;
 398
 399         WARN_ON(!overlay->active);
 400
 401         /* According to intel docs the overlay hw may hang (when switching
 402          * off) without loading the filter coeffs. It is however unclear whether
 403          * this applies to the disabling of the overlay or to the switching off
 404          * of the hw. Do it in both cases */
 405         flip_addr |= OFC_UPDATE;
 406
 407         rq = alloc_request(overlay, intel_overlay_off_tail);
 408         if (IS_ERR(rq))
 409                 return PTR_ERR(rq);
 410
 411         cs = intel_ring_begin(rq, 6);
 412         if (IS_ERR(cs)) {
 413                 i915_request_add(rq);
 414                 return PTR_ERR(cs);
 415         }
 416
 417         /* wait for overlay to go idle */
 418         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 419         *cs++ = flip_addr;
 420         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 421
 422         /* turn overlay off */
 423         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
 424         *cs++ = flip_addr;
 425         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 426
 427         intel_ring_advance(rq, cs);
 428
 429         intel_overlay_flip_prepare(overlay, NULL);
 430         i915_request_add(rq);
 431
 432         return i915_active_wait(&overlay->last_flip);
 433 }
 434
 435 /* recover from an interruption due to a signal
 436  * We have to be careful not to repeat work forever an make forward progess. */
 437 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 438 {
 439         return i915_active_wait(&overlay->last_flip);
 440 }
 441
 442 /* Wait for pending overlay flip and release old frame.
 443  * Needs to be called before the overlay register are changed
 444  * via intel_overlay_(un)map_regs
 445  */
 446 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 447 {
 448         struct drm_i915_private *dev_priv = overlay->i915;
 449         struct i915_request *rq;
 450         u32 *cs;
 451
 452         /*
 453          * Only wait if there is actually an old frame to release to
 454          * guarantee forward progress.
 455          */
 456         if (!overlay->old_vma)
 457                 return 0;
 458
 459         if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
 460                 intel_overlay_release_old_vid_tail(overlay);
 461                 return 0;
 462         }
 463
 464         rq = alloc_request(overlay, intel_overlay_release_old_vid_tail);
 465         if (IS_ERR(rq))
 466                 return PTR_ERR(rq);
 467
 468         cs = intel_ring_begin(rq, 2);
 469         if (IS_ERR(cs)) {
 470                 i915_request_add(rq);
 471                 return PTR_ERR(cs);
 472         }
 473
 474         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 475         *cs++ = MI_NOOP;
 476         intel_ring_advance(rq, cs);
 477
 478         i915_request_add(rq);
 479
 480         return i915_active_wait(&overlay->last_flip);
 481 }
 482
 483 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 484 {
 485         struct intel_overlay *overlay = dev_priv->overlay;
 486
 487         if (!overlay)
 488                 return;
 489
 490         overlay->old_xscale = 0;
 491         overlay->old_yscale = 0;
 492         overlay->crtc = NULL;
 493         overlay->active = false;
 494 }
 495
 496 static int packed_depth_bytes(u32 format)
 497 {
 498         switch (format & I915_OVERLAY_DEPTH_MASK) {
 499         case I915_OVERLAY_YUV422:
 500                 return 4;
 501         case I915_OVERLAY_YUV411:
 502                 /* return 6; not implemented */
 503         default:
 504                 return -EINVAL;
 505         }
 506 }
 507
 508 static int packed_width_bytes(u32 format, short width)
 509 {
 510         switch (format & I915_OVERLAY_DEPTH_MASK) {
 511         case I915_OVERLAY_YUV422:
 512                 return width << 1;
 513         default:
 514                 return -EINVAL;
 515         }
 516 }
 517
 518 static int uv_hsubsampling(u32 format)
 519 {
 520         switch (format & I915_OVERLAY_DEPTH_MASK) {
 521         case I915_OVERLAY_YUV422:
 522         case I915_OVERLAY_YUV420:
 523                 return 2;
 524         case I915_OVERLAY_YUV411:
 525         case I915_OVERLAY_YUV410:
 526                 return 4;
 527         default:
 528                 return -EINVAL;
 529         }
 530 }
 531
 532 static int uv_vsubsampling(u32 format)
 533 {
 534         switch (format & I915_OVERLAY_DEPTH_MASK) {
 535         case I915_OVERLAY_YUV420:
 536         case I915_OVERLAY_YUV410:
 537                 return 2;
 538         case I915_OVERLAY_YUV422:
 539         case I915_OVERLAY_YUV411:
 540                 return 1;
 541         default:
 542                 return -EINVAL;
 543         }
 544 }
 545
 546 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 547 {
 548         u32 sw;
 549
 550         if (IS_GEN(dev_priv, 2))
 551                 sw = ALIGN((offset & 31) + width, 32);
 552         else
 553                 sw = ALIGN((offset & 63) + width, 64);
 554
 555         if (sw == 0)
 556                 return 0;
 557
 558         return (sw - 32) >> 3;
 559 }
 560
 561 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
 562         [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
 563         [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
 564         [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
 565         [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
 566         [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
 567         [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
 568         [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
 569         [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
 570         [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
 571         [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
 572         [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
 573         [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
 574         [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
 575         [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
 576         [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
 577         [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
 578         [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
 579 };
 580
 581 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
 582         [ 0] = { 0x3000, 0x1800, 0x1800, },
 583         [ 1] = { 0xb000, 0x18d0, 0x2e60, },
 584         [ 2] = { 0xb000, 0x1990, 0x2ce0, },
 585         [ 3] = { 0xb020, 0x1a68, 0x2b40, },
 586         [ 4] = { 0xb040, 0x1b20, 0x29e0, },
 587         [ 5] = { 0xb060, 0x1bd8, 0x2880, },
 588         [ 6] = { 0xb080, 0x1c88, 0x3e60, },
 589         [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
 590         [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
 591         [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
 592         [10] = { 0xb100, 0x1eb8, 0x3620, },
 593         [11] = { 0xb100, 0x1f18, 0x34a0, },
 594         [12] = { 0xb100, 0x1f68, 0x3360, },
 595         [13] = { 0xb0e0, 0x1fa8, 0x3240, },
 596         [14] = { 0xb0c0, 0x1fe0, 0x3140, },
 597         [15] = { 0xb060, 0x1ff0, 0x30a0, },
 598         [16] = { 0x3000, 0x0800, 0x3000, },
 599 };
 600
 601 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 602 {
 603         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 604         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 605                     sizeof(uv_static_hcoeffs));
 606 }
 607
 608 static bool update_scaling_factors(struct intel_overlay *overlay,
 609                                    struct overlay_registers __iomem *regs,
 610                                    struct drm_intel_overlay_put_image *params)
 611 {
 612         /* fixed point with a 12 bit shift */
 613         u32 xscale, yscale, xscale_UV, yscale_UV;
 614 #define FP_SHIFT 12
 615 #define FRACT_MASK 0xfff
 616         bool scale_changed = false;
 617         int uv_hscale = uv_hsubsampling(params->flags);
 618         int uv_vscale = uv_vsubsampling(params->flags);
 619
 620         if (params->dst_width > 1)
 621                 xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
 622                         params->dst_width;
 623         else
 624                 xscale = 1 << FP_SHIFT;
 625
 626         if (params->dst_height > 1)
 627                 yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
 628                         params->dst_height;
 629         else
 630                 yscale = 1 << FP_SHIFT;
 631
 632         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 633         xscale_UV = xscale/uv_hscale;
 634         yscale_UV = yscale/uv_vscale;
 635         /* make the Y scale to UV scale ratio an exact multiply */
 636         xscale = xscale_UV * uv_hscale;
 637         yscale = yscale_UV * uv_vscale;
 638         /*} else {
 639           xscale_UV = 0;
 640           yscale_UV = 0;
 641           }*/
 642
 643         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 644                 scale_changed = true;
 645         overlay->old_xscale = xscale;
 646         overlay->old_yscale = yscale;
 647
 648         iowrite32(((yscale & FRACT_MASK) << 20) |
 649                   ((xscale >> FP_SHIFT)  << 16) |
 650                   ((xscale & FRACT_MASK) << 3),
 651                  &regs->YRGBSCALE);
 652
 653         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 654                   ((xscale_UV >> FP_SHIFT)  << 16) |
 655                   ((xscale_UV & FRACT_MASK) << 3),
 656                  &regs->UVSCALE);
 657
 658         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 659                    ((yscale_UV >> FP_SHIFT) << 0)),
 660                  &regs->UVSCALEV);
 661
 662         if (scale_changed)
 663                 update_polyphase_filter(regs);
 664
 665         return scale_changed;
 666 }
 667
 668 static void update_colorkey(struct intel_overlay *overlay,
 669                             struct overlay_registers __iomem *regs)
 670 {
 671         const struct intel_plane_state *state =
 672                 to_intel_plane_state(overlay->crtc->base.primary->state);
 673         u32 key = overlay->color_key;
 674         u32 format = 0;
 675         u32 flags = 0;
 676
 677         if (overlay->color_key_enabled)
 678                 flags |= DST_KEY_ENABLE;
 679
 680         if (state->uapi.visible)
 681                 format = state->hw.fb->format->format;
 682
 683         switch (format) {
 684         case DRM_FORMAT_C8:
 685                 key = 0;
 686                 flags |= CLK_RGB8I_MASK;
 687                 break;
 688         case DRM_FORMAT_XRGB1555:
 689                 key = RGB15_TO_COLORKEY(key);
 690                 flags |= CLK_RGB15_MASK;
 691                 break;
 692         case DRM_FORMAT_RGB565:
 693                 key = RGB16_TO_COLORKEY(key);
 694                 flags |= CLK_RGB16_MASK;
 695                 break;
 696         default:
 697                 flags |= CLK_RGB24_MASK;
 698                 break;
 699         }
 700
 701         iowrite32(key, &regs->DCLRKV);
 702         iowrite32(flags, &regs->DCLRKM);
 703 }
 704
 705 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
 706 {
 707         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 708
 709         if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 710                 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 711                 case I915_OVERLAY_YUV422:
 712                         cmd |= OCMD_YUV_422_PLANAR;
 713                         break;
 714                 case I915_OVERLAY_YUV420:
 715                         cmd |= OCMD_YUV_420_PLANAR;
 716                         break;
 717                 case I915_OVERLAY_YUV411:
 718                 case I915_OVERLAY_YUV410:
 719                         cmd |= OCMD_YUV_410_PLANAR;
 720                         break;
 721                 }
 722         } else { /* YUV packed */
 723                 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 724                 case I915_OVERLAY_YUV422:
 725                         cmd |= OCMD_YUV_422_PACKED;
 726                         break;
 727                 case I915_OVERLAY_YUV411:
 728                         cmd |= OCMD_YUV_411_PACKED;
 729                         break;
 730                 }
 731
 732                 switch (params->flags & I915_OVERLAY_SWAP_MASK) {
 733                 case I915_OVERLAY_NO_SWAP:
 734                         break;
 735                 case I915_OVERLAY_UV_SWAP:
 736                         cmd |= OCMD_UV_SWAP;
 737                         break;
 738                 case I915_OVERLAY_Y_SWAP:
 739                         cmd |= OCMD_Y_SWAP;
 740                         break;
 741                 case I915_OVERLAY_Y_AND_UV_SWAP:
 742                         cmd |= OCMD_Y_AND_UV_SWAP;
 743                         break;
 744                 }
 745         }
 746
 747         return cmd;
 748 }
 749
 750 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 751                                       struct drm_i915_gem_object *new_bo,
 752                                       struct drm_intel_overlay_put_image *params)
 753 {
 754         struct overlay_registers __iomem *regs = overlay->regs;
 755         struct drm_i915_private *dev_priv = overlay->i915;
 756         u32 swidth, swidthsw, sheight, ostride;
 757         enum pipe pipe = overlay->crtc->pipe;
 758         bool scale_changed = false;
 759         struct i915_vma *vma;
 760         int ret, tmp_width;
 761
 762         drm_WARN_ON(&dev_priv->drm,
 763                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 764
 765         ret = intel_overlay_release_old_vid(overlay);
 766         if (ret != 0)
 767                 return ret;
 768
 769         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
 770
 771         vma = i915_gem_object_pin_to_display_plane(new_bo,
 772                                                    0, NULL, PIN_MAPPABLE);
 773         if (IS_ERR(vma)) {
 774                 ret = PTR_ERR(vma);
 775                 goto out_pin_section;
 776         }
 777         i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
 778
 779         if (!overlay->active) {
 780                 u32 oconfig;
 781
 782                 oconfig = OCONF_CC_OUT_8BIT;
 783                 if (IS_GEN(dev_priv, 4))
 784                         oconfig |= OCONF_CSC_MODE_BT709;
 785                 oconfig |= pipe == 0 ?
 786                         OCONF_PIPE_A : OCONF_PIPE_B;
 787                 iowrite32(oconfig, &regs->OCONFIG);
 788
 789                 ret = intel_overlay_on(overlay);
 790                 if (ret != 0)
 791                         goto out_unpin;
 792         }
 793
 794         iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);
 795         iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);
 796
 797         if (params->flags & I915_OVERLAY_YUV_PACKED)
 798                 tmp_width = packed_width_bytes(params->flags,
 799                                                params->src_width);
 800         else
 801                 tmp_width = params->src_width;
 802
 803         swidth = params->src_width;
 804         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 805         sheight = params->src_height;
 806         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 807         ostride = params->stride_Y;
 808
 809         if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 810                 int uv_hscale = uv_hsubsampling(params->flags);
 811                 int uv_vscale = uv_vsubsampling(params->flags);
 812                 u32 tmp_U, tmp_V;
 813
 814                 swidth |= (params->src_width / uv_hscale) << 16;
 815                 sheight |= (params->src_height / uv_vscale) << 16;
 816
 817                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 818                                       params->src_width / uv_hscale);
 819                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 820                                       params->src_width / uv_hscale);
 821                 swidthsw |= max(tmp_U, tmp_V) << 16;
 822
 823                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 824                           &regs->OBUF_0U);
 825                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 826                           &regs->OBUF_0V);
 827
 828                 ostride |= params->stride_UV << 16;
 829         }
 830
 831         iowrite32(swidth, &regs->SWIDTH);
 832         iowrite32(swidthsw, &regs->SWIDTHSW);
 833         iowrite32(sheight, &regs->SHEIGHT);
 834         iowrite32(ostride, &regs->OSTRIDE);
 835
 836         scale_changed = update_scaling_factors(overlay, regs, params);
 837
 838         update_colorkey(overlay, regs);
 839
 840         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 841
 842         ret = intel_overlay_continue(overlay, vma, scale_changed);
 843         if (ret)
 844                 goto out_unpin;
 845
 846         return 0;
 847
 848 out_unpin:
 849         i915_gem_object_unpin_from_display_plane(vma);
 850 out_pin_section:
 851         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
 852
 853         return ret;
 854 }
 855
 856 int intel_overlay_switch_off(struct intel_overlay *overlay)
 857 {
 858         struct drm_i915_private *dev_priv = overlay->i915;
 859         int ret;
 860
 861         drm_WARN_ON(&dev_priv->drm,
 862                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 863
 864         ret = intel_overlay_recover_from_interrupt(overlay);
 865         if (ret != 0)
 866                 return ret;
 867
 868         if (!overlay->active)
 869                 return 0;
 870
 871         ret = intel_overlay_release_old_vid(overlay);
 872         if (ret != 0)
 873                 return ret;
 874
 875         iowrite32(0, &overlay->regs->OCMD);
 876
 877         return intel_overlay_off(overlay);
 878 }
 879
 880 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 881                                           struct intel_crtc *crtc)
 882 {
 883         if (!crtc->active)
 884                 return -EINVAL;
 885
 886         /* can't use the overlay with double wide pipe */
 887         if (crtc->config->double_wide)
 888                 return -EINVAL;
 889
 890         return 0;
 891 }
 892
 893 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 894 {
 895         struct drm_i915_private *dev_priv = overlay->i915;
 896         u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL);
 897         u32 ratio;
 898
 899         /* XXX: This is not the same logic as in the xorg driver, but more in
 900          * line with the intel documentation for the i965
 901          */
 902         if (INTEL_GEN(dev_priv) >= 4) {
 903                 /* on i965 use the PGM reg to read out the autoscaler values */
 904                 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 905         } else {
 906                 if (pfit_control & VERT_AUTO_SCALE)
 907                         ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
 908                 else
 909                         ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
 910                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 911         }
 912
 913         overlay->pfit_vscale_ratio = ratio;
 914 }
 915
 916 static int check_overlay_dst(struct intel_overlay *overlay,
 917                              struct drm_intel_overlay_put_image *rec)
 918 {
 919         const struct intel_crtc_state *pipe_config =
 920                 overlay->crtc->config;
 921
 922         if (rec->dst_x < pipe_config->pipe_src_w &&
 923             rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
 924             rec->dst_y < pipe_config->pipe_src_h &&
 925             rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
 926                 return 0;
 927         else
 928                 return -EINVAL;
 929 }
 930
 931 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
 932 {
 933         u32 tmp;
 934
 935         /* downscaling limit is 8.0 */
 936         tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
 937         if (tmp > 7)
 938                 return -EINVAL;
 939
 940         tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
 941         if (tmp > 7)
 942                 return -EINVAL;
 943
 944         return 0;
 945 }
 946
 947 static int check_overlay_src(struct drm_i915_private *dev_priv,
 948                              struct drm_intel_overlay_put_image *rec,
 949                              struct drm_i915_gem_object *new_bo)
 950 {
 951         int uv_hscale = uv_hsubsampling(rec->flags);
 952         int uv_vscale = uv_vsubsampling(rec->flags);
 953         u32 stride_mask;
 954         int depth;
 955         u32 tmp;
 956
 957         /* check src dimensions */
 958         if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
 959                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 960                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 961                         return -EINVAL;
 962         } else {
 963                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 964                     rec->src_width  > IMAGE_MAX_WIDTH)
 965                         return -EINVAL;
 966         }
 967
 968         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 969         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 970             rec->src_width  < N_HORIZ_Y_TAPS*4)
 971                 return -EINVAL;
 972
 973         /* check alignment constraints */
 974         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 975         case I915_OVERLAY_RGB:
 976                 /* not implemented */
 977                 return -EINVAL;
 978
 979         case I915_OVERLAY_YUV_PACKED:
 980                 if (uv_vscale != 1)
 981                         return -EINVAL;
 982
 983                 depth = packed_depth_bytes(rec->flags);
 984                 if (depth < 0)
 985                         return depth;
 986
 987                 /* ignore UV planes */
 988                 rec->stride_UV = 0;
 989                 rec->offset_U = 0;
 990                 rec->offset_V = 0;
 991                 /* check pixel alignment */
 992                 if (rec->offset_Y % depth)
 993                         return -EINVAL;
 994                 break;
 995
 996         case I915_OVERLAY_YUV_PLANAR:
 997                 if (uv_vscale < 0 || uv_hscale < 0)
 998                         return -EINVAL;
 999                 /* no offset restrictions for planar formats */
1000                 break;
1001
1002         default:
1003                 return -EINVAL;
1004         }
1005
1006         if (rec->src_width % uv_hscale)
1007                 return -EINVAL;
1008
1009         /* stride checking */
1010         if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1011                 stride_mask = 255;
1012         else
1013                 stride_mask = 63;
1014
1015         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1016                 return -EINVAL;
1017         if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512)
1018                 return -EINVAL;
1019
1020         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1021                 4096 : 8192;
1022         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1023                 return -EINVAL;
1024
1025         /* check buffer dimensions */
1026         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1027         case I915_OVERLAY_RGB:
1028         case I915_OVERLAY_YUV_PACKED:
1029                 /* always 4 Y values per depth pixels */
1030                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1031                         return -EINVAL;
1032
1033                 tmp = rec->stride_Y*rec->src_height;
1034                 if (rec->offset_Y + tmp > new_bo->base.size)
1035                         return -EINVAL;
1036                 break;
1037
1038         case I915_OVERLAY_YUV_PLANAR:
1039                 if (rec->src_width > rec->stride_Y)
1040                         return -EINVAL;
1041                 if (rec->src_width/uv_hscale > rec->stride_UV)
1042                         return -EINVAL;
1043
1044                 tmp = rec->stride_Y * rec->src_height;
1045                 if (rec->offset_Y + tmp > new_bo->base.size)
1046                         return -EINVAL;
1047
1048                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1049                 if (rec->offset_U + tmp > new_bo->base.size ||
1050                     rec->offset_V + tmp > new_bo->base.size)
1051                         return -EINVAL;
1052                 break;
1053         }
1054
1055         return 0;
1056 }
1057
1058 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1059                                   struct drm_file *file_priv)
1060 {
1061         struct drm_intel_overlay_put_image *params = data;
1062         struct drm_i915_private *dev_priv = to_i915(dev);
1063         struct intel_overlay *overlay;
1064         struct drm_crtc *drmmode_crtc;
1065         struct intel_crtc *crtc;
1066         struct drm_i915_gem_object *new_bo;
1067         int ret;
1068
1069         overlay = dev_priv->overlay;
1070         if (!overlay) {
1071                 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1072                 return -ENODEV;
1073         }
1074
1075         if (!(params->flags & I915_OVERLAY_ENABLE)) {
1076                 drm_modeset_lock_all(dev);
1077                 ret = intel_overlay_switch_off(overlay);
1078                 drm_modeset_unlock_all(dev);
1079
1080                 return ret;
1081         }
1082
1083         drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1084         if (!drmmode_crtc)
1085                 return -ENOENT;
1086         crtc = to_intel_crtc(drmmode_crtc);
1087
1088         new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1089         if (!new_bo)
1090                 return -ENOENT;
1091
1092         drm_modeset_lock_all(dev);
1093
1094         if (i915_gem_object_is_tiled(new_bo)) {
1095                 drm_dbg_kms(&dev_priv->drm,
1096                             "buffer used for overlay image can not be tiled\n");
1097                 ret = -EINVAL;
1098                 goto out_unlock;
1099         }
1100
1101         ret = intel_overlay_recover_from_interrupt(overlay);
1102         if (ret != 0)
1103                 goto out_unlock;
1104
1105         if (overlay->crtc != crtc) {
1106                 ret = intel_overlay_switch_off(overlay);
1107                 if (ret != 0)
1108                         goto out_unlock;
1109
1110                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1111                 if (ret != 0)
1112                         goto out_unlock;
1113
1114                 overlay->crtc = crtc;
1115                 crtc->overlay = overlay;
1116
1117                 /* line too wide, i.e. one-line-mode */
1118                 if (crtc->config->pipe_src_w > 1024 &&
1119                     crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1120                         overlay->pfit_active = true;
1121                         update_pfit_vscale_ratio(overlay);
1122                 } else
1123                         overlay->pfit_active = false;
1124         }
1125
1126         ret = check_overlay_dst(overlay, params);
1127         if (ret != 0)
1128                 goto out_unlock;
1129
1130         if (overlay->pfit_active) {
1131                 params->dst_y = (((u32)params->dst_y << 12) /
1132                                  overlay->pfit_vscale_ratio);
1133                 /* shifting right rounds downwards, so add 1 */
1134                 params->dst_height = (((u32)params->dst_height << 12) /
1135                                  overlay->pfit_vscale_ratio) + 1;
1136         }
1137
1138         if (params->src_scan_height > params->src_height ||
1139             params->src_scan_width > params->src_width) {
1140                 ret = -EINVAL;
1141                 goto out_unlock;
1142         }
1143
1144         ret = check_overlay_src(dev_priv, params, new_bo);
1145         if (ret != 0)
1146                 goto out_unlock;
1147
1148         /* Check scaling after src size to prevent a divide-by-zero. */
1149         ret = check_overlay_scaling(params);
1150         if (ret != 0)
1151                 goto out_unlock;
1152
1153         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1154         if (ret != 0)
1155                 goto out_unlock;
1156
1157         drm_modeset_unlock_all(dev);
1158         i915_gem_object_put(new_bo);
1159
1160         return 0;
1161
1162 out_unlock:
1163         drm_modeset_unlock_all(dev);
1164         i915_gem_object_put(new_bo);
1165
1166         return ret;
1167 }
1168
1169 static void update_reg_attrs(struct intel_overlay *overlay,
1170                              struct overlay_registers __iomem *regs)
1171 {
1172         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1173                   &regs->OCLRC0);
1174         iowrite32(overlay->saturation, &regs->OCLRC1);
1175 }
1176
1177 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1178 {
1179         int i;
1180
1181         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1182                 return false;
1183
1184         for (i = 0; i < 3; i++) {
1185                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1186                         return false;
1187         }
1188
1189         return true;
1190 }
1191
1192 static bool check_gamma5_errata(u32 gamma5)
1193 {
1194         int i;
1195
1196         for (i = 0; i < 3; i++) {
1197                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1198                         return false;
1199         }
1200
1201         return true;
1202 }
1203
1204 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1205 {
1206         if (!check_gamma_bounds(0, attrs->gamma0) ||
1207             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1208             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1209             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1210             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1211             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1212             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1213                 return -EINVAL;
1214
1215         if (!check_gamma5_errata(attrs->gamma5))
1216                 return -EINVAL;
1217
1218         return 0;
1219 }
1220
1221 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1222                               struct drm_file *file_priv)
1223 {
1224         struct drm_intel_overlay_attrs *attrs = data;
1225         struct drm_i915_private *dev_priv = to_i915(dev);
1226         struct intel_overlay *overlay;
1227         int ret;
1228
1229         overlay = dev_priv->overlay;
1230         if (!overlay) {
1231                 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1232                 return -ENODEV;
1233         }
1234
1235         drm_modeset_lock_all(dev);
1236
1237         ret = -EINVAL;
1238         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1239                 attrs->color_key  = overlay->color_key;
1240                 attrs->brightness = overlay->brightness;
1241                 attrs->contrast   = overlay->contrast;
1242                 attrs->saturation = overlay->saturation;
1243
1244                 if (!IS_GEN(dev_priv, 2)) {
1245                         attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
1246                         attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
1247                         attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
1248                         attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);
1249                         attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);
1250                         attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);
1251                 }
1252         } else {
1253                 if (attrs->brightness < -128 || attrs->brightness > 127)
1254                         goto out_unlock;
1255                 if (attrs->contrast > 255)
1256                         goto out_unlock;
1257                 if (attrs->saturation > 1023)
1258                         goto out_unlock;
1259
1260                 overlay->color_key  = attrs->color_key;
1261                 overlay->brightness = attrs->brightness;
1262                 overlay->contrast   = attrs->contrast;
1263                 overlay->saturation = attrs->saturation;
1264
1265                 update_reg_attrs(overlay, overlay->regs);
1266
1267                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1268                         if (IS_GEN(dev_priv, 2))
1269                                 goto out_unlock;
1270
1271                         if (overlay->active) {
1272                                 ret = -EBUSY;
1273                                 goto out_unlock;
1274                         }
1275
1276                         ret = check_gamma(attrs);
1277                         if (ret)
1278                                 goto out_unlock;
1279
1280                         intel_de_write(dev_priv, OGAMC0, attrs->gamma0);
1281                         intel_de_write(dev_priv, OGAMC1, attrs->gamma1);
1282                         intel_de_write(dev_priv, OGAMC2, attrs->gamma2);
1283                         intel_de_write(dev_priv, OGAMC3, attrs->gamma3);
1284                         intel_de_write(dev_priv, OGAMC4, attrs->gamma4);
1285                         intel_de_write(dev_priv, OGAMC5, attrs->gamma5);
1286                 }
1287         }
1288         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1289
1290         ret = 0;
1291 out_unlock:
1292         drm_modeset_unlock_all(dev);
1293
1294         return ret;
1295 }
1296
1297 static int get_registers(struct intel_overlay *overlay, bool use_phys)
1298 {
1299         struct drm_i915_private *i915 = overlay->i915;
1300         struct drm_i915_gem_object *obj;
1301         struct i915_vma *vma;
1302         int err;
1303
1304         obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
1305         if (IS_ERR(obj))
1306                 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1307         if (IS_ERR(obj))
1308                 return PTR_ERR(obj);
1309
1310         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1311         if (IS_ERR(vma)) {
1312                 err = PTR_ERR(vma);
1313                 goto err_put_bo;
1314         }
1315
1316         if (use_phys)
1317                 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1318         else
1319                 overlay->flip_addr = i915_ggtt_offset(vma);
1320         overlay->regs = i915_vma_pin_iomap(vma);
1321         i915_vma_unpin(vma);
1322
1323         if (IS_ERR(overlay->regs)) {
1324                 err = PTR_ERR(overlay->regs);
1325                 goto err_put_bo;
1326         }
1327
1328         overlay->reg_bo = obj;
1329         return 0;
1330
1331 err_put_bo:
1332         i915_gem_object_put(obj);
1333         return err;
1334 }
1335
1336 void intel_overlay_setup(struct drm_i915_private *dev_priv)
1337 {
1338         struct intel_overlay *overlay;
1339         struct intel_engine_cs *engine;
1340         int ret;
1341
1342         if (!HAS_OVERLAY(dev_priv))
1343                 return;
1344
1345         engine = dev_priv->engine[RCS0];
1346         if (!engine || !engine->kernel_context)
1347                 return;
1348
1349         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1350         if (!overlay)
1351                 return;
1352
1353         overlay->i915 = dev_priv;
1354         overlay->context = engine->kernel_context;
1355         GEM_BUG_ON(!overlay->context);
1356
1357         overlay->color_key = 0x0101fe;
1358         overlay->color_key_enabled = true;
1359         overlay->brightness = -19;
1360         overlay->contrast = 75;
1361         overlay->saturation = 146;
1362
1363         i915_active_init(&overlay->last_flip,
1364                          NULL, intel_overlay_last_flip_retire);
1365
1366         ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1367         if (ret)
1368                 goto out_free;
1369
1370         memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1371         update_polyphase_filter(overlay->regs);
1372         update_reg_attrs(overlay, overlay->regs);
1373
1374         dev_priv->overlay = overlay;
1375         drm_info(&dev_priv->drm, "Initialized overlay support.\n");
1376         return;
1377
1378 out_free:
1379         kfree(overlay);
1380 }
1381
1382 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1383 {
1384         struct intel_overlay *overlay;
1385
1386         overlay = fetch_and_zero(&dev_priv->overlay);
1387         if (!overlay)
1388                 return;
1389
1390         /*
1391          * The bo's should be free'd by the generic code already.
1392          * Furthermore modesetting teardown happens beforehand so the
1393          * hardware should be off already.
1394          */
1395         drm_WARN_ON(&dev_priv->drm, overlay->active);
1396
1397         i915_gem_object_put(overlay->reg_bo);
1398         i915_active_fini(&overlay->last_flip);
1399
1400         kfree(overlay);
1401 }
1402
1403 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1404
1405 struct intel_overlay_error_state {
1406         struct overlay_registers regs;
1407         unsigned long base;
1408         u32 dovsta;
1409         u32 isr;
1410 };
1411
1412 struct intel_overlay_error_state *
1413 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1414 {
1415         struct intel_overlay *overlay = dev_priv->overlay;
1416         struct intel_overlay_error_state *error;
1417
1418         if (!overlay || !overlay->active)
1419                 return NULL;
1420
1421         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1422         if (error == NULL)
1423                 return NULL;
1424
1425         error->dovsta = intel_de_read(dev_priv, DOVSTA);
1426         error->isr = intel_de_read(dev_priv, GEN2_ISR);
1427         error->base = overlay->flip_addr;
1428
1429         memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1430
1431         return error;
1432 }
1433
1434 void
1435 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1436                                 struct intel_overlay_error_state *error)
1437 {
1438         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1439                           error->dovsta, error->isr);
1440         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1441                           error->base);
1442
1443 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1444         P(OBUF_0Y);
1445         P(OBUF_1Y);
1446         P(OBUF_0U);
1447         P(OBUF_0V);
1448         P(OBUF_1U);
1449         P(OBUF_1V);
1450         P(OSTRIDE);
1451         P(YRGB_VPH);
1452         P(UV_VPH);
1453         P(HORZ_PH);
1454         P(INIT_PHS);
1455         P(DWINPOS);
1456         P(DWINSZ);
1457         P(SWIDTH);
1458         P(SWIDTHSW);
1459         P(SHEIGHT);
1460         P(YRGBSCALE);
1461         P(UVSCALE);
1462         P(OCLRC0);
1463         P(OCLRC1);
1464         P(DCLRKV);
1465         P(DCLRKM);
1466         P(SCLRKVH);
1467         P(SCLRKVL);
1468         P(SCLRKEN);
1469         P(OCONFIG);
1470         P(OCMD);
1471         P(OSTART_0Y);
1472         P(OSTART_1Y);
1473         P(OSTART_0U);
1474         P(OSTART_0V);
1475         P(OSTART_1U);
1476         P(OSTART_1V);
1477         P(OTILEOFF_0Y);
1478         P(OTILEOFF_1Y);
1479         P(OTILEOFF_0U);
1480         P(OTILEOFF_0V);
1481         P(OTILEOFF_1U);
1482         P(OTILEOFF_1V);
1483         P(FASTHSCALE);
1484         P(UVSCALEV);
1485 #undef P
1486 }
1487
1488 #endif