drivers/gpu/drm/i915/display/intel_modeset_setup.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  *
   5  * Read out the current hardware modeset state, and sanitize it to the current
   6  * state.
   7  */
   8
   9 #include <drm/drm_atomic_uapi.h>
  10 #include <drm/drm_atomic_state_helper.h>
  11
  12 #include "i915_drv.h"
  13 #include "i915_reg.h"
  14 #include "i9xx_wm.h"
  15 #include "intel_atomic.h"
  16 #include "intel_bw.h"
  17 #include "intel_color.h"
  18 #include "intel_crtc.h"
  19 #include "intel_crtc_state_dump.h"
  20 #include "intel_ddi.h"
  21 #include "intel_de.h"
  22 #include "intel_display.h"
  23 #include "intel_display_power.h"
  24 #include "intel_display_types.h"
  25 #include "intel_dmc.h"
  26 #include "intel_fifo_underrun.h"
  27 #include "intel_modeset_setup.h"
  28 #include "intel_pch_display.h"
  29 #include "intel_vblank.h"
  30 #include "intel_wm.h"
  31 #include "skl_watermark.h"
  32
  33 static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
  34                                               struct drm_modeset_acquire_ctx *ctx)
  35 {
  36         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
  37         struct intel_crtc_state *crtc_state =
  38                 to_intel_crtc_state(crtc->base.state);
  39         struct intel_plane *plane;
  40         struct drm_atomic_state *state;
  41         struct intel_crtc_state *temp_crtc_state;
  42         int ret;
  43
  44         if (!crtc_state->hw.active)
  45                 return;
  46
  47         for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
  48                 const struct intel_plane_state *plane_state =
  49                         to_intel_plane_state(plane->base.state);
  50
  51                 if (plane_state->uapi.visible)
  52                         intel_plane_disable_noatomic(crtc, plane);
  53         }
  54
  55         state = drm_atomic_state_alloc(&i915->drm);
  56         if (!state) {
  57                 drm_dbg_kms(&i915->drm,
  58                             "failed to disable [CRTC:%d:%s], out of memory",
  59                             crtc->base.base.id, crtc->base.name);
  60                 return;
  61         }
  62
  63         state->acquire_ctx = ctx;
  64         to_intel_atomic_state(state)->internal = true;
  65
  66         /* Everything's already locked, -EDEADLK can't happen. */
  67         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
  68         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
  69
  70         drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
  71
  72         i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
  73
  74         drm_atomic_state_put(state);
  75
  76         drm_dbg_kms(&i915->drm,
  77                     "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
  78                     crtc->base.base.id, crtc->base.name);
  79
  80         crtc->active = false;
  81         crtc->base.enabled = false;
  82
  83         if (crtc_state->shared_dpll)
  84                 intel_unreference_shared_dpll_crtc(crtc,
  85                                                    crtc_state->shared_dpll,
  86                                                    &crtc_state->shared_dpll->state);
  87 }
  88
  89 static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
  90 {
  91         struct intel_encoder *encoder;
  92         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
  93         struct intel_bw_state *bw_state =
  94                 to_intel_bw_state(i915->display.bw.obj.state);
  95         struct intel_cdclk_state *cdclk_state =
  96                 to_intel_cdclk_state(i915->display.cdclk.obj.state);
  97         struct intel_dbuf_state *dbuf_state =
  98                 to_intel_dbuf_state(i915->display.dbuf.obj.state);
  99         struct intel_crtc_state *crtc_state =
 100                 to_intel_crtc_state(crtc->base.state);
 101         enum pipe pipe = crtc->pipe;
 102
 103         __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 104         intel_crtc_free_hw_state(crtc_state);
 105         intel_crtc_state_reset(crtc_state, crtc);
 106
 107         for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder)
 108                 encoder->base.crtc = NULL;
 109
 110         intel_fbc_disable(crtc);
 111         intel_update_watermarks(i915);
 112
 113         intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains);
 114
 115         cdclk_state->min_cdclk[pipe] = 0;
 116         cdclk_state->min_voltage_level[pipe] = 0;
 117         cdclk_state->active_pipes &= ~BIT(pipe);
 118
 119         dbuf_state->active_pipes &= ~BIT(pipe);
 120
 121         bw_state->data_rate[pipe] = 0;
 122         bw_state->num_active_planes[pipe] = 0;
 123 }
 124
 125 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 126                                         struct drm_modeset_acquire_ctx *ctx)
 127 {
 128         intel_crtc_disable_noatomic_begin(crtc, ctx);
 129         intel_crtc_disable_noatomic_complete(crtc);
 130 }
 131
 132 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
 133 {
 134         struct intel_connector *connector;
 135         struct drm_connector_list_iter conn_iter;
 136
 137         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 138         for_each_intel_connector_iter(connector, &conn_iter) {
 139                 struct drm_connector_state *conn_state = connector->base.state;
 140                 struct intel_encoder *encoder =
 141                         to_intel_encoder(connector->base.encoder);
 142
 143                 if (conn_state->crtc)
 144                         drm_connector_put(&connector->base);
 145
 146                 if (encoder) {
 147                         struct intel_crtc *crtc =
 148                                 to_intel_crtc(encoder->base.crtc);
 149                         const struct intel_crtc_state *crtc_state =
 150                                 to_intel_crtc_state(crtc->base.state);
 151
 152                         conn_state->best_encoder = &encoder->base;
 153                         conn_state->crtc = &crtc->base;
 154                         conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
 155
 156                         drm_connector_get(&connector->base);
 157                 } else {
 158                         conn_state->best_encoder = NULL;
 159                         conn_state->crtc = NULL;
 160                 }
 161         }
 162         drm_connector_list_iter_end(&conn_iter);
 163 }
 164
 165 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
 166 {
 167         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 168                 return;
 169
 170         crtc_state->uapi.enable = crtc_state->hw.enable;
 171         crtc_state->uapi.active = crtc_state->hw.active;
 172         drm_WARN_ON(crtc_state->uapi.crtc->dev,
 173                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
 174
 175         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
 176         crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
 177
 178         /* assume 1:1 mapping */
 179         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
 180                                   crtc_state->pre_csc_lut);
 181         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
 182                                   crtc_state->post_csc_lut);
 183
 184         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
 185                                   crtc_state->hw.degamma_lut);
 186         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
 187                                   crtc_state->hw.gamma_lut);
 188         drm_property_replace_blob(&crtc_state->uapi.ctm,
 189                                   crtc_state->hw.ctm);
 190 }
 191
 192 static void
 193 intel_sanitize_plane_mapping(struct drm_i915_private *i915)
 194 {
 195         struct intel_crtc *crtc;
 196
 197         if (DISPLAY_VER(i915) >= 4)
 198                 return;
 199
 200         for_each_intel_crtc(&i915->drm, crtc) {
 201                 struct intel_plane *plane =
 202                         to_intel_plane(crtc->base.primary);
 203                 struct intel_crtc *plane_crtc;
 204                 enum pipe pipe;
 205
 206                 if (!plane->get_hw_state(plane, &pipe))
 207                         continue;
 208
 209                 if (pipe == crtc->pipe)
 210                         continue;
 211
 212                 drm_dbg_kms(&i915->drm,
 213                             "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
 214                             plane->base.base.id, plane->base.name);
 215
 216                 plane_crtc = intel_crtc_for_pipe(i915, pipe);
 217                 intel_plane_disable_noatomic(plane_crtc, plane);
 218         }
 219 }
 220
 221 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
 222 {
 223         struct drm_device *dev = crtc->base.dev;
 224         struct intel_encoder *encoder;
 225
 226         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 227                 return true;
 228
 229         return false;
 230 }
 231
 232 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
 233 {
 234         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 235         struct drm_connector_list_iter conn_iter;
 236         struct intel_connector *connector;
 237         struct intel_connector *found_connector = NULL;
 238
 239         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 240         for_each_intel_connector_iter(connector, &conn_iter) {
 241                 if (&encoder->base == connector->base.encoder) {
 242                         found_connector = connector;
 243                         break;
 244                 }
 245         }
 246         drm_connector_list_iter_end(&conn_iter);
 247
 248         return found_connector;
 249 }
 250
 251 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
 252 {
 253         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 254         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 255
 256         /*
 257          * We start out with underrun reporting disabled on active
 258          * pipes to avoid races.
 259          *
 260          * Also on gmch platforms we dont have any hardware bits to
 261          * disable the underrun reporting. Which means we need to start
 262          * out with underrun reporting disabled also on inactive pipes,
 263          * since otherwise we'll complain about the garbage we read when
 264          * e.g. coming up after runtime pm.
 265          *
 266          * No protection against concurrent access is required - at
 267          * worst a fifo underrun happens which also sets this to false.
 268          */
 269         intel_init_fifo_underrun_reporting(i915, crtc,
 270                                            !crtc_state->hw.active &&
 271                                            !HAS_GMCH(i915));
 272 }
 273
 274 static void intel_sanitize_crtc(struct intel_crtc *crtc,
 275                                 struct drm_modeset_acquire_ctx *ctx)
 276 {
 277         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 278         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
 279
 280         if (crtc_state->hw.active) {
 281                 struct intel_plane *plane;
 282
 283                 /* Disable everything but the primary plane */
 284                 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 285                         const struct intel_plane_state *plane_state =
 286                                 to_intel_plane_state(plane->base.state);
 287
 288                         if (plane_state->uapi.visible &&
 289                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
 290                                 intel_plane_disable_noatomic(crtc, plane);
 291                 }
 292
 293                 /* Disable any background color/etc. set by the BIOS */
 294                 intel_color_commit_noarm(crtc_state);
 295                 intel_color_commit_arm(crtc_state);
 296         }
 297
 298         /*
 299          * Adjust the state of the output pipe according to whether we have
 300          * active connectors/encoders.
 301          */
 302         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
 303             !intel_crtc_is_bigjoiner_slave(crtc_state))
 304                 intel_crtc_disable_noatomic(crtc, ctx);
 305 }
 306
 307 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
 308 {
 309         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 310
 311         /*
 312          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
 313          * the hardware when a high res displays plugged in. DPLL P
 314          * divider is zero, and the pipe timings are bonkers. We'll
 315          * try to disable everything in that case.
 316          *
 317          * FIXME would be nice to be able to sanitize this state
 318          * without several WARNs, but for now let's take the easy
 319          * road.
 320          */
 321         return IS_SANDYBRIDGE(i915) &&
 322                 crtc_state->hw.active &&
 323                 crtc_state->shared_dpll &&
 324                 crtc_state->port_clock == 0;
 325 }
 326
 327 static void intel_sanitize_encoder(struct intel_encoder *encoder)
 328 {
 329         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 330         struct intel_connector *connector;
 331         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 332         struct intel_crtc_state *crtc_state = crtc ?
 333                 to_intel_crtc_state(crtc->base.state) : NULL;
 334
 335         /*
 336          * We need to check both for a crtc link (meaning that the encoder is
 337          * active and trying to read from a pipe) and the pipe itself being
 338          * active.
 339          */
 340         bool has_active_crtc = crtc_state &&
 341                 crtc_state->hw.active;
 342
 343         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
 344                 drm_dbg_kms(&i915->drm,
 345                             "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
 346                             pipe_name(crtc->pipe));
 347                 has_active_crtc = false;
 348         }
 349
 350         connector = intel_encoder_find_connector(encoder);
 351         if (connector && !has_active_crtc) {
 352                 drm_dbg_kms(&i915->drm,
 353                             "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
 354                             encoder->base.base.id,
 355                             encoder->base.name);
 356
 357                 /*
 358                  * Connector is active, but has no active pipe. This is fallout
 359                  * from our resume register restoring. Disable the encoder
 360                  * manually again.
 361                  */
 362                 if (crtc_state) {
 363                         struct drm_encoder *best_encoder;
 364
 365                         drm_dbg_kms(&i915->drm,
 366                                     "[ENCODER:%d:%s] manually disabled\n",
 367                                     encoder->base.base.id,
 368                                     encoder->base.name);
 369
 370                         /* avoid oopsing in case the hooks consult best_encoder */
 371                         best_encoder = connector->base.state->best_encoder;
 372                         connector->base.state->best_encoder = &encoder->base;
 373
 374                         /* FIXME NULL atomic state passed! */
 375                         if (encoder->disable)
 376                                 encoder->disable(NULL, encoder, crtc_state,
 377                                                  connector->base.state);
 378                         if (encoder->post_disable)
 379                                 encoder->post_disable(NULL, encoder, crtc_state,
 380                                                       connector->base.state);
 381
 382                         connector->base.state->best_encoder = best_encoder;
 383                 }
 384                 encoder->base.crtc = NULL;
 385
 386                 /*
 387                  * Inconsistent output/port/pipe state happens presumably due to
 388                  * a bug in one of the get_hw_state functions. Or someplace else
 389                  * in our code, like the register restore mess on resume. Clamp
 390                  * things to off as a safer default.
 391                  */
 392                 connector->base.dpms = DRM_MODE_DPMS_OFF;
 393                 connector->base.encoder = NULL;
 394         }
 395
 396         /* notify opregion of the sanitized encoder state */
 397         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
 398
 399         if (HAS_DDI(i915))
 400                 intel_ddi_sanitize_encoder_pll_mapping(encoder);
 401 }
 402
 403 /* FIXME read out full plane state for all planes */
 404 static void readout_plane_state(struct drm_i915_private *i915)
 405 {
 406         struct intel_plane *plane;
 407         struct intel_crtc *crtc;
 408
 409         for_each_intel_plane(&i915->drm, plane) {
 410                 struct intel_plane_state *plane_state =
 411                         to_intel_plane_state(plane->base.state);
 412                 struct intel_crtc_state *crtc_state;
 413                 enum pipe pipe = PIPE_A;
 414                 bool visible;
 415
 416                 visible = plane->get_hw_state(plane, &pipe);
 417
 418                 crtc = intel_crtc_for_pipe(i915, pipe);
 419                 crtc_state = to_intel_crtc_state(crtc->base.state);
 420
 421                 intel_set_plane_visible(crtc_state, plane_state, visible);
 422
 423                 drm_dbg_kms(&i915->drm,
 424                             "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
 425                             plane->base.base.id, plane->base.name,
 426                             str_enabled_disabled(visible), pipe_name(pipe));
 427         }
 428
 429         for_each_intel_crtc(&i915->drm, crtc) {
 430                 struct intel_crtc_state *crtc_state =
 431                         to_intel_crtc_state(crtc->base.state);
 432
 433                 intel_plane_fixup_bitmasks(crtc_state);
 434         }
 435 }
 436
 437 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
 438 {
 439         struct intel_cdclk_state *cdclk_state =
 440                 to_intel_cdclk_state(i915->display.cdclk.obj.state);
 441         struct intel_dbuf_state *dbuf_state =
 442                 to_intel_dbuf_state(i915->display.dbuf.obj.state);
 443         enum pipe pipe;
 444         struct intel_crtc *crtc;
 445         struct intel_encoder *encoder;
 446         struct intel_connector *connector;
 447         struct drm_connector_list_iter conn_iter;
 448         u8 active_pipes = 0;
 449
 450         for_each_intel_crtc(&i915->drm, crtc) {
 451                 struct intel_crtc_state *crtc_state =
 452                         to_intel_crtc_state(crtc->base.state);
 453
 454                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 455                 intel_crtc_free_hw_state(crtc_state);
 456                 intel_crtc_state_reset(crtc_state, crtc);
 457
 458                 intel_crtc_get_pipe_config(crtc_state);
 459
 460                 crtc_state->hw.enable = crtc_state->hw.active;
 461
 462                 crtc->base.enabled = crtc_state->hw.enable;
 463                 crtc->active = crtc_state->hw.active;
 464
 465                 if (crtc_state->hw.active)
 466                         active_pipes |= BIT(crtc->pipe);
 467
 468                 drm_dbg_kms(&i915->drm,
 469                             "[CRTC:%d:%s] hw state readout: %s\n",
 470                             crtc->base.base.id, crtc->base.name,
 471                             str_enabled_disabled(crtc_state->hw.active));
 472         }
 473
 474         cdclk_state->active_pipes = active_pipes;
 475         dbuf_state->active_pipes = active_pipes;
 476
 477         readout_plane_state(i915);
 478
 479         for_each_intel_encoder(&i915->drm, encoder) {
 480                 struct intel_crtc_state *crtc_state = NULL;
 481
 482                 pipe = 0;
 483
 484                 if (encoder->get_hw_state(encoder, &pipe)) {
 485                         crtc = intel_crtc_for_pipe(i915, pipe);
 486                         crtc_state = to_intel_crtc_state(crtc->base.state);
 487
 488                         encoder->base.crtc = &crtc->base;
 489                         intel_encoder_get_config(encoder, crtc_state);
 490
 491                         /* read out to slave crtc as well for bigjoiner */
 492                         if (crtc_state->bigjoiner_pipes) {
 493                                 struct intel_crtc *slave_crtc;
 494
 495                                 /* encoder should read be linked to bigjoiner master */
 496                                 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
 497
 498                                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
 499                                                                  intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
 500                                         struct intel_crtc_state *slave_crtc_state;
 501
 502                                         slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
 503                                         intel_encoder_get_config(encoder, slave_crtc_state);
 504                                 }
 505                         }
 506                 } else {
 507                         encoder->base.crtc = NULL;
 508                 }
 509
 510                 if (encoder->sync_state)
 511                         encoder->sync_state(encoder, crtc_state);
 512
 513                 drm_dbg_kms(&i915->drm,
 514                             "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
 515                             encoder->base.base.id, encoder->base.name,
 516                             str_enabled_disabled(encoder->base.crtc),
 517                             pipe_name(pipe));
 518         }
 519
 520         intel_dpll_readout_hw_state(i915);
 521
 522         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 523         for_each_intel_connector_iter(connector, &conn_iter) {
 524                 if (connector->get_hw_state(connector)) {
 525                         struct intel_crtc_state *crtc_state;
 526                         struct intel_crtc *crtc;
 527
 528                         connector->base.dpms = DRM_MODE_DPMS_ON;
 529
 530                         encoder = intel_attached_encoder(connector);
 531                         connector->base.encoder = &encoder->base;
 532
 533                         crtc = to_intel_crtc(encoder->base.crtc);
 534                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
 535
 536                         if (crtc_state && crtc_state->hw.active) {
 537                                 /*
 538                                  * This has to be done during hardware readout
 539                                  * because anything calling .crtc_disable may
 540                                  * rely on the connector_mask being accurate.
 541                                  */
 542                                 crtc_state->uapi.connector_mask |=
 543                                         drm_connector_mask(&connector->base);
 544                                 crtc_state->uapi.encoder_mask |=
 545                                         drm_encoder_mask(&encoder->base);
 546                         }
 547                 } else {
 548                         connector->base.dpms = DRM_MODE_DPMS_OFF;
 549                         connector->base.encoder = NULL;
 550                 }
 551                 drm_dbg_kms(&i915->drm,
 552                             "[CONNECTOR:%d:%s] hw state readout: %s\n",
 553                             connector->base.base.id, connector->base.name,
 554                             str_enabled_disabled(connector->base.encoder));
 555         }
 556         drm_connector_list_iter_end(&conn_iter);
 557
 558         for_each_intel_crtc(&i915->drm, crtc) {
 559                 struct intel_bw_state *bw_state =
 560                         to_intel_bw_state(i915->display.bw.obj.state);
 561                 struct intel_crtc_state *crtc_state =
 562                         to_intel_crtc_state(crtc->base.state);
 563                 struct intel_plane *plane;
 564                 int min_cdclk = 0;
 565
 566                 if (crtc_state->hw.active) {
 567                         /*
 568                          * The initial mode needs to be set in order to keep
 569                          * the atomic core happy. It wants a valid mode if the
 570                          * crtc's enabled, so we do the above call.
 571                          *
 572                          * But we don't set all the derived state fully, hence
 573                          * set a flag to indicate that a full recalculation is
 574                          * needed on the next commit.
 575                          */
 576                         crtc_state->inherited = true;
 577
 578                         intel_crtc_update_active_timings(crtc_state,
 579                                                          crtc_state->vrr.enable);
 580
 581                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
 582                 }
 583
 584                 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 585                         const struct intel_plane_state *plane_state =
 586                                 to_intel_plane_state(plane->base.state);
 587
 588                         /*
 589                          * FIXME don't have the fb yet, so can't
 590                          * use intel_plane_data_rate() :(
 591                          */
 592                         if (plane_state->uapi.visible)
 593                                 crtc_state->data_rate[plane->id] =
 594                                         4 * crtc_state->pixel_rate;
 595                         /*
 596                          * FIXME don't have the fb yet, so can't
 597                          * use plane->min_cdclk() :(
 598                          */
 599                         if (plane_state->uapi.visible && plane->min_cdclk) {
 600                                 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
 601                                         crtc_state->min_cdclk[plane->id] =
 602                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
 603                                 else
 604                                         crtc_state->min_cdclk[plane->id] =
 605                                                 crtc_state->pixel_rate;
 606                         }
 607                         drm_dbg_kms(&i915->drm,
 608                                     "[PLANE:%d:%s] min_cdclk %d kHz\n",
 609                                     plane->base.base.id, plane->base.name,
 610                                     crtc_state->min_cdclk[plane->id]);
 611                 }
 612
 613                 if (crtc_state->hw.active) {
 614                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
 615                         if (drm_WARN_ON(&i915->drm, min_cdclk < 0))
 616                                 min_cdclk = 0;
 617                 }
 618
 619                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
 620                 cdclk_state->min_voltage_level[crtc->pipe] =
 621                         crtc_state->min_voltage_level;
 622
 623                 intel_bw_crtc_update(bw_state, crtc_state);
 624         }
 625 }
 626
 627 static void
 628 get_encoder_power_domains(struct drm_i915_private *i915)
 629 {
 630         struct intel_encoder *encoder;
 631
 632         for_each_intel_encoder(&i915->drm, encoder) {
 633                 struct intel_crtc_state *crtc_state;
 634
 635                 if (!encoder->get_power_domains)
 636                         continue;
 637
 638                 /*
 639                  * MST-primary and inactive encoders don't have a crtc state
 640                  * and neither of these require any power domain references.
 641                  */
 642                 if (!encoder->base.crtc)
 643                         continue;
 644
 645                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
 646                 encoder->get_power_domains(encoder, crtc_state);
 647         }
 648 }
 649
 650 static void intel_early_display_was(struct drm_i915_private *i915)
 651 {
 652         /*
 653          * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
 654          * Also known as Wa_14010480278.
 655          */
 656         if (IS_DISPLAY_VER(i915, 10, 12))
 657                 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);
 658
 659         /*
 660          * WaRsPkgCStateDisplayPMReq:hsw
 661          * System hang if this isn't done before disabling all planes!
 662          */
 663         if (IS_HASWELL(i915))
 664                 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);
 665
 666         if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
 667                 /* Display WA #1142:kbl,cfl,cml */
 668                 intel_de_rmw(i915, CHICKEN_PAR1_1,
 669                              KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
 670                 intel_de_rmw(i915, CHICKEN_MISC_2,
 671                              KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
 672                              KBL_ARB_FILL_SPARE_14);
 673         }
 674 }
 675
 676 void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
 677                                   struct drm_modeset_acquire_ctx *ctx)
 678 {
 679         struct intel_encoder *encoder;
 680         struct intel_crtc *crtc;
 681         intel_wakeref_t wakeref;
 682
 683         wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
 684
 685         intel_early_display_was(i915);
 686         intel_modeset_readout_hw_state(i915);
 687
 688         /* HW state is read out, now we need to sanitize this mess. */
 689         get_encoder_power_domains(i915);
 690
 691         intel_pch_sanitize(i915);
 692
 693         /*
 694          * intel_sanitize_plane_mapping() may need to do vblank
 695          * waits, so we need vblank interrupts restored beforehand.
 696          */
 697         for_each_intel_crtc(&i915->drm, crtc) {
 698                 struct intel_crtc_state *crtc_state =
 699                         to_intel_crtc_state(crtc->base.state);
 700
 701                 intel_sanitize_fifo_underrun_reporting(crtc_state);
 702
 703                 drm_crtc_vblank_reset(&crtc->base);
 704
 705                 if (crtc_state->hw.active) {
 706                         intel_dmc_enable_pipe(i915, crtc->pipe);
 707                         intel_crtc_vblank_on(crtc_state);
 708                 }
 709         }
 710
 711         intel_fbc_sanitize(i915);
 712
 713         intel_sanitize_plane_mapping(i915);
 714
 715         for_each_intel_encoder(&i915->drm, encoder)
 716                 intel_sanitize_encoder(encoder);
 717
 718         /*
 719          * Sanitizing CRTCs needs their connector atomic state to be
 720          * up-to-date, so ensure that already here.
 721          */
 722         intel_modeset_update_connector_atomic_state(i915);
 723
 724         for_each_intel_crtc(&i915->drm, crtc) {
 725                 struct intel_crtc_state *crtc_state =
 726                         to_intel_crtc_state(crtc->base.state);
 727
 728                 intel_sanitize_crtc(crtc, ctx);
 729                 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
 730         }
 731
 732         intel_dpll_sanitize_state(i915);
 733
 734         intel_wm_get_hw_state(i915);
 735
 736         for_each_intel_crtc(&i915->drm, crtc) {
 737                 struct intel_crtc_state *crtc_state =
 738                         to_intel_crtc_state(crtc->base.state);
 739                 struct intel_power_domain_mask put_domains;
 740
 741                 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
 742                 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
 743                         intel_modeset_put_crtc_power_domains(crtc, &put_domains);
 744         }
 745
 746         intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
 747
 748         intel_power_domains_sanitize_state(i915);
 749 }