drivers/gpu/drm/i915/display/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Dave Airlie <airlied@linux.ie>
  27  *      Jesse Barnes <jesse.barnes@intel.com>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/acpi.h>
  32 #include <linux/dmi.h>
  33 #include <linux/i2c.h>
  34 #include <linux/slab.h>
  35 #include <linux/vga_switcheroo.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_edid.h>
  40
  41 #include "i915_drv.h"
  42 #include "intel_atomic.h"
  43 #include "intel_connector.h"
  44 #include "intel_display_types.h"
  45 #include "intel_gmbus.h"
  46 #include "intel_lvds.h"
  47 #include "intel_panel.h"
  48
  49 /* Private structure for the integrated LVDS support */
  50 struct intel_lvds_pps {
  51         /* 100us units */
  52         int t1_t2;
  53         int t3;
  54         int t4;
  55         int t5;
  56         int tx;
  57
  58         int divider;
  59
  60         int port;
  61         bool powerdown_on_reset;
  62 };
  63
  64 struct intel_lvds_encoder {
  65         struct intel_encoder base;
  66
  67         bool is_dual_link;
  68         i915_reg_t reg;
  69         u32 a3_power;
  70
  71         struct intel_lvds_pps init_pps;
  72         u32 init_lvds_val;
  73
  74         struct intel_connector *attached_connector;
  75 };
  76
  77 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  78 {
  79         return container_of(encoder, struct intel_lvds_encoder, base.base);
  80 }
  81
  82 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
  83                              i915_reg_t lvds_reg, enum pipe *pipe)
  84 {
  85         u32 val;
  86
  87         val = intel_de_read(dev_priv, lvds_reg);
  88
  89         /* asserts want to know the pipe even if the port is disabled */
  90         if (HAS_PCH_CPT(dev_priv))
  91                 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
  92         else
  93                 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
  94
  95         return val & LVDS_PORT_EN;
  96 }
  97
  98 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  99                                     enum pipe *pipe)
 100 {
 101         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 102         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 103         intel_wakeref_t wakeref;
 104         bool ret;
 105
 106         wakeref = intel_display_power_get_if_enabled(dev_priv,
 107                                                      encoder->power_domain);
 108         if (!wakeref)
 109                 return false;
 110
 111         ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
 112
 113         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 114
 115         return ret;
 116 }
 117
 118 static void intel_lvds_get_config(struct intel_encoder *encoder,
 119                                   struct intel_crtc_state *pipe_config)
 120 {
 121         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 122         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 123         u32 tmp, flags = 0;
 124
 125         pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 126
 127         tmp = intel_de_read(dev_priv, lvds_encoder->reg);
 128         if (tmp & LVDS_HSYNC_POLARITY)
 129                 flags |= DRM_MODE_FLAG_NHSYNC;
 130         else
 131                 flags |= DRM_MODE_FLAG_PHSYNC;
 132         if (tmp & LVDS_VSYNC_POLARITY)
 133                 flags |= DRM_MODE_FLAG_NVSYNC;
 134         else
 135                 flags |= DRM_MODE_FLAG_PVSYNC;
 136
 137         pipe_config->hw.adjusted_mode.flags |= flags;
 138
 139         if (INTEL_GEN(dev_priv) < 5)
 140                 pipe_config->gmch_pfit.lvds_border_bits =
 141                         tmp & LVDS_BORDER_ENABLE;
 142
 143         /* gen2/3 store dither state in pfit control, needs to match */
 144         if (INTEL_GEN(dev_priv) < 4) {
 145                 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
 146
 147                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 148         }
 149
 150         pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
 151 }
 152
 153 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 154                                         struct intel_lvds_pps *pps)
 155 {
 156         u32 val;
 157
 158         pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET;
 159
 160         val = intel_de_read(dev_priv, PP_ON_DELAYS(0));
 161         pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
 162         pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
 163         pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
 164
 165         val = intel_de_read(dev_priv, PP_OFF_DELAYS(0));
 166         pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
 167         pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
 168
 169         val = intel_de_read(dev_priv, PP_DIVISOR(0));
 170         pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
 171         val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
 172         /*
 173          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 174          * too short power-cycle delay due to the asynchronous programming of
 175          * the register.
 176          */
 177         if (val)
 178                 val--;
 179         /* Convert from 100ms to 100us units */
 180         pps->t4 = val * 1000;
 181
 182         if (INTEL_GEN(dev_priv) <= 4 &&
 183             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 184                 drm_dbg_kms(&dev_priv->drm,
 185                             "Panel power timings uninitialized, "
 186                             "setting defaults\n");
 187                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 188                 pps->t1_t2 = 40 * 10;
 189                 pps->t5 = 200 * 10;
 190                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 191                 pps->t3 = 35 * 10;
 192                 pps->tx = 200 * 10;
 193         }
 194
 195         drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 196                 "divider %d port %d powerdown_on_reset %d\n",
 197                 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 198                 pps->divider, pps->port, pps->powerdown_on_reset);
 199 }
 200
 201 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 202                                    struct intel_lvds_pps *pps)
 203 {
 204         u32 val;
 205
 206         val = intel_de_read(dev_priv, PP_CONTROL(0));
 207         drm_WARN_ON(&dev_priv->drm,
 208                     (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 209         if (pps->powerdown_on_reset)
 210                 val |= PANEL_POWER_RESET;
 211         intel_de_write(dev_priv, PP_CONTROL(0), val);
 212
 213         intel_de_write(dev_priv, PP_ON_DELAYS(0),
 214                        REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
 215
 216         intel_de_write(dev_priv, PP_OFF_DELAYS(0),
 217                        REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
 218
 219         intel_de_write(dev_priv, PP_DIVISOR(0),
 220                        REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1));
 221 }
 222
 223 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 224                                   const struct intel_crtc_state *pipe_config,
 225                                   const struct drm_connector_state *conn_state)
 226 {
 227         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 228         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 229         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 230         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 231         enum pipe pipe = crtc->pipe;
 232         u32 temp;
 233
 234         if (HAS_PCH_SPLIT(dev_priv)) {
 235                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 236                 assert_shared_dpll_disabled(dev_priv,
 237                                             pipe_config->shared_dpll);
 238         } else {
 239                 assert_pll_disabled(dev_priv, pipe);
 240         }
 241
 242         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 243
 244         temp = lvds_encoder->init_lvds_val;
 245         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 246
 247         if (HAS_PCH_CPT(dev_priv)) {
 248                 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
 249                 temp |= LVDS_PIPE_SEL_CPT(pipe);
 250         } else {
 251                 temp &= ~LVDS_PIPE_SEL_MASK;
 252                 temp |= LVDS_PIPE_SEL(pipe);
 253         }
 254
 255         /* set the corresponsding LVDS_BORDER bit */
 256         temp &= ~LVDS_BORDER_ENABLE;
 257         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 258
 259         /*
 260          * Set the B0-B3 data pairs corresponding to whether we're going to
 261          * set the DPLLs for dual-channel mode or not.
 262          */
 263         if (lvds_encoder->is_dual_link)
 264                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 265         else
 266                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 267
 268         /*
 269          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 270          * appropriately here, but we need to look more thoroughly into how
 271          * panels behave in the two modes. For now, let's just maintain the
 272          * value we got from the BIOS.
 273          */
 274         temp &= ~LVDS_A3_POWER_MASK;
 275         temp |= lvds_encoder->a3_power;
 276
 277         /*
 278          * Set the dithering flag on LVDS as needed, note that there is no
 279          * special lvds dither control bit on pch-split platforms, dithering is
 280          * only controlled through the PIPECONF reg.
 281          */
 282         if (IS_GEN(dev_priv, 4)) {
 283                 /*
 284                  * Bspec wording suggests that LVDS port dithering only exists
 285                  * for 18bpp panels.
 286                  */
 287                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 288                         temp |= LVDS_ENABLE_DITHER;
 289                 else
 290                         temp &= ~LVDS_ENABLE_DITHER;
 291         }
 292         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 293         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 294                 temp |= LVDS_HSYNC_POLARITY;
 295         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 296                 temp |= LVDS_VSYNC_POLARITY;
 297
 298         intel_de_write(dev_priv, lvds_encoder->reg, temp);
 299 }
 300
 301 /*
 302  * Sets the power state for the panel.
 303  */
 304 static void intel_enable_lvds(struct intel_encoder *encoder,
 305                               const struct intel_crtc_state *pipe_config,
 306                               const struct drm_connector_state *conn_state)
 307 {
 308         struct drm_device *dev = encoder->base.dev;
 309         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 310         struct drm_i915_private *dev_priv = to_i915(dev);
 311
 312         intel_de_write(dev_priv, lvds_encoder->reg,
 313                        intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN);
 314
 315         intel_de_write(dev_priv, PP_CONTROL(0),
 316                        intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON);
 317         intel_de_posting_read(dev_priv, lvds_encoder->reg);
 318
 319         if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
 320                 drm_err(&dev_priv->drm,
 321                         "timed out waiting for panel to power on\n");
 322
 323         intel_panel_enable_backlight(pipe_config, conn_state);
 324 }
 325
 326 static void intel_disable_lvds(struct intel_encoder *encoder,
 327                                const struct intel_crtc_state *old_crtc_state,
 328                                const struct drm_connector_state *old_conn_state)
 329 {
 330         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 331         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 332
 333         intel_de_write(dev_priv, PP_CONTROL(0),
 334                        intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON);
 335         if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
 336                 drm_err(&dev_priv->drm,
 337                         "timed out waiting for panel to power off\n");
 338
 339         intel_de_write(dev_priv, lvds_encoder->reg,
 340                        intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN);
 341         intel_de_posting_read(dev_priv, lvds_encoder->reg);
 342 }
 343
 344 static void gmch_disable_lvds(struct intel_encoder *encoder,
 345                               const struct intel_crtc_state *old_crtc_state,
 346                               const struct drm_connector_state *old_conn_state)
 347
 348 {
 349         intel_panel_disable_backlight(old_conn_state);
 350
 351         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 352 }
 353
 354 static void pch_disable_lvds(struct intel_encoder *encoder,
 355                              const struct intel_crtc_state *old_crtc_state,
 356                              const struct drm_connector_state *old_conn_state)
 357 {
 358         intel_panel_disable_backlight(old_conn_state);
 359 }
 360
 361 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 362                                   const struct intel_crtc_state *old_crtc_state,
 363                                   const struct drm_connector_state *old_conn_state)
 364 {
 365         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 366 }
 367
 368 static enum drm_mode_status
 369 intel_lvds_mode_valid(struct drm_connector *connector,
 370                       struct drm_display_mode *mode)
 371 {
 372         struct intel_connector *intel_connector = to_intel_connector(connector);
 373         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 374         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 375
 376         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 377                 return MODE_NO_DBLESCAN;
 378         if (mode->hdisplay > fixed_mode->hdisplay)
 379                 return MODE_PANEL;
 380         if (mode->vdisplay > fixed_mode->vdisplay)
 381                 return MODE_PANEL;
 382         if (fixed_mode->clock > max_pixclk)
 383                 return MODE_CLOCK_HIGH;
 384
 385         return MODE_OK;
 386 }
 387
 388 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 389                                      struct intel_crtc_state *pipe_config,
 390                                      struct drm_connector_state *conn_state)
 391 {
 392         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 393         struct intel_lvds_encoder *lvds_encoder =
 394                 to_lvds_encoder(&intel_encoder->base);
 395         struct intel_connector *intel_connector =
 396                 lvds_encoder->attached_connector;
 397         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 398         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 399         unsigned int lvds_bpp;
 400
 401         /* Should never happen!! */
 402         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 403                 drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n");
 404                 return -EINVAL;
 405         }
 406
 407         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 408                 lvds_bpp = 8*3;
 409         else
 410                 lvds_bpp = 6*3;
 411
 412         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 413                 drm_dbg_kms(&dev_priv->drm,
 414                             "forcing display bpp (was %d) to LVDS (%d)\n",
 415                             pipe_config->pipe_bpp, lvds_bpp);
 416                 pipe_config->pipe_bpp = lvds_bpp;
 417         }
 418
 419         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 420
 421         /*
 422          * We have timings from the BIOS for the panel, put them in
 423          * to the adjusted mode.  The CRTC will be set up for this mode,
 424          * with the panel scaling set up to source from the H/VDisplay
 425          * of the original mode.
 426          */
 427         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 428                                adjusted_mode);
 429
 430         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 431                 return -EINVAL;
 432
 433         if (HAS_PCH_SPLIT(dev_priv)) {
 434                 pipe_config->has_pch_encoder = true;
 435
 436                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 437                                         conn_state->scaling_mode);
 438         } else {
 439                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 440                                          conn_state->scaling_mode);
 441
 442         }
 443
 444         /*
 445          * XXX: It would be nice to support lower refresh rates on the
 446          * panels to reduce power consumption, and perhaps match the
 447          * user's requested refresh rate.
 448          */
 449
 450         return 0;
 451 }
 452
 453 static enum drm_connector_status
 454 intel_lvds_detect(struct drm_connector *connector, bool force)
 455 {
 456         return connector_status_connected;
 457 }
 458
 459 /*
 460  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 461  */
 462 static int intel_lvds_get_modes(struct drm_connector *connector)
 463 {
 464         struct intel_connector *intel_connector = to_intel_connector(connector);
 465         struct drm_device *dev = connector->dev;
 466         struct drm_display_mode *mode;
 467
 468         /* use cached edid if we have one */
 469         if (!IS_ERR_OR_NULL(intel_connector->edid))
 470                 return drm_add_edid_modes(connector, intel_connector->edid);
 471
 472         mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode);
 473         if (mode == NULL)
 474                 return 0;
 475
 476         drm_mode_probed_add(connector, mode);
 477         return 1;
 478 }
 479
 480 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 481         .get_modes = intel_lvds_get_modes,
 482         .mode_valid = intel_lvds_mode_valid,
 483         .atomic_check = intel_digital_connector_atomic_check,
 484 };
 485
 486 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 487         .detect = intel_lvds_detect,
 488         .fill_modes = drm_helper_probe_single_connector_modes,
 489         .atomic_get_property = intel_digital_connector_atomic_get_property,
 490         .atomic_set_property = intel_digital_connector_atomic_set_property,
 491         .late_register = intel_connector_register,
 492         .early_unregister = intel_connector_unregister,
 493         .destroy = intel_connector_destroy,
 494         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 495         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 496 };
 497
 498 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 499         .destroy = intel_encoder_destroy,
 500 };
 501
 502 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 503 {
 504         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 505         return 1;
 506 }
 507
 508 /* These systems claim to have LVDS, but really don't */
 509 static const struct dmi_system_id intel_no_lvds[] = {
 510         {
 511                 .callback = intel_no_lvds_dmi_callback,
 512                 .ident = "Apple Mac Mini (Core series)",
 513                 .matches = {
 514                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 515                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 516                 },
 517         },
 518         {
 519                 .callback = intel_no_lvds_dmi_callback,
 520                 .ident = "Apple Mac Mini (Core 2 series)",
 521                 .matches = {
 522                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 523                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 524                 },
 525         },
 526         {
 527                 .callback = intel_no_lvds_dmi_callback,
 528                 .ident = "MSI IM-945GSE-A",
 529                 .matches = {
 530                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 531                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 532                 },
 533         },
 534         {
 535                 .callback = intel_no_lvds_dmi_callback,
 536                 .ident = "Dell Studio Hybrid",
 537                 .matches = {
 538                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 539                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 540                 },
 541         },
 542         {
 543                 .callback = intel_no_lvds_dmi_callback,
 544                 .ident = "Dell OptiPlex FX170",
 545                 .matches = {
 546                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 547                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 548                 },
 549         },
 550         {
 551                 .callback = intel_no_lvds_dmi_callback,
 552                 .ident = "AOpen Mini PC",
 553                 .matches = {
 554                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 555                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 556                 },
 557         },
 558         {
 559                 .callback = intel_no_lvds_dmi_callback,
 560                 .ident = "AOpen Mini PC MP915",
 561                 .matches = {
 562                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 563                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 564                 },
 565         },
 566         {
 567                 .callback = intel_no_lvds_dmi_callback,
 568                 .ident = "AOpen i915GMm-HFS",
 569                 .matches = {
 570                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 571                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 572                 },
 573         },
 574         {
 575                 .callback = intel_no_lvds_dmi_callback,
 576                 .ident = "AOpen i45GMx-I",
 577                 .matches = {
 578                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 579                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 580                 },
 581         },
 582         {
 583                 .callback = intel_no_lvds_dmi_callback,
 584                 .ident = "Aopen i945GTt-VFA",
 585                 .matches = {
 586                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 587                 },
 588         },
 589         {
 590                 .callback = intel_no_lvds_dmi_callback,
 591                 .ident = "Clientron U800",
 592                 .matches = {
 593                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 594                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 595                 },
 596         },
 597         {
 598                 .callback = intel_no_lvds_dmi_callback,
 599                 .ident = "Clientron E830",
 600                 .matches = {
 601                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 602                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 603                 },
 604         },
 605         {
 606                 .callback = intel_no_lvds_dmi_callback,
 607                 .ident = "Asus EeeBox PC EB1007",
 608                 .matches = {
 609                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 610                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 611                 },
 612         },
 613         {
 614                 .callback = intel_no_lvds_dmi_callback,
 615                 .ident = "Asus AT5NM10T-I",
 616                 .matches = {
 617                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 618                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 619                 },
 620         },
 621         {
 622                 .callback = intel_no_lvds_dmi_callback,
 623                 .ident = "Hewlett-Packard HP t5740",
 624                 .matches = {
 625                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 626                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 627                 },
 628         },
 629         {
 630                 .callback = intel_no_lvds_dmi_callback,
 631                 .ident = "Hewlett-Packard t5745",
 632                 .matches = {
 633                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 634                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 635                 },
 636         },
 637         {
 638                 .callback = intel_no_lvds_dmi_callback,
 639                 .ident = "Hewlett-Packard st5747",
 640                 .matches = {
 641                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 642                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 643                 },
 644         },
 645         {
 646                 .callback = intel_no_lvds_dmi_callback,
 647                 .ident = "MSI Wind Box DC500",
 648                 .matches = {
 649                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 650                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 651                 },
 652         },
 653         {
 654                 .callback = intel_no_lvds_dmi_callback,
 655                 .ident = "Gigabyte GA-D525TUD",
 656                 .matches = {
 657                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 658                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 659                 },
 660         },
 661         {
 662                 .callback = intel_no_lvds_dmi_callback,
 663                 .ident = "Supermicro X7SPA-H",
 664                 .matches = {
 665                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 666                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 667                 },
 668         },
 669         {
 670                 .callback = intel_no_lvds_dmi_callback,
 671                 .ident = "Fujitsu Esprimo Q900",
 672                 .matches = {
 673                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 674                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 675                 },
 676         },
 677         {
 678                 .callback = intel_no_lvds_dmi_callback,
 679                 .ident = "Intel D410PT",
 680                 .matches = {
 681                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 682                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 683                 },
 684         },
 685         {
 686                 .callback = intel_no_lvds_dmi_callback,
 687                 .ident = "Intel D425KT",
 688                 .matches = {
 689                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 690                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 691                 },
 692         },
 693         {
 694                 .callback = intel_no_lvds_dmi_callback,
 695                 .ident = "Intel D510MO",
 696                 .matches = {
 697                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 698                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 699                 },
 700         },
 701         {
 702                 .callback = intel_no_lvds_dmi_callback,
 703                 .ident = "Intel D525MW",
 704                 .matches = {
 705                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 706                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 707                 },
 708         },
 709         {
 710                 .callback = intel_no_lvds_dmi_callback,
 711                 .ident = "Radiant P845",
 712                 .matches = {
 713                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 714                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 715                 },
 716         },
 717
 718         { }     /* terminating entry */
 719 };
 720
 721 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 722 {
 723         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 724         return 1;
 725 }
 726
 727 static const struct dmi_system_id intel_dual_link_lvds[] = {
 728         {
 729                 .callback = intel_dual_link_lvds_callback,
 730                 .ident = "Apple MacBook Pro 15\" (2010)",
 731                 .matches = {
 732                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 733                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 734                 },
 735         },
 736         {
 737                 .callback = intel_dual_link_lvds_callback,
 738                 .ident = "Apple MacBook Pro 15\" (2011)",
 739                 .matches = {
 740                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 741                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 742                 },
 743         },
 744         {
 745                 .callback = intel_dual_link_lvds_callback,
 746                 .ident = "Apple MacBook Pro 15\" (2012)",
 747                 .matches = {
 748                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 749                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 750                 },
 751         },
 752         { }     /* terminating entry */
 753 };
 754
 755 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv)
 756 {
 757         struct intel_encoder *encoder;
 758
 759         for_each_intel_encoder(&dev_priv->drm, encoder) {
 760                 if (encoder->type == INTEL_OUTPUT_LVDS)
 761                         return encoder;
 762         }
 763
 764         return NULL;
 765 }
 766
 767 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv)
 768 {
 769         struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv);
 770
 771         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 772 }
 773
 774 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 775 {
 776         struct drm_device *dev = lvds_encoder->base.base.dev;
 777         unsigned int val;
 778         struct drm_i915_private *dev_priv = to_i915(dev);
 779
 780         /* use the module option value if specified */
 781         if (i915_modparams.lvds_channel_mode > 0)
 782                 return i915_modparams.lvds_channel_mode == 2;
 783
 784         /* single channel LVDS is limited to 112 MHz */
 785         if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999)
 786                 return true;
 787
 788         if (dmi_check_system(intel_dual_link_lvds))
 789                 return true;
 790
 791         /*
 792          * BIOS should set the proper LVDS register value at boot, but
 793          * in reality, it doesn't set the value when the lid is closed;
 794          * we need to check "the value to be set" in VBT when LVDS
 795          * register is uninitialized.
 796          */
 797         val = intel_de_read(dev_priv, lvds_encoder->reg);
 798         if (HAS_PCH_CPT(dev_priv))
 799                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
 800         else
 801                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 802         if (val == 0)
 803                 val = dev_priv->vbt.bios_lvds_val;
 804
 805         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 806 }
 807
 808 /**
 809  * intel_lvds_init - setup LVDS connectors on this device
 810  * @dev_priv: i915 device
 811  *
 812  * Create the connector, register the LVDS DDC bus, and try to figure out what
 813  * modes we can display on the LVDS panel (if present).
 814  */
 815 void intel_lvds_init(struct drm_i915_private *dev_priv)
 816 {
 817         struct drm_device *dev = &dev_priv->drm;
 818         struct intel_lvds_encoder *lvds_encoder;
 819         struct intel_encoder *intel_encoder;
 820         struct intel_connector *intel_connector;
 821         struct drm_connector *connector;
 822         struct drm_encoder *encoder;
 823         struct drm_display_mode *fixed_mode = NULL;
 824         struct drm_display_mode *downclock_mode = NULL;
 825         struct edid *edid;
 826         i915_reg_t lvds_reg;
 827         u32 lvds;
 828         u8 pin;
 829         u32 allowed_scalers;
 830
 831         /* Skip init on machines we know falsely report LVDS */
 832         if (dmi_check_system(intel_no_lvds)) {
 833                 drm_WARN(dev, !dev_priv->vbt.int_lvds_support,
 834                          "Useless DMI match. Internal LVDS support disabled by VBT\n");
 835                 return;
 836         }
 837
 838         if (!dev_priv->vbt.int_lvds_support) {
 839                 drm_dbg_kms(&dev_priv->drm,
 840                             "Internal LVDS support disabled by VBT\n");
 841                 return;
 842         }
 843
 844         if (HAS_PCH_SPLIT(dev_priv))
 845                 lvds_reg = PCH_LVDS;
 846         else
 847                 lvds_reg = LVDS;
 848
 849         lvds = intel_de_read(dev_priv, lvds_reg);
 850
 851         if (HAS_PCH_SPLIT(dev_priv)) {
 852                 if ((lvds & LVDS_DETECTED) == 0)
 853                         return;
 854         }
 855
 856         pin = GMBUS_PIN_PANEL;
 857         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 858                 if ((lvds & LVDS_PORT_EN) == 0) {
 859                         drm_dbg_kms(&dev_priv->drm,
 860                                     "LVDS is not present in VBT\n");
 861                         return;
 862                 }
 863                 drm_dbg_kms(&dev_priv->drm,
 864                             "LVDS is not present in VBT, but enabled anyway\n");
 865         }
 866
 867         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 868         if (!lvds_encoder)
 869                 return;
 870
 871         intel_connector = intel_connector_alloc();
 872         if (!intel_connector) {
 873                 kfree(lvds_encoder);
 874                 return;
 875         }
 876
 877         lvds_encoder->attached_connector = intel_connector;
 878
 879         intel_encoder = &lvds_encoder->base;
 880         encoder = &intel_encoder->base;
 881         connector = &intel_connector->base;
 882         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
 883                            DRM_MODE_CONNECTOR_LVDS);
 884
 885         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
 886                          DRM_MODE_ENCODER_LVDS, "LVDS");
 887
 888         intel_encoder->enable = intel_enable_lvds;
 889         intel_encoder->pre_enable = intel_pre_enable_lvds;
 890         intel_encoder->compute_config = intel_lvds_compute_config;
 891         if (HAS_PCH_SPLIT(dev_priv)) {
 892                 intel_encoder->disable = pch_disable_lvds;
 893                 intel_encoder->post_disable = pch_post_disable_lvds;
 894         } else {
 895                 intel_encoder->disable = gmch_disable_lvds;
 896         }
 897         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
 898         intel_encoder->get_config = intel_lvds_get_config;
 899         intel_encoder->update_pipe = intel_panel_update_backlight;
 900         intel_connector->get_hw_state = intel_connector_get_hw_state;
 901
 902         intel_connector_attach_encoder(intel_connector, intel_encoder);
 903
 904         intel_encoder->type = INTEL_OUTPUT_LVDS;
 905         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 906         intel_encoder->port = PORT_NONE;
 907         intel_encoder->cloneable = 0;
 908         if (INTEL_GEN(dev_priv) < 4)
 909                 intel_encoder->pipe_mask = BIT(PIPE_B);
 910         else
 911                 intel_encoder->pipe_mask = ~0;
 912
 913         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
 914         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 915         connector->interlace_allowed = false;
 916         connector->doublescan_allowed = false;
 917
 918         lvds_encoder->reg = lvds_reg;
 919
 920         /* create the scaling mode property */
 921         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
 922         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
 923         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
 924         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
 925         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
 926
 927         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
 928         lvds_encoder->init_lvds_val = lvds;
 929
 930         /*
 931          * LVDS discovery:
 932          * 1) check for EDID on DDC
 933          * 2) check for VBT data
 934          * 3) check to see if LVDS is already on
 935          *    if none of the above, no panel
 936          */
 937
 938         /*
 939          * Attempt to get the fixed panel mode from DDC.  Assume that the
 940          * preferred mode is the right one.
 941          */
 942         mutex_lock(&dev->mode_config.mutex);
 943         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 944                 edid = drm_get_edid_switcheroo(connector,
 945                                     intel_gmbus_get_adapter(dev_priv, pin));
 946         else
 947                 edid = drm_get_edid(connector,
 948                                     intel_gmbus_get_adapter(dev_priv, pin));
 949         if (edid) {
 950                 if (drm_add_edid_modes(connector, edid)) {
 951                         drm_connector_update_edid_property(connector,
 952                                                                 edid);
 953                 } else {
 954                         kfree(edid);
 955                         edid = ERR_PTR(-EINVAL);
 956                 }
 957         } else {
 958                 edid = ERR_PTR(-ENOENT);
 959         }
 960         intel_connector->edid = edid;
 961
 962         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
 963         if (fixed_mode)
 964                 goto out;
 965
 966         /* Failed to get EDID, what about VBT? */
 967         fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
 968         if (fixed_mode)
 969                 goto out;
 970
 971         /*
 972          * If we didn't get EDID, try checking if the panel is already turned
 973          * on.  If so, assume that whatever is currently programmed is the
 974          * correct mode.
 975          */
 976         fixed_mode = intel_encoder_current_mode(intel_encoder);
 977         if (fixed_mode) {
 978                 drm_dbg_kms(&dev_priv->drm, "using current (BIOS) mode: ");
 979                 drm_mode_debug_printmodeline(fixed_mode);
 980                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 981         }
 982
 983         /* If we still don't have a mode after all that, give up. */
 984         if (!fixed_mode)
 985                 goto failed;
 986
 987 out:
 988         mutex_unlock(&dev->mode_config.mutex);
 989
 990         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
 991         intel_panel_setup_backlight(connector, INVALID_PIPE);
 992
 993         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
 994         drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n",
 995                     lvds_encoder->is_dual_link ? "dual" : "single");
 996
 997         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
 998
 999         return;
1000
1001 failed:
1002         mutex_unlock(&dev->mode_config.mutex);
1003
1004         drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n");
1005         drm_connector_cleanup(connector);
1006         drm_encoder_cleanup(encoder);
1007         kfree(lvds_encoder);
1008         intel_connector_free(intel_connector);
1009         return;
1010 }