2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <drm/intel_lpe_audio.h>
41 #include "i915_debugfs.h"
43 #include "intel_atomic.h"
44 #include "intel_connector.h"
45 #include "intel_ddi.h"
47 #include "intel_display_types.h"
49 #include "intel_gmbus.h"
50 #include "intel_hdcp.h"
51 #include "intel_hdmi.h"
52 #include "intel_lspcon.h"
53 #include "intel_panel.h"
55 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
57 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
61 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
63 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
64 struct drm_i915_private *dev_priv = to_i915(dev);
67 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
70 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
71 "HDMI port enabled, expecting disabled\n");
75 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
76 enum transcoder cpu_transcoder)
78 drm_WARN(&dev_priv->drm,
79 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
80 TRANS_DDI_FUNC_ENABLE,
81 "HDMI transcoder function enabled, expecting disabled\n");
84 static u32 g4x_infoframe_index(unsigned int type)
87 case HDMI_PACKET_TYPE_GAMUT_METADATA:
88 return VIDEO_DIP_SELECT_GAMUT;
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_SELECT_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_SELECT_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_SELECT_VENDOR;
101 static u32 g4x_infoframe_enable(unsigned int type)
104 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
105 return VIDEO_DIP_ENABLE_GCP;
106 case HDMI_PACKET_TYPE_GAMUT_METADATA:
107 return VIDEO_DIP_ENABLE_GAMUT;
110 case HDMI_INFOFRAME_TYPE_AVI:
111 return VIDEO_DIP_ENABLE_AVI;
112 case HDMI_INFOFRAME_TYPE_SPD:
113 return VIDEO_DIP_ENABLE_SPD;
114 case HDMI_INFOFRAME_TYPE_VENDOR:
115 return VIDEO_DIP_ENABLE_VENDOR;
116 case HDMI_INFOFRAME_TYPE_DRM:
124 static u32 hsw_infoframe_enable(unsigned int type)
127 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
128 return VIDEO_DIP_ENABLE_GCP_HSW;
129 case HDMI_PACKET_TYPE_GAMUT_METADATA:
130 return VIDEO_DIP_ENABLE_GMP_HSW;
132 return VIDEO_DIP_ENABLE_VSC_HSW;
134 return VDIP_ENABLE_PPS;
135 case HDMI_INFOFRAME_TYPE_AVI:
136 return VIDEO_DIP_ENABLE_AVI_HSW;
137 case HDMI_INFOFRAME_TYPE_SPD:
138 return VIDEO_DIP_ENABLE_SPD_HSW;
139 case HDMI_INFOFRAME_TYPE_VENDOR:
140 return VIDEO_DIP_ENABLE_VS_HSW;
141 case HDMI_INFOFRAME_TYPE_DRM:
142 return VIDEO_DIP_ENABLE_DRM_GLK;
150 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
151 enum transcoder cpu_transcoder,
156 case HDMI_PACKET_TYPE_GAMUT_METADATA:
157 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
159 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
161 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
162 case HDMI_INFOFRAME_TYPE_AVI:
163 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
164 case HDMI_INFOFRAME_TYPE_SPD:
165 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
166 case HDMI_INFOFRAME_TYPE_VENDOR:
167 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_DRM:
169 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
172 return INVALID_MMIO_REG;
176 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
181 return VIDEO_DIP_VSC_DATA_SIZE;
183 return VIDEO_DIP_PPS_DATA_SIZE;
184 case HDMI_PACKET_TYPE_GAMUT_METADATA:
185 if (DISPLAY_VER(dev_priv) >= 11)
186 return VIDEO_DIP_GMP_DATA_SIZE;
188 return VIDEO_DIP_DATA_SIZE;
190 return VIDEO_DIP_DATA_SIZE;
194 static void g4x_write_infoframe(struct intel_encoder *encoder,
195 const struct intel_crtc_state *crtc_state,
197 const void *frame, ssize_t len)
199 const u32 *data = frame;
200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
201 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
204 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
205 "Writing DIP with CTL reg disabled\n");
207 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
208 val |= g4x_infoframe_index(type);
210 val &= ~g4x_infoframe_enable(type);
212 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
214 for (i = 0; i < len; i += 4) {
215 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
218 /* Write every possible data byte to force correct ECC calculation. */
219 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
220 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
222 val |= g4x_infoframe_enable(type);
223 val &= ~VIDEO_DIP_FREQ_MASK;
224 val |= VIDEO_DIP_FREQ_VSYNC;
226 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
227 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
230 static void g4x_read_infoframe(struct intel_encoder *encoder,
231 const struct intel_crtc_state *crtc_state,
233 void *frame, ssize_t len)
235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
236 u32 val, *data = frame;
239 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
241 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
242 val |= g4x_infoframe_index(type);
244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
246 for (i = 0; i < len; i += 4)
247 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
250 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
251 const struct intel_crtc_state *pipe_config)
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
254 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
256 if ((val & VIDEO_DIP_ENABLE) == 0)
259 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
262 return val & (VIDEO_DIP_ENABLE_AVI |
263 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
266 static void ibx_write_infoframe(struct intel_encoder *encoder,
267 const struct intel_crtc_state *crtc_state,
269 const void *frame, ssize_t len)
271 const u32 *data = frame;
272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
274 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
275 u32 val = intel_de_read(dev_priv, reg);
278 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
279 "Writing DIP with CTL reg disabled\n");
281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
282 val |= g4x_infoframe_index(type);
284 val &= ~g4x_infoframe_enable(type);
286 intel_de_write(dev_priv, reg, val);
288 for (i = 0; i < len; i += 4) {
289 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
293 /* Write every possible data byte to force correct ECC calculation. */
294 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
295 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
297 val |= g4x_infoframe_enable(type);
298 val &= ~VIDEO_DIP_FREQ_MASK;
299 val |= VIDEO_DIP_FREQ_VSYNC;
301 intel_de_write(dev_priv, reg, val);
302 intel_de_posting_read(dev_priv, reg);
305 static void ibx_read_infoframe(struct intel_encoder *encoder,
306 const struct intel_crtc_state *crtc_state,
308 void *frame, ssize_t len)
310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
312 u32 val, *data = frame;
315 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
317 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
318 val |= g4x_infoframe_index(type);
320 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
322 for (i = 0; i < len; i += 4)
323 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
326 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
327 const struct intel_crtc_state *pipe_config)
329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
330 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
331 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
332 u32 val = intel_de_read(dev_priv, reg);
334 if ((val & VIDEO_DIP_ENABLE) == 0)
337 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
340 return val & (VIDEO_DIP_ENABLE_AVI |
341 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
342 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
345 static void cpt_write_infoframe(struct intel_encoder *encoder,
346 const struct intel_crtc_state *crtc_state,
348 const void *frame, ssize_t len)
350 const u32 *data = frame;
351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
353 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
354 u32 val = intel_de_read(dev_priv, reg);
357 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
358 "Writing DIP with CTL reg disabled\n");
360 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
361 val |= g4x_infoframe_index(type);
363 /* The DIP control register spec says that we need to update the AVI
364 * infoframe without clearing its enable bit */
365 if (type != HDMI_INFOFRAME_TYPE_AVI)
366 val &= ~g4x_infoframe_enable(type);
368 intel_de_write(dev_priv, reg, val);
370 for (i = 0; i < len; i += 4) {
371 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
375 /* Write every possible data byte to force correct ECC calculation. */
376 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
377 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
379 val |= g4x_infoframe_enable(type);
380 val &= ~VIDEO_DIP_FREQ_MASK;
381 val |= VIDEO_DIP_FREQ_VSYNC;
383 intel_de_write(dev_priv, reg, val);
384 intel_de_posting_read(dev_priv, reg);
387 static void cpt_read_infoframe(struct intel_encoder *encoder,
388 const struct intel_crtc_state *crtc_state,
390 void *frame, ssize_t len)
392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
394 u32 val, *data = frame;
397 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
399 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
400 val |= g4x_infoframe_index(type);
402 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
404 for (i = 0; i < len; i += 4)
405 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
408 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
409 const struct intel_crtc_state *pipe_config)
411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
412 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
413 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
415 if ((val & VIDEO_DIP_ENABLE) == 0)
418 return val & (VIDEO_DIP_ENABLE_AVI |
419 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
420 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
423 static void vlv_write_infoframe(struct intel_encoder *encoder,
424 const struct intel_crtc_state *crtc_state,
426 const void *frame, ssize_t len)
428 const u32 *data = frame;
429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
431 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
432 u32 val = intel_de_read(dev_priv, reg);
435 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
436 "Writing DIP with CTL reg disabled\n");
438 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
439 val |= g4x_infoframe_index(type);
441 val &= ~g4x_infoframe_enable(type);
443 intel_de_write(dev_priv, reg, val);
445 for (i = 0; i < len; i += 4) {
446 intel_de_write(dev_priv,
447 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
450 /* Write every possible data byte to force correct ECC calculation. */
451 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
452 intel_de_write(dev_priv,
453 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
455 val |= g4x_infoframe_enable(type);
456 val &= ~VIDEO_DIP_FREQ_MASK;
457 val |= VIDEO_DIP_FREQ_VSYNC;
459 intel_de_write(dev_priv, reg, val);
460 intel_de_posting_read(dev_priv, reg);
463 static void vlv_read_infoframe(struct intel_encoder *encoder,
464 const struct intel_crtc_state *crtc_state,
466 void *frame, ssize_t len)
468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
470 u32 val, *data = frame;
473 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
475 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
476 val |= g4x_infoframe_index(type);
478 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
480 for (i = 0; i < len; i += 4)
481 *data++ = intel_de_read(dev_priv,
482 VLV_TVIDEO_DIP_DATA(crtc->pipe));
485 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
486 const struct intel_crtc_state *pipe_config)
488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
490 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
492 if ((val & VIDEO_DIP_ENABLE) == 0)
495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
498 return val & (VIDEO_DIP_ENABLE_AVI |
499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
503 void hsw_write_infoframe(struct intel_encoder *encoder,
504 const struct intel_crtc_state *crtc_state,
506 const void *frame, ssize_t len)
508 const u32 *data = frame;
509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
514 u32 val = intel_de_read(dev_priv, ctl_reg);
516 data_size = hsw_dip_data_size(dev_priv, type);
518 drm_WARN_ON(&dev_priv->drm, len > data_size);
520 val &= ~hsw_infoframe_enable(type);
521 intel_de_write(dev_priv, ctl_reg, val);
523 for (i = 0; i < len; i += 4) {
524 intel_de_write(dev_priv,
525 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
529 /* Write every possible data byte to force correct ECC calculation. */
530 for (; i < data_size; i += 4)
531 intel_de_write(dev_priv,
532 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
536 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
540 val |= hsw_infoframe_enable(type);
541 intel_de_write(dev_priv, ctl_reg, val);
542 intel_de_posting_read(dev_priv, ctl_reg);
545 void hsw_read_infoframe(struct intel_encoder *encoder,
546 const struct intel_crtc_state *crtc_state,
547 unsigned int type, void *frame, ssize_t len)
549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
554 for (i = 0; i < len; i += 4)
555 *data++ = intel_de_read(dev_priv,
556 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
559 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
560 const struct intel_crtc_state *pipe_config)
562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
563 u32 val = intel_de_read(dev_priv,
564 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
571 if (DISPLAY_VER(dev_priv) >= 10)
572 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
577 static const u8 infoframe_type_to_idx[] = {
578 HDMI_PACKET_TYPE_GENERAL_CONTROL,
579 HDMI_PACKET_TYPE_GAMUT_METADATA,
581 HDMI_INFOFRAME_TYPE_AVI,
582 HDMI_INFOFRAME_TYPE_SPD,
583 HDMI_INFOFRAME_TYPE_VENDOR,
584 HDMI_INFOFRAME_TYPE_DRM,
587 u32 intel_hdmi_infoframe_enable(unsigned int type)
591 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
592 if (infoframe_type_to_idx[i] == type)
599 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
600 const struct intel_crtc_state *crtc_state)
602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
607 val = dig_port->infoframes_enabled(encoder, crtc_state);
609 /* map from hardware bits to dip idx */
610 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
611 unsigned int type = infoframe_type_to_idx[i];
613 if (HAS_DDI(dev_priv)) {
614 if (val & hsw_infoframe_enable(type))
617 if (val & g4x_infoframe_enable(type))
626 * The data we write to the DIP data buffer registers is 1 byte bigger than the
627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
628 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
629 * used for both technologies.
631 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
632 * DW1: DB3 | DB2 | DB1 | DB0
633 * DW2: DB7 | DB6 | DB5 | DB4
636 * (HB is Header Byte, DB is Data Byte)
638 * The hdmi pack() functions don't know about that hardware specific hole so we
639 * trick them by giving an offset into the buffer and moving back the header
642 static void intel_write_infoframe(struct intel_encoder *encoder,
643 const struct intel_crtc_state *crtc_state,
644 enum hdmi_infoframe_type type,
645 const union hdmi_infoframe *frame)
647 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
648 u8 buffer[VIDEO_DIP_DATA_SIZE];
651 if ((crtc_state->infoframes.enable &
652 intel_hdmi_infoframe_enable(type)) == 0)
655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
658 /* see comment above for the reason for this offset */
659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
660 if (drm_WARN_ON(encoder->base.dev, len < 0))
663 /* Insert the 'hole' (see big comment above) at position 3 */
664 memmove(&buffer[0], &buffer[1], 3);
668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
671 void intel_read_infoframe(struct intel_encoder *encoder,
672 const struct intel_crtc_state *crtc_state,
673 enum hdmi_infoframe_type type,
674 union hdmi_infoframe *frame)
676 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
677 u8 buffer[VIDEO_DIP_DATA_SIZE];
680 if ((crtc_state->infoframes.enable &
681 intel_hdmi_infoframe_enable(type)) == 0)
684 dig_port->read_infoframe(encoder, crtc_state,
685 type, buffer, sizeof(buffer));
687 /* Fill the 'hole' (see big comment above) at position 3 */
688 memmove(&buffer[1], &buffer[0], 3);
690 /* see comment above for the reason for this offset */
691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
693 drm_dbg_kms(encoder->base.dev,
694 "Failed to unpack infoframe type 0x%02x\n", type);
698 if (frame->any.type != type)
699 drm_dbg_kms(encoder->base.dev,
700 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
701 frame->any.type, type);
705 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
706 struct intel_crtc_state *crtc_state,
707 struct drm_connector_state *conn_state)
709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
710 const struct drm_display_mode *adjusted_mode =
711 &crtc_state->hw.adjusted_mode;
712 struct drm_connector *connector = conn_state->connector;
715 if (!crtc_state->has_infoframe)
718 crtc_state->infoframes.enable |=
719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
727 frame->colorspace = HDMI_COLORSPACE_YUV420;
728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
729 frame->colorspace = HDMI_COLORSPACE_YUV444;
731 frame->colorspace = HDMI_COLORSPACE_RGB;
733 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
735 /* nonsense combination */
736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
740 drm_hdmi_avi_infoframe_quant_range(frame, connector,
742 crtc_state->limited_color_range ?
743 HDMI_QUANTIZATION_RANGE_LIMITED :
744 HDMI_QUANTIZATION_RANGE_FULL);
746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
750 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
752 /* TODO: handle pixel repetition for YCBCR420 outputs */
754 ret = hdmi_avi_infoframe_check(frame);
755 if (drm_WARN_ON(encoder->base.dev, ret))
762 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
763 struct intel_crtc_state *crtc_state,
764 struct drm_connector_state *conn_state)
766 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
769 if (!crtc_state->has_infoframe)
772 crtc_state->infoframes.enable |=
773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
775 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
776 if (drm_WARN_ON(encoder->base.dev, ret))
779 frame->sdi = HDMI_SPD_SDI_PC;
781 ret = hdmi_spd_infoframe_check(frame);
782 if (drm_WARN_ON(encoder->base.dev, ret))
789 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
790 struct intel_crtc_state *crtc_state,
791 struct drm_connector_state *conn_state)
793 struct hdmi_vendor_infoframe *frame =
794 &crtc_state->infoframes.hdmi.vendor.hdmi;
795 const struct drm_display_info *info =
796 &conn_state->connector->display_info;
799 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
802 crtc_state->infoframes.enable |=
803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
805 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
806 conn_state->connector,
807 &crtc_state->hw.adjusted_mode);
808 if (drm_WARN_ON(encoder->base.dev, ret))
811 ret = hdmi_vendor_infoframe_check(frame);
812 if (drm_WARN_ON(encoder->base.dev, ret))
819 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
820 struct intel_crtc_state *crtc_state,
821 struct drm_connector_state *conn_state)
823 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
827 if (DISPLAY_VER(dev_priv) < 10)
830 if (!crtc_state->has_infoframe)
833 if (!conn_state->hdr_output_metadata)
836 crtc_state->infoframes.enable |=
837 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
839 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
841 drm_dbg_kms(&dev_priv->drm,
842 "couldn't set HDR metadata in infoframe\n");
846 ret = hdmi_drm_infoframe_check(frame);
847 if (drm_WARN_ON(&dev_priv->drm, ret))
853 static void g4x_set_infoframes(struct intel_encoder *encoder,
855 const struct intel_crtc_state *crtc_state,
856 const struct drm_connector_state *conn_state)
858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
860 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
861 i915_reg_t reg = VIDEO_DIP_CTL;
862 u32 val = intel_de_read(dev_priv, reg);
863 u32 port = VIDEO_DIP_PORT(encoder->port);
865 assert_hdmi_port_disabled(intel_hdmi);
867 /* If the registers were not initialized yet, they might be zeroes,
868 * which means we're selecting the AVI DIP and we're setting its
869 * frequency to once. This seems to really confuse the HW and make
870 * things stop working (the register spec says the AVI always needs to
871 * be sent every VSync). So here we avoid writing to the register more
872 * than we need and also explicitly select the AVI DIP and explicitly
873 * set its frequency to every VSync. Avoiding to write it twice seems to
874 * be enough to solve the problem, but being defensive shouldn't hurt us
876 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
879 if (!(val & VIDEO_DIP_ENABLE))
881 if (port != (val & VIDEO_DIP_PORT_MASK)) {
882 drm_dbg_kms(&dev_priv->drm,
883 "video DIP still enabled on port %c\n",
884 (val & VIDEO_DIP_PORT_MASK) >> 29);
887 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
888 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
889 intel_de_write(dev_priv, reg, val);
890 intel_de_posting_read(dev_priv, reg);
894 if (port != (val & VIDEO_DIP_PORT_MASK)) {
895 if (val & VIDEO_DIP_ENABLE) {
896 drm_dbg_kms(&dev_priv->drm,
897 "video DIP already enabled on port %c\n",
898 (val & VIDEO_DIP_PORT_MASK) >> 29);
901 val &= ~VIDEO_DIP_PORT_MASK;
905 val |= VIDEO_DIP_ENABLE;
906 val &= ~(VIDEO_DIP_ENABLE_AVI |
907 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
909 intel_de_write(dev_priv, reg, val);
910 intel_de_posting_read(dev_priv, reg);
912 intel_write_infoframe(encoder, crtc_state,
913 HDMI_INFOFRAME_TYPE_AVI,
914 &crtc_state->infoframes.avi);
915 intel_write_infoframe(encoder, crtc_state,
916 HDMI_INFOFRAME_TYPE_SPD,
917 &crtc_state->infoframes.spd);
918 intel_write_infoframe(encoder, crtc_state,
919 HDMI_INFOFRAME_TYPE_VENDOR,
920 &crtc_state->infoframes.hdmi);
924 * Determine if default_phase=1 can be indicated in the GCP infoframe.
926 * From HDMI specification 1.4a:
927 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
928 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
929 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
930 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
933 static bool gcp_default_phase_possible(int pipe_bpp,
934 const struct drm_display_mode *mode)
936 unsigned int pixels_per_group;
940 /* 4 pixels in 5 clocks */
941 pixels_per_group = 4;
944 /* 2 pixels in 3 clocks */
945 pixels_per_group = 2;
948 /* 1 pixel in 2 clocks */
949 pixels_per_group = 1;
952 /* phase information not relevant for 8bpc */
956 return mode->crtc_hdisplay % pixels_per_group == 0 &&
957 mode->crtc_htotal % pixels_per_group == 0 &&
958 mode->crtc_hblank_start % pixels_per_group == 0 &&
959 mode->crtc_hblank_end % pixels_per_group == 0 &&
960 mode->crtc_hsync_start % pixels_per_group == 0 &&
961 mode->crtc_hsync_end % pixels_per_group == 0 &&
962 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
963 mode->crtc_htotal/2 % pixels_per_group == 0);
966 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
967 const struct intel_crtc_state *crtc_state,
968 const struct drm_connector_state *conn_state)
970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
974 if ((crtc_state->infoframes.enable &
975 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
978 if (HAS_DDI(dev_priv))
979 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
980 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
981 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
982 else if (HAS_PCH_SPLIT(dev_priv))
983 reg = TVIDEO_DIP_GCP(crtc->pipe);
987 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
992 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
993 struct intel_crtc_state *crtc_state)
995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
999 if ((crtc_state->infoframes.enable &
1000 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1003 if (HAS_DDI(dev_priv))
1004 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1005 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1006 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1007 else if (HAS_PCH_SPLIT(dev_priv))
1008 reg = TVIDEO_DIP_GCP(crtc->pipe);
1012 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1015 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1016 struct intel_crtc_state *crtc_state,
1017 struct drm_connector_state *conn_state)
1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1021 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1024 crtc_state->infoframes.enable |=
1025 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1027 /* Indicate color indication for deep color mode */
1028 if (crtc_state->pipe_bpp > 24)
1029 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1031 /* Enable default_phase whenever the display mode is suitably aligned */
1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1033 &crtc_state->hw.adjusted_mode))
1034 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1037 static void ibx_set_infoframes(struct intel_encoder *encoder,
1039 const struct intel_crtc_state *crtc_state,
1040 const struct drm_connector_state *conn_state)
1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1045 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1046 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1047 u32 val = intel_de_read(dev_priv, reg);
1048 u32 port = VIDEO_DIP_PORT(encoder->port);
1050 assert_hdmi_port_disabled(intel_hdmi);
1052 /* See the big comment in g4x_set_infoframes() */
1053 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1056 if (!(val & VIDEO_DIP_ENABLE))
1058 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1059 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1060 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1061 intel_de_write(dev_priv, reg, val);
1062 intel_de_posting_read(dev_priv, reg);
1066 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1067 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1068 "DIP already enabled on port %c\n",
1069 (val & VIDEO_DIP_PORT_MASK) >> 29);
1070 val &= ~VIDEO_DIP_PORT_MASK;
1074 val |= VIDEO_DIP_ENABLE;
1075 val &= ~(VIDEO_DIP_ENABLE_AVI |
1076 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1077 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1079 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1080 val |= VIDEO_DIP_ENABLE_GCP;
1082 intel_de_write(dev_priv, reg, val);
1083 intel_de_posting_read(dev_priv, reg);
1085 intel_write_infoframe(encoder, crtc_state,
1086 HDMI_INFOFRAME_TYPE_AVI,
1087 &crtc_state->infoframes.avi);
1088 intel_write_infoframe(encoder, crtc_state,
1089 HDMI_INFOFRAME_TYPE_SPD,
1090 &crtc_state->infoframes.spd);
1091 intel_write_infoframe(encoder, crtc_state,
1092 HDMI_INFOFRAME_TYPE_VENDOR,
1093 &crtc_state->infoframes.hdmi);
1096 static void cpt_set_infoframes(struct intel_encoder *encoder,
1098 const struct intel_crtc_state *crtc_state,
1099 const struct drm_connector_state *conn_state)
1101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1103 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1104 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1105 u32 val = intel_de_read(dev_priv, reg);
1107 assert_hdmi_port_disabled(intel_hdmi);
1109 /* See the big comment in g4x_set_infoframes() */
1110 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1113 if (!(val & VIDEO_DIP_ENABLE))
1115 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1116 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1117 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1118 intel_de_write(dev_priv, reg, val);
1119 intel_de_posting_read(dev_priv, reg);
1123 /* Set both together, unset both together: see the spec. */
1124 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1125 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1126 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1128 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1129 val |= VIDEO_DIP_ENABLE_GCP;
1131 intel_de_write(dev_priv, reg, val);
1132 intel_de_posting_read(dev_priv, reg);
1134 intel_write_infoframe(encoder, crtc_state,
1135 HDMI_INFOFRAME_TYPE_AVI,
1136 &crtc_state->infoframes.avi);
1137 intel_write_infoframe(encoder, crtc_state,
1138 HDMI_INFOFRAME_TYPE_SPD,
1139 &crtc_state->infoframes.spd);
1140 intel_write_infoframe(encoder, crtc_state,
1141 HDMI_INFOFRAME_TYPE_VENDOR,
1142 &crtc_state->infoframes.hdmi);
1145 static void vlv_set_infoframes(struct intel_encoder *encoder,
1147 const struct intel_crtc_state *crtc_state,
1148 const struct drm_connector_state *conn_state)
1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1153 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1154 u32 val = intel_de_read(dev_priv, reg);
1155 u32 port = VIDEO_DIP_PORT(encoder->port);
1157 assert_hdmi_port_disabled(intel_hdmi);
1159 /* See the big comment in g4x_set_infoframes() */
1160 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1163 if (!(val & VIDEO_DIP_ENABLE))
1165 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1166 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1167 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1168 intel_de_write(dev_priv, reg, val);
1169 intel_de_posting_read(dev_priv, reg);
1173 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1174 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1175 "DIP already enabled on port %c\n",
1176 (val & VIDEO_DIP_PORT_MASK) >> 29);
1177 val &= ~VIDEO_DIP_PORT_MASK;
1181 val |= VIDEO_DIP_ENABLE;
1182 val &= ~(VIDEO_DIP_ENABLE_AVI |
1183 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1184 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1186 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1187 val |= VIDEO_DIP_ENABLE_GCP;
1189 intel_de_write(dev_priv, reg, val);
1190 intel_de_posting_read(dev_priv, reg);
1192 intel_write_infoframe(encoder, crtc_state,
1193 HDMI_INFOFRAME_TYPE_AVI,
1194 &crtc_state->infoframes.avi);
1195 intel_write_infoframe(encoder, crtc_state,
1196 HDMI_INFOFRAME_TYPE_SPD,
1197 &crtc_state->infoframes.spd);
1198 intel_write_infoframe(encoder, crtc_state,
1199 HDMI_INFOFRAME_TYPE_VENDOR,
1200 &crtc_state->infoframes.hdmi);
1203 static void hsw_set_infoframes(struct intel_encoder *encoder,
1205 const struct intel_crtc_state *crtc_state,
1206 const struct drm_connector_state *conn_state)
1208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1209 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1210 u32 val = intel_de_read(dev_priv, reg);
1212 assert_hdmi_transcoder_func_disabled(dev_priv,
1213 crtc_state->cpu_transcoder);
1215 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1216 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1217 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1218 VIDEO_DIP_ENABLE_DRM_GLK);
1221 intel_de_write(dev_priv, reg, val);
1222 intel_de_posting_read(dev_priv, reg);
1226 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1227 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1229 intel_de_write(dev_priv, reg, val);
1230 intel_de_posting_read(dev_priv, reg);
1232 intel_write_infoframe(encoder, crtc_state,
1233 HDMI_INFOFRAME_TYPE_AVI,
1234 &crtc_state->infoframes.avi);
1235 intel_write_infoframe(encoder, crtc_state,
1236 HDMI_INFOFRAME_TYPE_SPD,
1237 &crtc_state->infoframes.spd);
1238 intel_write_infoframe(encoder, crtc_state,
1239 HDMI_INFOFRAME_TYPE_VENDOR,
1240 &crtc_state->infoframes.hdmi);
1241 intel_write_infoframe(encoder, crtc_state,
1242 HDMI_INFOFRAME_TYPE_DRM,
1243 &crtc_state->infoframes.drm);
1246 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1248 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1249 struct i2c_adapter *adapter =
1250 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1252 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1255 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1256 enable ? "Enabling" : "Disabling");
1258 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1261 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1262 unsigned int offset, void *buffer, size_t size)
1264 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1265 struct intel_hdmi *hdmi = &dig_port->hdmi;
1266 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1269 u8 start = offset & 0xff;
1270 struct i2c_msg msgs[] = {
1272 .addr = DRM_HDCP_DDC_ADDR,
1278 .addr = DRM_HDCP_DDC_ADDR,
1284 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1285 if (ret == ARRAY_SIZE(msgs))
1287 return ret >= 0 ? -EIO : ret;
1290 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1291 unsigned int offset, void *buffer, size_t size)
1293 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1294 struct intel_hdmi *hdmi = &dig_port->hdmi;
1295 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1301 write_buf = kzalloc(size + 1, GFP_KERNEL);
1305 write_buf[0] = offset & 0xff;
1306 memcpy(&write_buf[1], buffer, size);
1308 msg.addr = DRM_HDCP_DDC_ADDR;
1311 msg.buf = write_buf;
1313 ret = i2c_transfer(adapter, &msg, 1);
1324 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1327 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1328 struct intel_hdmi *hdmi = &dig_port->hdmi;
1329 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1333 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1336 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1341 ret = intel_gmbus_output_aksv(adapter);
1343 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1349 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1352 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1355 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1358 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1364 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1367 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1370 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1371 bstatus, DRM_HDCP_BSTATUS_LEN);
1373 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1379 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1380 bool *repeater_present)
1382 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1388 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1392 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1397 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1400 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1404 ri_prime, DRM_HDCP_RI_LEN);
1406 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1412 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1415 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1421 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1425 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1430 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1431 int num_downstream, u8 *ksv_fifo)
1433 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1436 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1438 drm_dbg_kms(&i915->drm,
1439 "Read ksv fifo over DDC failed (%d)\n", ret);
1446 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1449 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1452 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1455 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1456 part, DRM_HDCP_V_PRIME_PART_LEN);
1458 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1463 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1464 enum transcoder cpu_transcoder)
1466 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1467 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1468 struct drm_crtc *crtc = connector->base.state->crtc;
1469 struct intel_crtc *intel_crtc = container_of(crtc,
1470 struct intel_crtc, base);
1475 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe));
1476 if (scanline > 100 && scanline < 200)
1478 usleep_range(25, 50);
1481 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1482 false, TRANS_DDI_HDCP_SIGNALLING);
1484 drm_err(&dev_priv->drm,
1485 "Disable HDCP signalling failed (%d)\n", ret);
1489 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1490 true, TRANS_DDI_HDCP_SIGNALLING);
1492 drm_err(&dev_priv->drm,
1493 "Enable HDCP signalling failed (%d)\n", ret);
1501 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1502 enum transcoder cpu_transcoder,
1505 struct intel_hdmi *hdmi = &dig_port->hdmi;
1506 struct intel_connector *connector = hdmi->attached_connector;
1507 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1511 usleep_range(6, 60); /* Bspec says >= 6us */
1513 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1514 cpu_transcoder, enable,
1515 TRANS_DDI_HDCP_SIGNALLING);
1517 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1518 enable ? "Enable" : "Disable", ret);
1523 * WA: To fix incorrect positioning of the window of
1524 * opportunity and enc_en signalling in KABYLAKE.
1526 if (IS_KABYLAKE(dev_priv) && enable)
1527 return kbl_repositioning_enc_en_signal(connector,
1534 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1535 struct intel_connector *connector)
1537 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1538 enum port port = dig_port->base.port;
1539 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1543 u8 shim[DRM_HDCP_RI_LEN];
1546 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1550 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1552 /* Wait for Ri prime match */
1553 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1554 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1555 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1556 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1557 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1565 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1566 struct intel_connector *connector)
1568 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1571 for (retry = 0; retry < 3; retry++)
1572 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1575 drm_err(&i915->drm, "Link check failed\n");
1579 struct hdcp2_hdmi_msg_timeout {
1584 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1585 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1586 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1587 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1588 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1589 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1593 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1596 return intel_hdmi_hdcp_read(dig_port,
1597 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1599 HDCP_2_2_HDMI_RXSTATUS_LEN);
1602 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1606 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1608 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1610 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1613 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1614 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1615 return hdcp2_msg_timeout[i].timeout;
1622 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1623 u8 msg_id, bool *msg_ready,
1626 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1627 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1630 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1632 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1637 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1640 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1641 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1644 *msg_ready = *msg_sz;
1650 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1651 u8 msg_id, bool paired)
1653 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1654 bool msg_ready = false;
1658 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1662 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1665 !ret && msg_ready && msg_sz, timeout * 1000,
1668 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1669 msg_id, ret, timeout);
1671 return ret ? ret : msg_sz;
1675 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1676 void *buf, size_t size)
1678 unsigned int offset;
1680 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1681 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1685 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1686 u8 msg_id, void *buf, size_t size)
1688 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1689 struct intel_hdmi *hdmi = &dig_port->hdmi;
1690 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1691 unsigned int offset;
1694 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1700 * Available msg size should be equal to or lesser than the
1704 drm_dbg_kms(&i915->drm,
1705 "msg_sz(%zd) is more than exp size(%zu)\n",
1710 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1711 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1713 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1720 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1721 struct intel_connector *connector)
1723 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1726 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1731 * Re-auth request and Link Integrity Failures are represented by
1732 * same bit. i.e reauth_req.
1734 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1735 ret = HDCP_REAUTH_REQUEST;
1736 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1737 ret = HDCP_TOPOLOGY_CHANGE;
1743 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1750 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1751 &hdcp2_version, sizeof(hdcp2_version));
1752 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1758 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1759 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1760 .read_bksv = intel_hdmi_hdcp_read_bksv,
1761 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1762 .repeater_present = intel_hdmi_hdcp_repeater_present,
1763 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1764 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1765 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1766 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1767 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1768 .check_link = intel_hdmi_hdcp_check_link,
1769 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1770 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1771 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1772 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1773 .protocol = HDCP_PROTOCOL_HDMI,
1776 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1778 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1779 int max_tmds_clock, vbt_max_tmds_clock;
1781 if (DISPLAY_VER(dev_priv) >= 10)
1782 max_tmds_clock = 594000;
1783 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1784 max_tmds_clock = 300000;
1785 else if (DISPLAY_VER(dev_priv) >= 5)
1786 max_tmds_clock = 225000;
1788 max_tmds_clock = 165000;
1790 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1791 if (vbt_max_tmds_clock)
1792 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1794 return max_tmds_clock;
1797 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1798 const struct drm_connector_state *conn_state)
1800 return hdmi->has_hdmi_sink &&
1801 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1804 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1805 bool respect_downstream_limits,
1808 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1809 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1811 if (respect_downstream_limits) {
1812 struct intel_connector *connector = hdmi->attached_connector;
1813 const struct drm_display_info *info = &connector->base.display_info;
1815 if (hdmi->dp_dual_mode.max_tmds_clock)
1816 max_tmds_clock = min(max_tmds_clock,
1817 hdmi->dp_dual_mode.max_tmds_clock);
1819 if (info->max_tmds_clock)
1820 max_tmds_clock = min(max_tmds_clock,
1821 info->max_tmds_clock);
1822 else if (!has_hdmi_sink)
1823 max_tmds_clock = min(max_tmds_clock, 165000);
1826 return max_tmds_clock;
1829 static enum drm_mode_status
1830 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1831 int clock, bool respect_downstream_limits,
1834 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1837 return MODE_CLOCK_LOW;
1838 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1840 return MODE_CLOCK_HIGH;
1842 /* GLK DPLL can't generate 446-480 MHz */
1843 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1844 return MODE_CLOCK_RANGE;
1846 /* BXT/GLK DPLL can't generate 223-240 MHz */
1847 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1848 clock > 223333 && clock < 240000)
1849 return MODE_CLOCK_RANGE;
1851 /* CHV DPLL can't generate 216-240 MHz */
1852 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1853 return MODE_CLOCK_RANGE;
1858 static int intel_hdmi_port_clock(int clock, int bpc)
1861 * Need to adjust the port link by:
1865 return clock * bpc / 8;
1868 static bool intel_hdmi_bpc_possible(struct drm_connector *connector,
1869 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1871 struct drm_i915_private *i915 = to_i915(connector->dev);
1872 const struct drm_display_info *info = &connector->display_info;
1873 const struct drm_hdmi_info *hdmi = &info->hdmi;
1883 if (ycbcr420_output)
1884 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1886 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36;
1888 if (DISPLAY_VER(i915) < 11)
1894 if (ycbcr420_output)
1895 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1897 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30;
1906 static enum drm_mode_status
1907 intel_hdmi_mode_clock_valid(struct intel_hdmi *hdmi, int clock, bool has_hdmi_sink)
1909 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1910 struct drm_i915_private *dev_priv = to_i915(dev);
1911 enum drm_mode_status status;
1913 /* check if we can do 8bpc */
1914 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8),
1915 true, has_hdmi_sink);
1917 if (has_hdmi_sink) {
1918 /* if we can't do 8bpc we may still be able to do 12bpc */
1919 if (status != MODE_OK && !HAS_GMCH(dev_priv))
1920 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12),
1921 true, has_hdmi_sink);
1923 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1924 if (status != MODE_OK && DISPLAY_VER(dev_priv) >= 11)
1925 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10),
1926 true, has_hdmi_sink);
1932 static enum drm_mode_status
1933 intel_hdmi_mode_valid(struct drm_connector *connector,
1934 struct drm_display_mode *mode)
1936 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1937 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1938 struct drm_i915_private *dev_priv = to_i915(dev);
1939 enum drm_mode_status status;
1940 int clock = mode->clock;
1941 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1942 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1943 bool ycbcr_420_only;
1945 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1946 return MODE_NO_DBLESCAN;
1948 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1951 if (clock > max_dotclk)
1952 return MODE_CLOCK_HIGH;
1954 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1956 return MODE_CLOCK_LOW;
1960 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
1964 status = intel_hdmi_mode_clock_valid(hdmi, clock, has_hdmi_sink);
1965 if (status != MODE_OK) {
1966 if (ycbcr_420_only ||
1967 !connector->ycbcr_420_allowed ||
1968 !drm_mode_is_420_also(&connector->display_info, mode))
1972 status = intel_hdmi_mode_clock_valid(hdmi, clock, has_hdmi_sink);
1973 if (status != MODE_OK)
1977 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
1980 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1981 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1983 struct drm_atomic_state *state = crtc_state->uapi.state;
1984 struct drm_connector_state *connector_state;
1985 struct drm_connector *connector;
1988 if (crtc_state->pipe_bpp < bpc * 3)
1991 for_each_new_connector_in_state(state, connector, connector_state, i) {
1992 if (connector_state->crtc != crtc_state->uapi.crtc)
1995 if (!intel_hdmi_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2002 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2005 struct drm_i915_private *dev_priv =
2006 to_i915(crtc_state->uapi.crtc->dev);
2007 const struct drm_display_mode *adjusted_mode =
2008 &crtc_state->hw.adjusted_mode;
2011 * HDMI deep color affects the clocks, so it's only possible
2012 * when not cloning with other encoder types.
2014 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2017 /* Display Wa_1405510057:icl,ehl */
2018 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2019 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2020 (adjusted_mode->crtc_hblank_end -
2021 adjusted_mode->crtc_hblank_start) % 8 == 2)
2024 return intel_hdmi_deep_color_possible(crtc_state, bpc,
2025 crtc_state->has_hdmi_sink,
2026 crtc_state->output_format ==
2027 INTEL_OUTPUT_FORMAT_YCBCR420);
2030 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2031 struct intel_crtc_state *crtc_state,
2034 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2037 for (bpc = 12; bpc >= 10; bpc -= 2) {
2038 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2039 hdmi_port_clock_valid(intel_hdmi,
2040 intel_hdmi_port_clock(clock, bpc),
2041 true, crtc_state->has_hdmi_sink) == MODE_OK)
2048 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2049 struct intel_crtc_state *crtc_state)
2051 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2052 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2053 const struct drm_display_mode *adjusted_mode =
2054 &crtc_state->hw.adjusted_mode;
2055 int bpc, clock = adjusted_mode->crtc_clock;
2057 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2060 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2061 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2064 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2066 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2069 * pipe_bpp could already be below 8bpc due to
2070 * FDI bandwidth constraints. We shouldn't bump it
2071 * back up to 8bpc in that case.
2073 if (crtc_state->pipe_bpp > bpc * 3)
2074 crtc_state->pipe_bpp = bpc * 3;
2076 drm_dbg_kms(&i915->drm,
2077 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2078 bpc, crtc_state->pipe_bpp);
2080 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2081 false, crtc_state->has_hdmi_sink) != MODE_OK) {
2082 drm_dbg_kms(&i915->drm,
2083 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2084 crtc_state->port_clock);
2091 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2092 const struct drm_connector_state *conn_state)
2094 const struct intel_digital_connector_state *intel_conn_state =
2095 to_intel_digital_connector_state(conn_state);
2096 const struct drm_display_mode *adjusted_mode =
2097 &crtc_state->hw.adjusted_mode;
2100 * Our YCbCr output is always limited range.
2101 * crtc_state->limited_color_range only applies to RGB,
2102 * and it must never be set for YCbCr or we risk setting
2103 * some conflicting bits in PIPECONF which will mess up
2104 * the colors on the monitor.
2106 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2109 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2110 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2111 return crtc_state->has_hdmi_sink &&
2112 drm_default_rgb_quant_range(adjusted_mode) ==
2113 HDMI_QUANTIZATION_RANGE_LIMITED;
2115 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2119 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2120 const struct intel_crtc_state *crtc_state,
2121 const struct drm_connector_state *conn_state)
2123 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2124 const struct intel_digital_connector_state *intel_conn_state =
2125 to_intel_digital_connector_state(conn_state);
2127 if (!crtc_state->has_hdmi_sink)
2130 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2131 return intel_hdmi->has_audio;
2133 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2136 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2137 struct intel_crtc_state *crtc_state,
2138 const struct drm_connector_state *conn_state)
2140 struct drm_connector *connector = conn_state->connector;
2141 struct drm_i915_private *i915 = to_i915(connector->dev);
2142 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2144 bool ycbcr_420_only;
2146 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode);
2147 if (connector->ycbcr_420_allowed && ycbcr_420_only) {
2148 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2150 if (!connector->ycbcr_420_allowed && ycbcr_420_only)
2151 drm_dbg_kms(&i915->drm,
2152 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2153 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2156 ret = intel_hdmi_compute_clock(encoder, crtc_state);
2158 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
2159 connector->ycbcr_420_allowed &&
2160 drm_mode_is_420_also(&connector->display_info, adjusted_mode)) {
2161 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2162 ret = intel_hdmi_compute_clock(encoder, crtc_state);
2169 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2170 struct intel_crtc_state *pipe_config,
2171 struct drm_connector_state *conn_state)
2173 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2175 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2176 struct drm_connector *connector = conn_state->connector;
2177 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2180 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2183 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2184 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2187 if (pipe_config->has_hdmi_sink)
2188 pipe_config->has_infoframe = true;
2190 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2191 pipe_config->pixel_multiplier = 2;
2193 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2194 pipe_config->has_pch_encoder = true;
2196 pipe_config->has_audio =
2197 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2199 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state);
2203 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2204 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2209 pipe_config->limited_color_range =
2210 intel_hdmi_limited_color_range(pipe_config, conn_state);
2212 if (conn_state->picture_aspect_ratio)
2213 adjusted_mode->picture_aspect_ratio =
2214 conn_state->picture_aspect_ratio;
2216 pipe_config->lane_count = 4;
2218 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2219 if (scdc->scrambling.low_rates)
2220 pipe_config->hdmi_scrambling = true;
2222 if (pipe_config->port_clock > 340000) {
2223 pipe_config->hdmi_scrambling = true;
2224 pipe_config->hdmi_high_tmds_clock_ratio = true;
2228 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2231 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2232 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2236 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2237 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2241 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2242 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2246 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2247 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2255 intel_hdmi_unset_edid(struct drm_connector *connector)
2257 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2259 intel_hdmi->has_hdmi_sink = false;
2260 intel_hdmi->has_audio = false;
2262 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2263 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2265 kfree(to_intel_connector(connector)->detect_edid);
2266 to_intel_connector(connector)->detect_edid = NULL;
2270 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2272 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2273 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2274 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2275 struct i2c_adapter *adapter =
2276 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2277 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2280 * Type 1 DVI adaptors are not required to implement any
2281 * registers, so we can't always detect their presence.
2282 * Ideally we should be able to check the state of the
2283 * CONFIG1 pin, but no such luck on our hardware.
2285 * The only method left to us is to check the VBT to see
2286 * if the port is a dual mode capable DP port. But let's
2287 * only do that when we sucesfully read the EDID, to avoid
2288 * confusing log messages about DP dual mode adaptors when
2289 * there's nothing connected to the port.
2291 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2292 /* An overridden EDID imply that we want this port for testing.
2293 * Make sure not to set limits for that port.
2295 if (has_edid && !connector->override_edid &&
2296 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2297 drm_dbg_kms(&dev_priv->drm,
2298 "Assuming DP dual mode adaptor presence based on VBT\n");
2299 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2301 type = DRM_DP_DUAL_MODE_NONE;
2305 if (type == DRM_DP_DUAL_MODE_NONE)
2308 hdmi->dp_dual_mode.type = type;
2309 hdmi->dp_dual_mode.max_tmds_clock =
2310 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2312 drm_dbg_kms(&dev_priv->drm,
2313 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2314 drm_dp_get_dual_mode_type_name(type),
2315 hdmi->dp_dual_mode.max_tmds_clock);
2319 intel_hdmi_set_edid(struct drm_connector *connector)
2321 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2322 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2323 intel_wakeref_t wakeref;
2325 bool connected = false;
2326 struct i2c_adapter *i2c;
2328 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2330 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2332 edid = drm_get_edid(connector, i2c);
2334 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2335 drm_dbg_kms(&dev_priv->drm,
2336 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2337 intel_gmbus_force_bit(i2c, true);
2338 edid = drm_get_edid(connector, i2c);
2339 intel_gmbus_force_bit(i2c, false);
2342 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2344 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2346 to_intel_connector(connector)->detect_edid = edid;
2347 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2348 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2349 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2354 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2359 static enum drm_connector_status
2360 intel_hdmi_detect(struct drm_connector *connector, bool force)
2362 enum drm_connector_status status = connector_status_disconnected;
2363 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2364 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2365 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2366 intel_wakeref_t wakeref;
2368 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2369 connector->base.id, connector->name);
2371 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2372 return connector_status_disconnected;
2374 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2376 if (DISPLAY_VER(dev_priv) >= 11 &&
2377 !intel_digital_port_connected(encoder))
2380 intel_hdmi_unset_edid(connector);
2382 if (intel_hdmi_set_edid(connector))
2383 status = connector_status_connected;
2386 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2388 if (status != connector_status_connected)
2389 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2392 * Make sure the refs for power wells enabled during detect are
2393 * dropped to avoid a new detect cycle triggered by HPD polling.
2395 intel_display_power_flush_work(dev_priv);
2401 intel_hdmi_force(struct drm_connector *connector)
2403 struct drm_i915_private *i915 = to_i915(connector->dev);
2405 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2406 connector->base.id, connector->name);
2408 intel_hdmi_unset_edid(connector);
2410 if (connector->status != connector_status_connected)
2413 intel_hdmi_set_edid(connector);
2416 static int intel_hdmi_get_modes(struct drm_connector *connector)
2420 edid = to_intel_connector(connector)->detect_edid;
2424 return intel_connector_update_modes(connector, edid);
2427 static struct i2c_adapter *
2428 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2430 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2431 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2433 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2436 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2438 struct drm_i915_private *i915 = to_i915(connector->dev);
2439 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2440 struct kobject *i2c_kobj = &adapter->dev.kobj;
2441 struct kobject *connector_kobj = &connector->kdev->kobj;
2444 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2446 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2449 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2451 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2452 struct kobject *i2c_kobj = &adapter->dev.kobj;
2453 struct kobject *connector_kobj = &connector->kdev->kobj;
2455 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2459 intel_hdmi_connector_register(struct drm_connector *connector)
2463 ret = intel_connector_register(connector);
2467 intel_hdmi_create_i2c_symlink(connector);
2472 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2474 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2476 cec_notifier_conn_unregister(n);
2478 intel_hdmi_remove_i2c_symlink(connector);
2479 intel_connector_unregister(connector);
2482 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2483 .detect = intel_hdmi_detect,
2484 .force = intel_hdmi_force,
2485 .fill_modes = drm_helper_probe_single_connector_modes,
2486 .atomic_get_property = intel_digital_connector_atomic_get_property,
2487 .atomic_set_property = intel_digital_connector_atomic_set_property,
2488 .late_register = intel_hdmi_connector_register,
2489 .early_unregister = intel_hdmi_connector_unregister,
2490 .destroy = intel_connector_destroy,
2491 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2492 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2495 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2496 .get_modes = intel_hdmi_get_modes,
2497 .mode_valid = intel_hdmi_mode_valid,
2498 .atomic_check = intel_digital_connector_atomic_check,
2502 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2504 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2506 intel_attach_force_audio_property(connector);
2507 intel_attach_broadcast_rgb_property(connector);
2508 intel_attach_aspect_ratio_property(connector);
2510 intel_attach_hdmi_colorspace_property(connector);
2511 drm_connector_attach_content_type_property(connector);
2513 if (DISPLAY_VER(dev_priv) >= 10)
2514 drm_connector_attach_hdr_output_metadata_property(connector);
2516 if (!HAS_GMCH(dev_priv))
2517 drm_connector_attach_max_bpc_property(connector, 8, 12);
2521 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2522 * @encoder: intel_encoder
2523 * @connector: drm_connector
2524 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2525 * or reset the high tmds clock ratio for scrambling
2526 * @scrambling: bool to Indicate if the function needs to set or reset
2529 * This function handles scrambling on HDMI 2.0 capable sinks.
2530 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2531 * it enables scrambling. This should be called before enabling the HDMI
2532 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2533 * detect a scrambled clock within 100 ms.
2536 * True on success, false on failure.
2538 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2539 struct drm_connector *connector,
2540 bool high_tmds_clock_ratio,
2543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2544 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2545 struct drm_scrambling *sink_scrambling =
2546 &connector->display_info.hdmi.scdc.scrambling;
2547 struct i2c_adapter *adapter =
2548 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2550 if (!sink_scrambling->supported)
2553 drm_dbg_kms(&dev_priv->drm,
2554 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2555 connector->base.id, connector->name,
2556 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2558 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2559 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2560 high_tmds_clock_ratio) &&
2561 drm_scdc_set_scrambling(adapter, scrambling);
2564 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2570 ddc_pin = GMBUS_PIN_DPB;
2573 ddc_pin = GMBUS_PIN_DPC;
2576 ddc_pin = GMBUS_PIN_DPD_CHV;
2580 ddc_pin = GMBUS_PIN_DPB;
2586 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2592 ddc_pin = GMBUS_PIN_1_BXT;
2595 ddc_pin = GMBUS_PIN_2_BXT;
2599 ddc_pin = GMBUS_PIN_1_BXT;
2605 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2612 ddc_pin = GMBUS_PIN_1_BXT;
2615 ddc_pin = GMBUS_PIN_2_BXT;
2618 ddc_pin = GMBUS_PIN_4_CNP;
2621 ddc_pin = GMBUS_PIN_3_BXT;
2625 ddc_pin = GMBUS_PIN_1_BXT;
2631 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2633 enum phy phy = intel_port_to_phy(dev_priv, port);
2635 if (intel_phy_is_combo(dev_priv, phy))
2636 return GMBUS_PIN_1_BXT + port;
2637 else if (intel_phy_is_tc(dev_priv, phy))
2638 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2640 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2641 return GMBUS_PIN_2_BXT;
2644 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2646 enum phy phy = intel_port_to_phy(dev_priv, port);
2651 ddc_pin = GMBUS_PIN_1_BXT;
2654 ddc_pin = GMBUS_PIN_2_BXT;
2657 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2661 ddc_pin = GMBUS_PIN_1_BXT;
2667 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2669 enum phy phy = intel_port_to_phy(dev_priv, port);
2671 WARN_ON(port == PORT_C);
2674 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2675 * final two outputs use type-c pins, even though they're actually
2676 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2679 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2680 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2682 return GMBUS_PIN_1_BXT + phy;
2685 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2687 enum phy phy = intel_port_to_phy(i915, port);
2689 drm_WARN_ON(&i915->drm, port == PORT_A);
2692 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2693 * final two outputs use type-c pins, even though they're actually
2694 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2697 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2698 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2700 return GMBUS_PIN_1_BXT + phy;
2703 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2705 return intel_port_to_phy(dev_priv, port) + 1;
2708 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2710 enum phy phy = intel_port_to_phy(dev_priv, port);
2712 WARN_ON(port == PORT_B || port == PORT_C);
2715 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2716 * except first combo output.
2719 return GMBUS_PIN_1_BXT;
2721 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2724 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2731 ddc_pin = GMBUS_PIN_DPB;
2734 ddc_pin = GMBUS_PIN_DPC;
2737 ddc_pin = GMBUS_PIN_DPD;
2741 ddc_pin = GMBUS_PIN_DPB;
2747 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2750 enum port port = encoder->port;
2753 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2755 drm_dbg_kms(&dev_priv->drm,
2756 "Using DDC pin 0x%x for port %c (VBT)\n",
2757 ddc_pin, port_name(port));
2761 if (IS_ALDERLAKE_S(dev_priv))
2762 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2763 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2764 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2765 else if (IS_ROCKETLAKE(dev_priv))
2766 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2767 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2768 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2769 else if (HAS_PCH_MCC(dev_priv))
2770 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2771 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2772 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2773 else if (HAS_PCH_CNP(dev_priv))
2774 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2775 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2776 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2777 else if (IS_CHERRYVIEW(dev_priv))
2778 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2780 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2782 drm_dbg_kms(&dev_priv->drm,
2783 "Using DDC pin 0x%x for port %c (platform default)\n",
2784 ddc_pin, port_name(port));
2789 void intel_infoframe_init(struct intel_digital_port *dig_port)
2791 struct drm_i915_private *dev_priv =
2792 to_i915(dig_port->base.base.dev);
2794 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2795 dig_port->write_infoframe = vlv_write_infoframe;
2796 dig_port->read_infoframe = vlv_read_infoframe;
2797 dig_port->set_infoframes = vlv_set_infoframes;
2798 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2799 } else if (IS_G4X(dev_priv)) {
2800 dig_port->write_infoframe = g4x_write_infoframe;
2801 dig_port->read_infoframe = g4x_read_infoframe;
2802 dig_port->set_infoframes = g4x_set_infoframes;
2803 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2804 } else if (HAS_DDI(dev_priv)) {
2805 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2806 dig_port->write_infoframe = lspcon_write_infoframe;
2807 dig_port->read_infoframe = lspcon_read_infoframe;
2808 dig_port->set_infoframes = lspcon_set_infoframes;
2809 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2811 dig_port->write_infoframe = hsw_write_infoframe;
2812 dig_port->read_infoframe = hsw_read_infoframe;
2813 dig_port->set_infoframes = hsw_set_infoframes;
2814 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2816 } else if (HAS_PCH_IBX(dev_priv)) {
2817 dig_port->write_infoframe = ibx_write_infoframe;
2818 dig_port->read_infoframe = ibx_read_infoframe;
2819 dig_port->set_infoframes = ibx_set_infoframes;
2820 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2822 dig_port->write_infoframe = cpt_write_infoframe;
2823 dig_port->read_infoframe = cpt_read_infoframe;
2824 dig_port->set_infoframes = cpt_set_infoframes;
2825 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2829 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2830 struct intel_connector *intel_connector)
2832 struct drm_connector *connector = &intel_connector->base;
2833 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2834 struct intel_encoder *intel_encoder = &dig_port->base;
2835 struct drm_device *dev = intel_encoder->base.dev;
2836 struct drm_i915_private *dev_priv = to_i915(dev);
2837 struct i2c_adapter *ddc;
2838 enum port port = intel_encoder->port;
2839 struct cec_connector_info conn_info;
2841 drm_dbg_kms(&dev_priv->drm,
2842 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2843 intel_encoder->base.base.id, intel_encoder->base.name);
2845 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2848 if (drm_WARN(dev, dig_port->max_lanes < 4,
2849 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2850 dig_port->max_lanes, intel_encoder->base.base.id,
2851 intel_encoder->base.name))
2854 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2855 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2857 drm_connector_init_with_ddc(dev, connector,
2858 &intel_hdmi_connector_funcs,
2859 DRM_MODE_CONNECTOR_HDMIA,
2861 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2863 connector->interlace_allowed = 1;
2864 connector->doublescan_allowed = 0;
2865 connector->stereo_allowed = 1;
2867 if (DISPLAY_VER(dev_priv) >= 10)
2868 connector->ycbcr_420_allowed = true;
2870 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2872 if (HAS_DDI(dev_priv))
2873 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2875 intel_connector->get_hw_state = intel_connector_get_hw_state;
2877 intel_hdmi_add_properties(intel_hdmi, connector);
2879 intel_connector_attach_encoder(intel_connector, intel_encoder);
2880 intel_hdmi->attached_connector = intel_connector;
2882 if (is_hdcp_supported(dev_priv, port)) {
2883 int ret = intel_hdcp_init(intel_connector, dig_port,
2884 &intel_hdmi_hdcp_shim);
2886 drm_dbg_kms(&dev_priv->drm,
2887 "HDCP init failed, skipping.\n");
2890 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2891 * 0xd. Failure to do so will result in spurious interrupts being
2892 * generated on the port when a cable is not attached.
2894 if (IS_G45(dev_priv)) {
2895 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2896 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2897 (temp & ~0xf) | 0xd);
2900 cec_fill_conn_info_from_drm(&conn_info, connector);
2902 intel_hdmi->cec_notifier =
2903 cec_notifier_conn_register(dev->dev, port_identifier(port),
2905 if (!intel_hdmi->cec_notifier)
2906 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2910 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
2911 * @vactive: Vactive of a display mode
2913 * @return: appropriate dsc slice height for a given mode.
2915 int intel_hdmi_dsc_get_slice_height(int vactive)
2920 * Slice Height determination : HDMI2.1 Section 7.7.5.2
2921 * Select smallest slice height >=96, that results in a valid PPS and
2922 * requires minimum padding lines required for final slice.
2924 * Assumption : Vactive is even.
2926 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
2927 if (vactive % slice_height == 0)
2928 return slice_height;
2934 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
2935 * and dsc decoder capabilities
2937 * @crtc_state: intel crtc_state
2938 * @src_max_slices: maximum slices supported by the DSC encoder
2939 * @src_max_slice_width: maximum slice width supported by DSC encoder
2940 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
2941 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
2943 * @return: num of dsc slices that can be supported by the dsc encoder
2947 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
2948 int src_max_slices, int src_max_slice_width,
2949 int hdmi_max_slices, int hdmi_throughput)
2951 /* Pixel rates in KPixels/sec */
2952 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000
2954 * Rates at which the source and sink are required to process pixels in each
2955 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
2957 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
2958 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
2960 /* Spec limits the slice width to 2720 pixels */
2961 #define MAX_HDMI_SLICE_WIDTH 2720
2963 int adjusted_clk_khz;
2966 int max_throughput; /* max clock freq. in khz per slice */
2967 int max_slice_width;
2969 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
2971 if (!hdmi_throughput)
2975 * Slice Width determination : HDMI2.1 Section 7.7.5.1
2976 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
2977 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
2978 * dividing adjusted clock value by 10.
2980 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
2981 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2987 * As per spec, the rate at which the source and the sink process
2988 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
2989 * This depends upon the pixel clock rate and output formats
2991 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
2992 * at max 340MHz, otherwise they can be processed at max 400MHz.
2995 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
2997 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
2998 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3000 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3003 * Taking into account the sink's capability for maximum
3004 * clock per slice (in MHz) as read from HF-VSDB.
3006 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3008 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3009 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3012 * Keep on increasing the num of slices/line, starting from min_slices
3013 * per line till we get such a number, for which the slice_width is
3014 * just less than max_slice_width. The slices/line selected should be
3015 * less than or equal to the max horizontal slices that the combination
3016 * of PCON encoder and HDMI decoder can support.
3018 slice_width = max_slice_width;
3021 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3023 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3025 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3027 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3029 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3031 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3036 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3037 if (slice_width >= max_slice_width)
3038 min_slices = target_slices + 1;
3039 } while (slice_width >= max_slice_width);
3041 return target_slices;
3045 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3046 * source and sink capabilities.
3048 * @src_fraction_bpp: fractional bpp supported by the source
3049 * @slice_width: dsc slice width supported by the source and sink
3050 * @num_slices: num of slices supported by the source and sink
3051 * @output_format: video output format
3052 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3053 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3055 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3058 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3059 int output_format, bool hdmi_all_bpp,
3060 int hdmi_max_chunk_bytes)
3062 int max_dsc_bpp, min_dsc_bpp;
3064 bool bpp_found = false;
3065 int bpp_decrement_x16;
3070 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3071 * Start with the max bpp and keep on decrementing with
3072 * fractional bpp, if supported by PCON DSC encoder
3074 * for each bpp we check if no of bytes can be supported by HDMI sink
3077 /* Assuming: bpc as 8*/
3078 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3080 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3081 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3082 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3084 max_dsc_bpp = 3 * 8; /* 3*bpc */
3086 /* Assuming 4:2:2 encoding */
3088 max_dsc_bpp = 2 * 8; /* 2*bpc */
3092 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3093 * Section 7.7.34 : Source shall not enable compressed Video
3094 * Transport with bpp_target settings above 12 bpp unless
3095 * DSC_all_bpp is set to 1.
3098 max_dsc_bpp = min(max_dsc_bpp, 12);
3101 * The Sink has a limit of compressed data in bytes for a scanline,
3102 * as described in max_chunk_bytes field in HFVSDB block of edid.
3103 * The no. of bytes depend on the target bits per pixel that the
3104 * source configures. So we start with the max_bpp and calculate
3105 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3106 * till we get the target_chunk_bytes just less than what the sink's
3107 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3109 * The decrement is according to the fractional support from PCON DSC
3110 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3112 * bpp_target_x16 = bpp_target * 16
3113 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3114 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3117 bpp_target = max_dsc_bpp;
3119 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3120 if (!src_fractional_bpp)
3121 src_fractional_bpp = 1;
3122 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3123 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3125 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3128 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3129 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3130 if (target_bytes <= hdmi_max_chunk_bytes) {
3134 bpp_target_x16 -= bpp_decrement_x16;
3137 return bpp_target_x16;