drivers/gpu/drm/i915/display/intel_gmbus.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29
  30 #include <linux/export.h>
  31 #include <linux/i2c-algo-bit.h>
  32 #include <linux/i2c.h>
  33
  34 #include <drm/drm_hdcp.h>
  35
  36 #include "i915_drv.h"
  37 #include "intel_display_types.h"
  38 #include "intel_gmbus.h"
  39
  40 struct gmbus_pin {
  41         const char *name;
  42         enum i915_gpio gpio;
  43 };
  44
  45 /* Map gmbus pin pairs to names and registers. */
  46 static const struct gmbus_pin gmbus_pins[] = {
  47         [GMBUS_PIN_SSC] = { "ssc", GPIOB },
  48         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  49         [GMBUS_PIN_PANEL] = { "panel", GPIOC },
  50         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  51         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  52         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  53 };
  54
  55 static const struct gmbus_pin gmbus_pins_bdw[] = {
  56         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  57         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  58         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  59         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  60 };
  61
  62 static const struct gmbus_pin gmbus_pins_skl[] = {
  63         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  64         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  65         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  66 };
  67
  68 static const struct gmbus_pin gmbus_pins_bxt[] = {
  69         [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
  70         [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
  71         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
  72 };
  73
  74 static const struct gmbus_pin gmbus_pins_cnp[] = {
  75         [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
  76         [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
  77         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
  78         [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
  79 };
  80
  81 static const struct gmbus_pin gmbus_pins_icp[] = {
  82         [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
  83         [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
  84         [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
  85         [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
  86         [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
  87         [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
  88         [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
  89         [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
  90         [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
  91 };
  92
  93 static const struct gmbus_pin gmbus_pins_dg1[] = {
  94         [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
  95         [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
  96         [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
  97         [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
  98 };
  99
 100 /* pin is expected to be valid */
 101 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 102                                              unsigned int pin)
 103 {
 104         if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 105                 return &gmbus_pins_dg1[pin];
 106         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 107                 return &gmbus_pins_icp[pin];
 108         else if (HAS_PCH_CNP(dev_priv))
 109                 return &gmbus_pins_cnp[pin];
 110         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 111                 return &gmbus_pins_bxt[pin];
 112         else if (DISPLAY_VER(dev_priv) == 9)
 113                 return &gmbus_pins_skl[pin];
 114         else if (IS_BROADWELL(dev_priv))
 115                 return &gmbus_pins_bdw[pin];
 116         else
 117                 return &gmbus_pins[pin];
 118 }
 119
 120 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 121                               unsigned int pin)
 122 {
 123         unsigned int size;
 124
 125         if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
 126                 size = ARRAY_SIZE(gmbus_pins_dg1);
 127         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 128                 size = ARRAY_SIZE(gmbus_pins_icp);
 129         else if (HAS_PCH_CNP(dev_priv))
 130                 size = ARRAY_SIZE(gmbus_pins_cnp);
 131         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 132                 size = ARRAY_SIZE(gmbus_pins_bxt);
 133         else if (DISPLAY_VER(dev_priv) == 9)
 134                 size = ARRAY_SIZE(gmbus_pins_skl);
 135         else if (IS_BROADWELL(dev_priv))
 136                 size = ARRAY_SIZE(gmbus_pins_bdw);
 137         else
 138                 size = ARRAY_SIZE(gmbus_pins);
 139
 140         return pin < size && get_gmbus_pin(dev_priv, pin)->name;
 141 }
 142
 143 /* Intel GPIO access functions */
 144
 145 #define I2C_RISEFALL_TIME 10
 146
 147 static inline struct intel_gmbus *
 148 to_intel_gmbus(struct i2c_adapter *i2c)
 149 {
 150         return container_of(i2c, struct intel_gmbus, adapter);
 151 }
 152
 153 void
 154 intel_gmbus_reset(struct drm_i915_private *dev_priv)
 155 {
 156         intel_de_write(dev_priv, GMBUS0, 0);
 157         intel_de_write(dev_priv, GMBUS4, 0);
 158 }
 159
 160 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 161                                    bool enable)
 162 {
 163         u32 val;
 164
 165         /* When using bit bashing for I2C, this bit needs to be set to 1 */
 166         val = intel_de_read(dev_priv, DSPCLK_GATE_D);
 167         if (!enable)
 168                 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
 169         else
 170                 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
 171         intel_de_write(dev_priv, DSPCLK_GATE_D, val);
 172 }
 173
 174 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 175                                    bool enable)
 176 {
 177         u32 val;
 178
 179         val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);
 180         if (!enable)
 181                 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
 182         else
 183                 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
 184         intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);
 185 }
 186
 187 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
 188                                    bool enable)
 189 {
 190         u32 val;
 191
 192         val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);
 193         if (!enable)
 194                 val |= BXT_GMBUS_GATING_DIS;
 195         else
 196                 val &= ~BXT_GMBUS_GATING_DIS;
 197         intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);
 198 }
 199
 200 static u32 get_reserved(struct intel_gmbus *bus)
 201 {
 202         struct drm_i915_private *i915 = bus->dev_priv;
 203         struct intel_uncore *uncore = &i915->uncore;
 204         u32 reserved = 0;
 205
 206         /* On most chips, these bits must be preserved in software. */
 207         if (!IS_I830(i915) && !IS_I845G(i915))
 208                 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
 209                            (GPIO_DATA_PULLUP_DISABLE |
 210                             GPIO_CLOCK_PULLUP_DISABLE);
 211
 212         return reserved;
 213 }
 214
 215 static int get_clock(void *data)
 216 {
 217         struct intel_gmbus *bus = data;
 218         struct intel_uncore *uncore = &bus->dev_priv->uncore;
 219         u32 reserved = get_reserved(bus);
 220
 221         intel_uncore_write_notrace(uncore,
 222                                    bus->gpio_reg,
 223                                    reserved | GPIO_CLOCK_DIR_MASK);
 224         intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
 225
 226         return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
 227                 GPIO_CLOCK_VAL_IN) != 0;
 228 }
 229
 230 static int get_data(void *data)
 231 {
 232         struct intel_gmbus *bus = data;
 233         struct intel_uncore *uncore = &bus->dev_priv->uncore;
 234         u32 reserved = get_reserved(bus);
 235
 236         intel_uncore_write_notrace(uncore,
 237                                    bus->gpio_reg,
 238                                    reserved | GPIO_DATA_DIR_MASK);
 239         intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
 240
 241         return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
 242                 GPIO_DATA_VAL_IN) != 0;
 243 }
 244
 245 static void set_clock(void *data, int state_high)
 246 {
 247         struct intel_gmbus *bus = data;
 248         struct intel_uncore *uncore = &bus->dev_priv->uncore;
 249         u32 reserved = get_reserved(bus);
 250         u32 clock_bits;
 251
 252         if (state_high)
 253                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 254         else
 255                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 256                              GPIO_CLOCK_VAL_MASK;
 257
 258         intel_uncore_write_notrace(uncore,
 259                                    bus->gpio_reg,
 260                                    reserved | clock_bits);
 261         intel_uncore_posting_read(uncore, bus->gpio_reg);
 262 }
 263
 264 static void set_data(void *data, int state_high)
 265 {
 266         struct intel_gmbus *bus = data;
 267         struct intel_uncore *uncore = &bus->dev_priv->uncore;
 268         u32 reserved = get_reserved(bus);
 269         u32 data_bits;
 270
 271         if (state_high)
 272                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 273         else
 274                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 275                         GPIO_DATA_VAL_MASK;
 276
 277         intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
 278         intel_uncore_posting_read(uncore, bus->gpio_reg);
 279 }
 280
 281 static int
 282 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 283 {
 284         struct intel_gmbus *bus = container_of(adapter,
 285                                                struct intel_gmbus,
 286                                                adapter);
 287         struct drm_i915_private *dev_priv = bus->dev_priv;
 288
 289         intel_gmbus_reset(dev_priv);
 290
 291         if (IS_PINEVIEW(dev_priv))
 292                 pnv_gmbus_clock_gating(dev_priv, false);
 293
 294         set_data(bus, 1);
 295         set_clock(bus, 1);
 296         udelay(I2C_RISEFALL_TIME);
 297         return 0;
 298 }
 299
 300 static void
 301 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 302 {
 303         struct intel_gmbus *bus = container_of(adapter,
 304                                                struct intel_gmbus,
 305                                                adapter);
 306         struct drm_i915_private *dev_priv = bus->dev_priv;
 307
 308         set_data(bus, 1);
 309         set_clock(bus, 1);
 310
 311         if (IS_PINEVIEW(dev_priv))
 312                 pnv_gmbus_clock_gating(dev_priv, true);
 313 }
 314
 315 static void
 316 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
 317 {
 318         struct drm_i915_private *dev_priv = bus->dev_priv;
 319         struct i2c_algo_bit_data *algo;
 320
 321         algo = &bus->bit_algo;
 322
 323         bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
 324         bus->adapter.algo_data = algo;
 325         algo->setsda = set_data;
 326         algo->setscl = set_clock;
 327         algo->getsda = get_data;
 328         algo->getscl = get_clock;
 329         algo->pre_xfer = intel_gpio_pre_xfer;
 330         algo->post_xfer = intel_gpio_post_xfer;
 331         algo->udelay = I2C_RISEFALL_TIME;
 332         algo->timeout = usecs_to_jiffies(2200);
 333         algo->data = bus;
 334 }
 335
 336 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
 337 {
 338         DEFINE_WAIT(wait);
 339         u32 gmbus2;
 340         int ret;
 341
 342         /* Important: The hw handles only the first bit, so set only one! Since
 343          * we also need to check for NAKs besides the hw ready/idle signal, we
 344          * need to wake up periodically and check that ourselves.
 345          */
 346         if (!HAS_GMBUS_IRQ(dev_priv))
 347                 irq_en = 0;
 348
 349         add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 350         intel_de_write_fw(dev_priv, GMBUS4, irq_en);
 351
 352         status |= GMBUS_SATOER;
 353         ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
 354                           2);
 355         if (ret)
 356                 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,
 357                                50);
 358
 359         intel_de_write_fw(dev_priv, GMBUS4, 0);
 360         remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 361
 362         if (gmbus2 & GMBUS_SATOER)
 363                 return -ENXIO;
 364
 365         return ret;
 366 }
 367
 368 static int
 369 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 370 {
 371         DEFINE_WAIT(wait);
 372         u32 irq_enable;
 373         int ret;
 374
 375         /* Important: The hw handles only the first bit, so set only one! */
 376         irq_enable = 0;
 377         if (HAS_GMBUS_IRQ(dev_priv))
 378                 irq_enable = GMBUS_IDLE_EN;
 379
 380         add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 381         intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
 382
 383         ret = intel_wait_for_register_fw(&dev_priv->uncore,
 384                                          GMBUS2, GMBUS_ACTIVE, 0,
 385                                          10);
 386
 387         intel_de_write_fw(dev_priv, GMBUS4, 0);
 388         remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
 389
 390         return ret;
 391 }
 392
 393 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
 394 {
 395         return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
 396                GMBUS_BYTE_COUNT_MAX;
 397 }
 398
 399 static int
 400 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
 401                       unsigned short addr, u8 *buf, unsigned int len,
 402                       u32 gmbus0_reg, u32 gmbus1_index)
 403 {
 404         unsigned int size = len;
 405         bool burst_read = len > gmbus_max_xfer_size(dev_priv);
 406         bool extra_byte_added = false;
 407
 408         if (burst_read) {
 409                 /*
 410                  * As per HW Spec, for 512Bytes need to read extra Byte and
 411                  * Ignore the extra byte read.
 412                  */
 413                 if (len == 512) {
 414                         extra_byte_added = true;
 415                         len++;
 416                 }
 417                 size = len % 256 + 256;
 418                 intel_de_write_fw(dev_priv, GMBUS0,
 419                                   gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
 420         }
 421
 422         intel_de_write_fw(dev_priv, GMBUS1,
 423                           gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 424         while (len) {
 425                 int ret;
 426                 u32 val, loop = 0;
 427
 428                 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
 429                 if (ret)
 430                         return ret;
 431
 432                 val = intel_de_read_fw(dev_priv, GMBUS3);
 433                 do {
 434                         if (extra_byte_added && len == 1)
 435                                 break;
 436
 437                         *buf++ = val & 0xff;
 438                         val >>= 8;
 439                 } while (--len && ++loop < 4);
 440
 441                 if (burst_read && len == size - 4)
 442                         /* Reset the override bit */
 443                         intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);
 444         }
 445
 446         return 0;
 447 }
 448
 449 /*
 450  * HW spec says that 512Bytes in Burst read need special treatment.
 451  * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
 452  * an I2C slave, which supports such a lengthy burst read too for experiments.
 453  *
 454  * So until things get clarified on HW support, to avoid the burst read length
 455  * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
 456  */
 457 #define INTEL_GMBUS_BURST_READ_MAX_LEN          767U
 458
 459 static int
 460 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 461                 u32 gmbus0_reg, u32 gmbus1_index)
 462 {
 463         u8 *buf = msg->buf;
 464         unsigned int rx_size = msg->len;
 465         unsigned int len;
 466         int ret;
 467
 468         do {
 469                 if (HAS_GMBUS_BURST_READ(dev_priv))
 470                         len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
 471                 else
 472                         len = min(rx_size, gmbus_max_xfer_size(dev_priv));
 473
 474                 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
 475                                             gmbus0_reg, gmbus1_index);
 476                 if (ret)
 477                         return ret;
 478
 479                 rx_size -= len;
 480                 buf += len;
 481         } while (rx_size != 0);
 482
 483         return 0;
 484 }
 485
 486 static int
 487 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
 488                        unsigned short addr, u8 *buf, unsigned int len,
 489                        u32 gmbus1_index)
 490 {
 491         unsigned int chunk_size = len;
 492         u32 val, loop;
 493
 494         val = loop = 0;
 495         while (len && loop < 4) {
 496                 val |= *buf++ << (8 * loop++);
 497                 len -= 1;
 498         }
 499
 500         intel_de_write_fw(dev_priv, GMBUS3, val);
 501         intel_de_write_fw(dev_priv, GMBUS1,
 502                           gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 503         while (len) {
 504                 int ret;
 505
 506                 val = loop = 0;
 507                 do {
 508                         val |= *buf++ << (8 * loop);
 509                 } while (--len && ++loop < 4);
 510
 511                 intel_de_write_fw(dev_priv, GMBUS3, val);
 512
 513                 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
 514                 if (ret)
 515                         return ret;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static int
 522 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 523                  u32 gmbus1_index)
 524 {
 525         u8 *buf = msg->buf;
 526         unsigned int tx_size = msg->len;
 527         unsigned int len;
 528         int ret;
 529
 530         do {
 531                 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
 532
 533                 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
 534                                              gmbus1_index);
 535                 if (ret)
 536                         return ret;
 537
 538                 buf += len;
 539                 tx_size -= len;
 540         } while (tx_size != 0);
 541
 542         return 0;
 543 }
 544
 545 /*
 546  * The gmbus controller can combine a 1 or 2 byte write with another read/write
 547  * that immediately follows it by using an "INDEX" cycle.
 548  */
 549 static bool
 550 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
 551 {
 552         return (i + 1 < num &&
 553                 msgs[i].addr == msgs[i + 1].addr &&
 554                 !(msgs[i].flags & I2C_M_RD) &&
 555                 (msgs[i].len == 1 || msgs[i].len == 2) &&
 556                 msgs[i + 1].len > 0);
 557 }
 558
 559 static int
 560 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
 561                  u32 gmbus0_reg)
 562 {
 563         u32 gmbus1_index = 0;
 564         u32 gmbus5 = 0;
 565         int ret;
 566
 567         if (msgs[0].len == 2)
 568                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 569                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 570         if (msgs[0].len == 1)
 571                 gmbus1_index = GMBUS_CYCLE_INDEX |
 572                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 573
 574         /* GMBUS5 holds 16-bit index */
 575         if (gmbus5)
 576                 intel_de_write_fw(dev_priv, GMBUS5, gmbus5);
 577
 578         if (msgs[1].flags & I2C_M_RD)
 579                 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
 580                                       gmbus1_index);
 581         else
 582                 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
 583
 584         /* Clear GMBUS5 after each index transfer */
 585         if (gmbus5)
 586                 intel_de_write_fw(dev_priv, GMBUS5, 0);
 587
 588         return ret;
 589 }
 590
 591 static int
 592 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
 593               u32 gmbus0_source)
 594 {
 595         struct intel_gmbus *bus = container_of(adapter,
 596                                                struct intel_gmbus,
 597                                                adapter);
 598         struct drm_i915_private *dev_priv = bus->dev_priv;
 599         int i = 0, inc, try = 0;
 600         int ret = 0;
 601
 602         /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
 603         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 604                 bxt_gmbus_clock_gating(dev_priv, false);
 605         else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
 606                 pch_gmbus_clock_gating(dev_priv, false);
 607
 608 retry:
 609         intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);
 610
 611         for (; i < num; i += inc) {
 612                 inc = 1;
 613                 if (gmbus_is_index_xfer(msgs, i, num)) {
 614                         ret = gmbus_index_xfer(dev_priv, &msgs[i],
 615                                                gmbus0_source | bus->reg0);
 616                         inc = 2; /* an index transmission is two msgs */
 617                 } else if (msgs[i].flags & I2C_M_RD) {
 618                         ret = gmbus_xfer_read(dev_priv, &msgs[i],
 619                                               gmbus0_source | bus->reg0, 0);
 620                 } else {
 621                         ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
 622                 }
 623
 624                 if (!ret)
 625                         ret = gmbus_wait(dev_priv,
 626                                          GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
 627                 if (ret == -ETIMEDOUT)
 628                         goto timeout;
 629                 else if (ret)
 630                         goto clear_err;
 631         }
 632
 633         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 634          * a STOP on the very first cycle. To simplify the code we
 635          * unconditionally generate the STOP condition with an additional gmbus
 636          * cycle. */
 637         intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 638
 639         /* Mark the GMBUS interface as disabled after waiting for idle.
 640          * We will re-enable it at the start of the next xfer,
 641          * till then let it sleep.
 642          */
 643         if (gmbus_wait_idle(dev_priv)) {
 644                 drm_dbg_kms(&dev_priv->drm,
 645                             "GMBUS [%s] timed out waiting for idle\n",
 646                             adapter->name);
 647                 ret = -ETIMEDOUT;
 648         }
 649         intel_de_write_fw(dev_priv, GMBUS0, 0);
 650         ret = ret ?: i;
 651         goto out;
 652
 653 clear_err:
 654         /*
 655          * Wait for bus to IDLE before clearing NAK.
 656          * If we clear the NAK while bus is still active, then it will stay
 657          * active and the next transaction may fail.
 658          *
 659          * If no ACK is received during the address phase of a transaction, the
 660          * adapter must report -ENXIO. It is not clear what to return if no ACK
 661          * is received at other times. But we have to be careful to not return
 662          * spurious -ENXIO because that will prevent i2c and drm edid functions
 663          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 664          * timing out seems to happen when there _is_ a ddc chip present, but
 665          * it's slow responding and only answers on the 2nd retry.
 666          */
 667         ret = -ENXIO;
 668         if (gmbus_wait_idle(dev_priv)) {
 669                 drm_dbg_kms(&dev_priv->drm,
 670                             "GMBUS [%s] timed out after NAK\n",
 671                             adapter->name);
 672                 ret = -ETIMEDOUT;
 673         }
 674
 675         /* Toggle the Software Clear Interrupt bit. This has the effect
 676          * of resetting the GMBUS controller and so clearing the
 677          * BUS_ERROR raised by the slave's NAK.
 678          */
 679         intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);
 680         intel_de_write_fw(dev_priv, GMBUS1, 0);
 681         intel_de_write_fw(dev_priv, GMBUS0, 0);
 682
 683         drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 684                     adapter->name, msgs[i].addr,
 685                     (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 686
 687         /*
 688          * Passive adapters sometimes NAK the first probe. Retry the first
 689          * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
 690          * has retries internally. See also the retry loop in
 691          * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
 692          */
 693         if (ret == -ENXIO && i == 0 && try++ == 0) {
 694                 drm_dbg_kms(&dev_priv->drm,
 695                             "GMBUS [%s] NAK on first message, retry\n",
 696                             adapter->name);
 697                 goto retry;
 698         }
 699
 700         goto out;
 701
 702 timeout:
 703         drm_dbg_kms(&dev_priv->drm,
 704                     "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 705                     bus->adapter.name, bus->reg0 & 0xff);
 706         intel_de_write_fw(dev_priv, GMBUS0, 0);
 707
 708         /*
 709          * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
 710          * instead. Use EAGAIN to have i2c core retry.
 711          */
 712         ret = -EAGAIN;
 713
 714 out:
 715         /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
 716         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 717                 bxt_gmbus_clock_gating(dev_priv, true);
 718         else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
 719                 pch_gmbus_clock_gating(dev_priv, true);
 720
 721         return ret;
 722 }
 723
 724 static int
 725 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 726 {
 727         struct intel_gmbus *bus =
 728                 container_of(adapter, struct intel_gmbus, adapter);
 729         struct drm_i915_private *dev_priv = bus->dev_priv;
 730         intel_wakeref_t wakeref;
 731         int ret;
 732
 733         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 734
 735         if (bus->force_bit) {
 736                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 737                 if (ret < 0)
 738                         bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
 739         } else {
 740                 ret = do_gmbus_xfer(adapter, msgs, num, 0);
 741                 if (ret == -EAGAIN)
 742                         bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
 743         }
 744
 745         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
 746
 747         return ret;
 748 }
 749
 750 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
 751 {
 752         struct intel_gmbus *bus =
 753                 container_of(adapter, struct intel_gmbus, adapter);
 754         struct drm_i915_private *dev_priv = bus->dev_priv;
 755         u8 cmd = DRM_HDCP_DDC_AKSV;
 756         u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
 757         struct i2c_msg msgs[] = {
 758                 {
 759                         .addr = DRM_HDCP_DDC_ADDR,
 760                         .flags = 0,
 761                         .len = sizeof(cmd),
 762                         .buf = &cmd,
 763                 },
 764                 {
 765                         .addr = DRM_HDCP_DDC_ADDR,
 766                         .flags = 0,
 767                         .len = sizeof(buf),
 768                         .buf = buf,
 769                 }
 770         };
 771         intel_wakeref_t wakeref;
 772         int ret;
 773
 774         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
 775         mutex_lock(&dev_priv->gmbus_mutex);
 776
 777         /*
 778          * In order to output Aksv to the receiver, use an indexed write to
 779          * pass the i2c command, and tell GMBUS to use the HW-provided value
 780          * instead of sourcing GMBUS3 for the data.
 781          */
 782         ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
 783
 784         mutex_unlock(&dev_priv->gmbus_mutex);
 785         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
 786
 787         return ret;
 788 }
 789
 790 static u32 gmbus_func(struct i2c_adapter *adapter)
 791 {
 792         return i2c_bit_algo.functionality(adapter) &
 793                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 794                 /* I2C_FUNC_10BIT_ADDR | */
 795                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 796                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 797 }
 798
 799 static const struct i2c_algorithm gmbus_algorithm = {
 800         .master_xfer    = gmbus_xfer,
 801         .functionality  = gmbus_func
 802 };
 803
 804 static void gmbus_lock_bus(struct i2c_adapter *adapter,
 805                            unsigned int flags)
 806 {
 807         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 808         struct drm_i915_private *dev_priv = bus->dev_priv;
 809
 810         mutex_lock(&dev_priv->gmbus_mutex);
 811 }
 812
 813 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
 814                              unsigned int flags)
 815 {
 816         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 817         struct drm_i915_private *dev_priv = bus->dev_priv;
 818
 819         return mutex_trylock(&dev_priv->gmbus_mutex);
 820 }
 821
 822 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
 823                              unsigned int flags)
 824 {
 825         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 826         struct drm_i915_private *dev_priv = bus->dev_priv;
 827
 828         mutex_unlock(&dev_priv->gmbus_mutex);
 829 }
 830
 831 static const struct i2c_lock_operations gmbus_lock_ops = {
 832         .lock_bus =    gmbus_lock_bus,
 833         .trylock_bus = gmbus_trylock_bus,
 834         .unlock_bus =  gmbus_unlock_bus,
 835 };
 836
 837 /**
 838  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 839  * @dev_priv: i915 device private
 840  */
 841 int intel_gmbus_setup(struct drm_i915_private *dev_priv)
 842 {
 843         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 844         struct intel_gmbus *bus;
 845         unsigned int pin;
 846         int ret;
 847
 848         if (!HAS_DISPLAY(dev_priv))
 849                 return 0;
 850
 851         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 852                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 853         else if (!HAS_GMCH(dev_priv))
 854                 /*
 855                  * Broxton uses the same PCH offsets for South Display Engine,
 856                  * even though it doesn't have a PCH.
 857                  */
 858                 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
 859
 860         mutex_init(&dev_priv->gmbus_mutex);
 861         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
 862
 863         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 864                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 865                         continue;
 866
 867                 bus = &dev_priv->gmbus[pin];
 868
 869                 bus->adapter.owner = THIS_MODULE;
 870                 bus->adapter.class = I2C_CLASS_DDC;
 871                 snprintf(bus->adapter.name,
 872                          sizeof(bus->adapter.name),
 873                          "i915 gmbus %s",
 874                          get_gmbus_pin(dev_priv, pin)->name);
 875
 876                 bus->adapter.dev.parent = &pdev->dev;
 877                 bus->dev_priv = dev_priv;
 878
 879                 bus->adapter.algo = &gmbus_algorithm;
 880                 bus->adapter.lock_ops = &gmbus_lock_ops;
 881
 882                 /*
 883                  * We wish to retry with bit banging
 884                  * after a timed out GMBUS attempt.
 885                  */
 886                 bus->adapter.retries = 1;
 887
 888                 /* By default use a conservative clock rate */
 889                 bus->reg0 = pin | GMBUS_RATE_100KHZ;
 890
 891                 /* gmbus seems to be broken on i830 */
 892                 if (IS_I830(dev_priv))
 893                         bus->force_bit = 1;
 894
 895                 intel_gpio_setup(bus, pin);
 896
 897                 ret = i2c_add_adapter(&bus->adapter);
 898                 if (ret)
 899                         goto err;
 900         }
 901
 902         intel_gmbus_reset(dev_priv);
 903
 904         return 0;
 905
 906 err:
 907         while (pin--) {
 908                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 909                         continue;
 910
 911                 bus = &dev_priv->gmbus[pin];
 912                 i2c_del_adapter(&bus->adapter);
 913         }
 914         return ret;
 915 }
 916
 917 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 918                                             unsigned int pin)
 919 {
 920         if (drm_WARN_ON(&dev_priv->drm,
 921                         !intel_gmbus_is_valid_pin(dev_priv, pin)))
 922                 return NULL;
 923
 924         return &dev_priv->gmbus[pin].adapter;
 925 }
 926
 927 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 928 {
 929         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 930
 931         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 932 }
 933
 934 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 935 {
 936         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 937         struct drm_i915_private *dev_priv = bus->dev_priv;
 938
 939         mutex_lock(&dev_priv->gmbus_mutex);
 940
 941         bus->force_bit += force_bit ? 1 : -1;
 942         drm_dbg_kms(&dev_priv->drm,
 943                     "%sabling bit-banging on %s. force bit now %d\n",
 944                     force_bit ? "en" : "dis", adapter->name,
 945                     bus->force_bit);
 946
 947         mutex_unlock(&dev_priv->gmbus_mutex);
 948 }
 949
 950 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
 951 {
 952         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 953
 954         return bus->force_bit;
 955 }
 956
 957 void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
 958 {
 959         struct intel_gmbus *bus;
 960         unsigned int pin;
 961
 962         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
 963                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
 964                         continue;
 965
 966                 bus = &dev_priv->gmbus[pin];
 967                 i2c_del_adapter(&bus->adapter);
 968         }
 969 }