drivers/gpu/drm/i915/display/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <drm/drm_fourcc.h>
  42
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "i915_vgpu.h"
  46 #include "intel_display_types.h"
  47 #include "intel_fbc.h"
  48 #include "intel_frontbuffer.h"
  49
  50 /*
  51  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  52  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  53  * origin so the x and y offsets can actually fit the registers. As a
  54  * consequence, the fence doesn't really start exactly at the display plane
  55  * address we program because it starts at the real start of the buffer, so we
  56  * have to take this into consideration here.
  57  */
  58 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  59 {
  60         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  61 }
  62
  63 /*
  64  * For SKL+, the plane source size used by the hardware is based on the value we
  65  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  66  * we wrote to PIPESRC.
  67  */
  68 static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
  69                                             int *width, int *height)
  70 {
  71         if (width)
  72                 *width = cache->plane.src_w;
  73         if (height)
  74                 *height = cache->plane.src_h;
  75 }
  76
  77 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  78                                         const struct intel_fbc_state_cache *cache)
  79 {
  80         int lines;
  81
  82         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  83         if (IS_GEN(dev_priv, 7))
  84                 lines = min(lines, 2048);
  85         else if (INTEL_GEN(dev_priv) >= 8)
  86                 lines = min(lines, 2560);
  87
  88         /* Hardware needs the full buffer stride, not just the active area. */
  89         return lines * cache->fb.stride;
  90 }
  91
  92 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  93 {
  94         u32 fbc_ctl;
  95
  96         /* Disable compression */
  97         fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
  98         if ((fbc_ctl & FBC_CTL_EN) == 0)
  99                 return;
 100
 101         fbc_ctl &= ~FBC_CTL_EN;
 102         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
 103
 104         /* Wait for compressing bit to clear */
 105         if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
 106                                     FBC_STAT_COMPRESSING, 10)) {
 107                 DRM_DEBUG_KMS("FBC idle timed out\n");
 108                 return;
 109         }
 110 }
 111
 112 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 113 {
 114         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 115         int cfb_pitch;
 116         int i;
 117         u32 fbc_ctl;
 118
 119         /* Note: fbc.threshold == 1 for i8xx */
 120         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 121         if (params->fb.stride < cfb_pitch)
 122                 cfb_pitch = params->fb.stride;
 123
 124         /* FBC_CTL wants 32B or 64B units */
 125         if (IS_GEN(dev_priv, 2))
 126                 cfb_pitch = (cfb_pitch / 32) - 1;
 127         else
 128                 cfb_pitch = (cfb_pitch / 64) - 1;
 129
 130         /* Clear old tags */
 131         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 132                 intel_de_write(dev_priv, FBC_TAG(i), 0);
 133
 134         if (IS_GEN(dev_priv, 4)) {
 135                 u32 fbc_ctl2;
 136
 137                 /* Set it up... */
 138                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
 139                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 140                 if (params->fence_id >= 0)
 141                         fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 142                 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
 143                 intel_de_write(dev_priv, FBC_FENCE_OFF,
 144                                params->crtc.fence_y_offset);
 145         }
 146
 147         /* enable it... */
 148         fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
 149         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 150         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 151         if (IS_I945GM(dev_priv))
 152                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 153         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 154         if (params->fence_id >= 0)
 155                 fbc_ctl |= params->fence_id;
 156         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
 157 }
 158
 159 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 160 {
 161         return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
 162 }
 163
 164 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 165 {
 166         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 167         u32 dpfc_ctl;
 168
 169         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 170         if (params->fb.format->cpp[0] == 2)
 171                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 172         else
 173                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 174
 175         if (params->fence_id >= 0) {
 176                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
 177                 intel_de_write(dev_priv, DPFC_FENCE_YOFF,
 178                                params->crtc.fence_y_offset);
 179         } else {
 180                 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
 181         }
 182
 183         /* enable it... */
 184         intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 185 }
 186
 187 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 188 {
 189         u32 dpfc_ctl;
 190
 191         /* Disable compression */
 192         dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL);
 193         if (dpfc_ctl & DPFC_CTL_EN) {
 194                 dpfc_ctl &= ~DPFC_CTL_EN;
 195                 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl);
 196         }
 197 }
 198
 199 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 200 {
 201         return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
 202 }
 203
 204 /* This function forces a CFB recompression through the nuke operation. */
 205 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 206 {
 207         struct intel_fbc *fbc = &dev_priv->fbc;
 208
 209         trace_intel_fbc_nuke(fbc->crtc);
 210
 211         intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
 212         intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
 213 }
 214
 215 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 216 {
 217         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 218         u32 dpfc_ctl;
 219         int threshold = dev_priv->fbc.threshold;
 220
 221         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 222         if (params->fb.format->cpp[0] == 2)
 223                 threshold++;
 224
 225         switch (threshold) {
 226         case 4:
 227         case 3:
 228                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 229                 break;
 230         case 2:
 231                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 232                 break;
 233         case 1:
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235                 break;
 236         }
 237
 238         if (params->fence_id >= 0) {
 239                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 240                 if (IS_GEN(dev_priv, 5))
 241                         dpfc_ctl |= params->fence_id;
 242                 if (IS_GEN(dev_priv, 6)) {
 243                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 244                                        SNB_CPU_FENCE_ENABLE | params->fence_id);
 245                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 246                                        params->crtc.fence_y_offset);
 247                 }
 248         } else {
 249                 if (IS_GEN(dev_priv, 6)) {
 250                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 251                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 252                 }
 253         }
 254
 255         intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
 256                        params->crtc.fence_y_offset);
 257         /* enable it... */
 258         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 259
 260         intel_fbc_recompress(dev_priv);
 261 }
 262
 263 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 264 {
 265         u32 dpfc_ctl;
 266
 267         /* Disable compression */
 268         dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
 269         if (dpfc_ctl & DPFC_CTL_EN) {
 270                 dpfc_ctl &= ~DPFC_CTL_EN;
 271                 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl);
 272         }
 273 }
 274
 275 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 276 {
 277         return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 278 }
 279
 280 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 281 {
 282         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 283         u32 dpfc_ctl;
 284         int threshold = dev_priv->fbc.threshold;
 285
 286         /* Display WA #0529: skl, kbl, bxt. */
 287         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
 288                 u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
 289
 290                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 291
 292                 if (params->gen9_wa_cfb_stride)
 293                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 294
 295                 intel_de_write(dev_priv, CHICKEN_MISC_4, val);
 296         }
 297
 298         dpfc_ctl = 0;
 299         if (IS_IVYBRIDGE(dev_priv))
 300                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 301
 302         if (params->fb.format->cpp[0] == 2)
 303                 threshold++;
 304
 305         switch (threshold) {
 306         case 4:
 307         case 3:
 308                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 309                 break;
 310         case 2:
 311                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 312                 break;
 313         case 1:
 314                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 315                 break;
 316         }
 317
 318         if (params->fence_id >= 0) {
 319                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 320                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 321                                SNB_CPU_FENCE_ENABLE | params->fence_id);
 322                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 323                                params->crtc.fence_y_offset);
 324         } else if (dev_priv->ggtt.num_fences) {
 325                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 326                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 327         }
 328
 329         if (dev_priv->fbc.false_color)
 330                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 331
 332         if (IS_IVYBRIDGE(dev_priv)) {
 333                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 334                 intel_de_write(dev_priv, ILK_DISPLAY_CHICKEN1,
 335                                intel_de_read(dev_priv, ILK_DISPLAY_CHICKEN1) | ILK_FBCQ_DIS);
 336         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 337                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 338                 intel_de_write(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe),
 339                                intel_de_read(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe)) | HSW_FBCQ_DIS);
 340         }
 341
 342         if (INTEL_GEN(dev_priv) >= 11)
 343                 /* Wa_1409120013:icl,ehl,tgl */
 344                 intel_de_write(dev_priv, ILK_DPFC_CHICKEN,
 345                                ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 346
 347         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 348
 349         intel_fbc_recompress(dev_priv);
 350 }
 351
 352 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 353 {
 354         if (INTEL_GEN(dev_priv) >= 5)
 355                 return ilk_fbc_is_active(dev_priv);
 356         else if (IS_GM45(dev_priv))
 357                 return g4x_fbc_is_active(dev_priv);
 358         else
 359                 return i8xx_fbc_is_active(dev_priv);
 360 }
 361
 362 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 363 {
 364         struct intel_fbc *fbc = &dev_priv->fbc;
 365
 366         trace_intel_fbc_activate(fbc->crtc);
 367
 368         fbc->active = true;
 369         fbc->activated = true;
 370
 371         if (INTEL_GEN(dev_priv) >= 7)
 372                 gen7_fbc_activate(dev_priv);
 373         else if (INTEL_GEN(dev_priv) >= 5)
 374                 ilk_fbc_activate(dev_priv);
 375         else if (IS_GM45(dev_priv))
 376                 g4x_fbc_activate(dev_priv);
 377         else
 378                 i8xx_fbc_activate(dev_priv);
 379 }
 380
 381 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 382 {
 383         struct intel_fbc *fbc = &dev_priv->fbc;
 384
 385         trace_intel_fbc_deactivate(fbc->crtc);
 386
 387         fbc->active = false;
 388
 389         if (INTEL_GEN(dev_priv) >= 5)
 390                 ilk_fbc_deactivate(dev_priv);
 391         else if (IS_GM45(dev_priv))
 392                 g4x_fbc_deactivate(dev_priv);
 393         else
 394                 i8xx_fbc_deactivate(dev_priv);
 395 }
 396
 397 /**
 398  * intel_fbc_is_active - Is FBC active?
 399  * @dev_priv: i915 device instance
 400  *
 401  * This function is used to verify the current state of FBC.
 402  *
 403  * FIXME: This should be tracked in the plane config eventually
 404  * instead of queried at runtime for most callers.
 405  */
 406 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 407 {
 408         return dev_priv->fbc.active;
 409 }
 410
 411 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 412                                  const char *reason)
 413 {
 414         struct intel_fbc *fbc = &dev_priv->fbc;
 415
 416         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 417
 418         if (fbc->active)
 419                 intel_fbc_hw_deactivate(dev_priv);
 420
 421         fbc->no_fbc_reason = reason;
 422 }
 423
 424 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 425                                       struct drm_mm_node *node,
 426                                       unsigned int size,
 427                                       unsigned int fb_cpp)
 428 {
 429         int compression_threshold = 1;
 430         int ret;
 431         u64 end;
 432
 433         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 434          * reserved range size, so it always assumes the maximum (8mb) is used.
 435          * If we enable FBC using a CFB on that memory range we'll get FIFO
 436          * underruns, even if that range is not reserved by the BIOS. */
 437         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 438                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 439         else
 440                 end = U64_MAX;
 441
 442         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 443          * code changes, this code needs to change as well.
 444          *
 445          * The enable_fbc code will attempt to use one of our 2 compression
 446          * thresholds, therefore, in that case, we only have 1 resort.
 447          */
 448
 449         /* Try to over-allocate to reduce reallocations and fragmentation. */
 450         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 451                                                    4096, 0, end);
 452         if (ret == 0)
 453                 return compression_threshold;
 454
 455 again:
 456         /* HW's ability to limit the CFB is 1:4 */
 457         if (compression_threshold > 4 ||
 458             (fb_cpp == 2 && compression_threshold == 2))
 459                 return 0;
 460
 461         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 462                                                    4096, 0, end);
 463         if (ret && INTEL_GEN(dev_priv) <= 4) {
 464                 return 0;
 465         } else if (ret) {
 466                 compression_threshold <<= 1;
 467                 goto again;
 468         } else {
 469                 return compression_threshold;
 470         }
 471 }
 472
 473 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
 474                                unsigned int size, unsigned int fb_cpp)
 475 {
 476         struct intel_fbc *fbc = &dev_priv->fbc;
 477         struct drm_mm_node *uninitialized_var(compressed_llb);
 478         int ret;
 479
 480         drm_WARN_ON(&dev_priv->drm,
 481                     drm_mm_node_allocated(&fbc->compressed_fb));
 482
 483         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 484                                          size, fb_cpp);
 485         if (!ret)
 486                 goto err_llb;
 487         else if (ret > 1) {
 488                 DRM_INFO_ONCE("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 489         }
 490
 491         fbc->threshold = ret;
 492
 493         if (INTEL_GEN(dev_priv) >= 5)
 494                 intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
 495                                fbc->compressed_fb.start);
 496         else if (IS_GM45(dev_priv)) {
 497                 intel_de_write(dev_priv, DPFC_CB_BASE,
 498                                fbc->compressed_fb.start);
 499         } else {
 500                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 501                 if (!compressed_llb)
 502                         goto err_fb;
 503
 504                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 505                                                   4096, 4096);
 506                 if (ret)
 507                         goto err_fb;
 508
 509                 fbc->compressed_llb = compressed_llb;
 510
 511                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 512                                                  fbc->compressed_fb.start,
 513                                                  U32_MAX));
 514                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 515                                                  fbc->compressed_llb->start,
 516                                                  U32_MAX));
 517                 intel_de_write(dev_priv, FBC_CFB_BASE,
 518                                dev_priv->dsm.start + fbc->compressed_fb.start);
 519                 intel_de_write(dev_priv, FBC_LL_BASE,
 520                                dev_priv->dsm.start + compressed_llb->start);
 521         }
 522
 523         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 524                       fbc->compressed_fb.size, fbc->threshold);
 525
 526         return 0;
 527
 528 err_fb:
 529         kfree(compressed_llb);
 530         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 531 err_llb:
 532         if (drm_mm_initialized(&dev_priv->mm.stolen))
 533                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 534         return -ENOSPC;
 535 }
 536
 537 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 538 {
 539         struct intel_fbc *fbc = &dev_priv->fbc;
 540
 541         if (!drm_mm_node_allocated(&fbc->compressed_fb))
 542                 return;
 543
 544         if (fbc->compressed_llb) {
 545                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 546                 kfree(fbc->compressed_llb);
 547         }
 548
 549         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 550 }
 551
 552 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 553 {
 554         struct intel_fbc *fbc = &dev_priv->fbc;
 555
 556         if (!HAS_FBC(dev_priv))
 557                 return;
 558
 559         mutex_lock(&fbc->lock);
 560         __intel_fbc_cleanup_cfb(dev_priv);
 561         mutex_unlock(&fbc->lock);
 562 }
 563
 564 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 565                             unsigned int stride)
 566 {
 567         /* This should have been caught earlier. */
 568         if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
 569                 return false;
 570
 571         /* Below are the additional FBC restrictions. */
 572         if (stride < 512)
 573                 return false;
 574
 575         if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
 576                 return stride == 4096 || stride == 8192;
 577
 578         if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
 579                 return false;
 580
 581         if (stride > 16384)
 582                 return false;
 583
 584         return true;
 585 }
 586
 587 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 588                                   u32 pixel_format)
 589 {
 590         switch (pixel_format) {
 591         case DRM_FORMAT_XRGB8888:
 592         case DRM_FORMAT_XBGR8888:
 593                 return true;
 594         case DRM_FORMAT_XRGB1555:
 595         case DRM_FORMAT_RGB565:
 596                 /* 16bpp not supported on gen2 */
 597                 if (IS_GEN(dev_priv, 2))
 598                         return false;
 599                 /* WaFbcOnly1to1Ratio:ctg */
 600                 if (IS_G4X(dev_priv))
 601                         return false;
 602                 return true;
 603         default:
 604                 return false;
 605         }
 606 }
 607
 608 /*
 609  * For some reason, the hardware tracking starts looking at whatever we
 610  * programmed as the display plane base address register. It does not look at
 611  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 612  * variables instead of just looking at the pipe/plane size.
 613  */
 614 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 615 {
 616         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 617         struct intel_fbc *fbc = &dev_priv->fbc;
 618         unsigned int effective_w, effective_h, max_w, max_h;
 619
 620         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 621                 max_w = 5120;
 622                 max_h = 4096;
 623         } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 624                 max_w = 4096;
 625                 max_h = 4096;
 626         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 627                 max_w = 4096;
 628                 max_h = 2048;
 629         } else {
 630                 max_w = 2048;
 631                 max_h = 1536;
 632         }
 633
 634         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 635                                         &effective_h);
 636         effective_w += fbc->state_cache.plane.adjusted_x;
 637         effective_h += fbc->state_cache.plane.adjusted_y;
 638
 639         return effective_w <= max_w && effective_h <= max_h;
 640 }
 641
 642 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 643                                          const struct intel_crtc_state *crtc_state,
 644                                          const struct intel_plane_state *plane_state)
 645 {
 646         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 647         struct intel_fbc *fbc = &dev_priv->fbc;
 648         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 649         struct drm_framebuffer *fb = plane_state->hw.fb;
 650
 651         cache->plane.visible = plane_state->uapi.visible;
 652         if (!cache->plane.visible)
 653                 return;
 654
 655         cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
 656         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 657                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 658
 659         cache->plane.rotation = plane_state->hw.rotation;
 660         /*
 661          * Src coordinates are already rotated by 270 degrees for
 662          * the 90/270 degree plane rotation cases (to match the
 663          * GTT mapping), hence no need to account for rotation here.
 664          */
 665         cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 666         cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 667         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 668         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 669         cache->plane.y = plane_state->uapi.src.y1 >> 16;
 670
 671         cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 672
 673         cache->fb.format = fb->format;
 674         cache->fb.stride = fb->pitches[0];
 675
 676         drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
 677                     !plane_state->vma->fence);
 678
 679         if (plane_state->flags & PLANE_HAS_FENCE &&
 680             plane_state->vma->fence)
 681                 cache->fence_id = plane_state->vma->fence->id;
 682         else
 683                 cache->fence_id = -1;
 684 }
 685
 686 static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
 687 {
 688         struct intel_fbc *fbc = &dev_priv->fbc;
 689
 690         return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 691                 fbc->compressed_fb.size * fbc->threshold;
 692 }
 693
 694 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 695 {
 696         struct intel_fbc *fbc = &dev_priv->fbc;
 697
 698         if (intel_vgpu_active(dev_priv)) {
 699                 fbc->no_fbc_reason = "VGPU is active";
 700                 return false;
 701         }
 702
 703         if (!i915_modparams.enable_fbc) {
 704                 fbc->no_fbc_reason = "disabled per module param or by default";
 705                 return false;
 706         }
 707
 708         if (fbc->underrun_detected) {
 709                 fbc->no_fbc_reason = "underrun detected";
 710                 return false;
 711         }
 712
 713         return true;
 714 }
 715
 716 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 717 {
 718         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 719         struct intel_fbc *fbc = &dev_priv->fbc;
 720         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 721
 722         if (!intel_fbc_can_enable(dev_priv))
 723                 return false;
 724
 725         if (!cache->plane.visible) {
 726                 fbc->no_fbc_reason = "primary plane not visible";
 727                 return false;
 728         }
 729
 730         /* We don't need to use a state cache here since this information is
 731          * global for all CRTC.
 732          */
 733         if (fbc->underrun_detected) {
 734                 fbc->no_fbc_reason = "underrun detected";
 735                 return false;
 736         }
 737
 738         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 739                 fbc->no_fbc_reason = "incompatible mode";
 740                 return false;
 741         }
 742
 743         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 744                 fbc->no_fbc_reason = "mode too large for compression";
 745                 return false;
 746         }
 747
 748         /* The use of a CPU fence is mandatory in order to detect writes
 749          * by the CPU to the scanout and trigger updates to the FBC.
 750          *
 751          * Note that is possible for a tiled surface to be unmappable (and
 752          * so have no fence associated with it) due to aperture constaints
 753          * at the time of pinning.
 754          *
 755          * FIXME with 90/270 degree rotation we should use the fence on
 756          * the normal GTT view (the rotated view doesn't even have a
 757          * fence). Would need changes to the FBC fence Y offset as well.
 758          * For now this will effecively disable FBC with 90/270 degree
 759          * rotation.
 760          */
 761         if (cache->fence_id < 0) {
 762                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 763                 return false;
 764         }
 765         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 766             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 767                 fbc->no_fbc_reason = "rotation unsupported";
 768                 return false;
 769         }
 770
 771         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 772                 fbc->no_fbc_reason = "framebuffer stride not supported";
 773                 return false;
 774         }
 775
 776         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 777                 fbc->no_fbc_reason = "pixel format is invalid";
 778                 return false;
 779         }
 780
 781         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 782             cache->fb.format->has_alpha) {
 783                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 784                 return false;
 785         }
 786
 787         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 788         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 789             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 790                 fbc->no_fbc_reason = "pixel rate is too big";
 791                 return false;
 792         }
 793
 794         /* It is possible for the required CFB size change without a
 795          * crtc->disable + crtc->enable since it is possible to change the
 796          * stride without triggering a full modeset. Since we try to
 797          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 798          * if this happens, but if we exceed the current CFB size we'll have to
 799          * disable FBC. Notice that it would be possible to disable FBC, wait
 800          * for a frame, free the stolen node, then try to reenable FBC in case
 801          * we didn't get any invalidate/deactivate calls, but this would require
 802          * a lot of tracking just for a specific case. If we conclude it's an
 803          * important case, we can implement it later. */
 804         if (intel_fbc_cfb_size_changed(dev_priv)) {
 805                 fbc->no_fbc_reason = "CFB requirements changed";
 806                 return false;
 807         }
 808
 809         /*
 810          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 811          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 812          * and screen flicker.
 813          */
 814         if (INTEL_GEN(dev_priv) >= 9 &&
 815             (fbc->state_cache.plane.adjusted_y & 3)) {
 816                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 817                 return false;
 818         }
 819
 820         return true;
 821 }
 822
 823 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 824                                      struct intel_fbc_reg_params *params)
 825 {
 826         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 827         struct intel_fbc *fbc = &dev_priv->fbc;
 828         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 829
 830         /* Since all our fields are integer types, use memset here so the
 831          * comparison function can rely on memcmp because the padding will be
 832          * zero. */
 833         memset(params, 0, sizeof(*params));
 834
 835         params->fence_id = cache->fence_id;
 836
 837         params->crtc.pipe = crtc->pipe;
 838         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 839         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 840
 841         params->fb.format = cache->fb.format;
 842         params->fb.stride = cache->fb.stride;
 843
 844         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 845
 846         params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
 847
 848         params->plane_visible = cache->plane.visible;
 849 }
 850
 851 static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
 852 {
 853         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 854         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 855         const struct intel_fbc *fbc = &dev_priv->fbc;
 856         const struct intel_fbc_state_cache *cache = &fbc->state_cache;
 857         const struct intel_fbc_reg_params *params = &fbc->params;
 858
 859         if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
 860                 return false;
 861
 862         if (!params->plane_visible)
 863                 return false;
 864
 865         if (!intel_fbc_can_activate(crtc))
 866                 return false;
 867
 868         if (params->fb.format != cache->fb.format)
 869                 return false;
 870
 871         if (params->fb.stride != cache->fb.stride)
 872                 return false;
 873
 874         if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
 875                 return false;
 876
 877         if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
 878                 return false;
 879
 880         return true;
 881 }
 882
 883 bool intel_fbc_pre_update(struct intel_atomic_state *state,
 884                           struct intel_crtc *crtc)
 885 {
 886         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 887         const struct intel_crtc_state *crtc_state =
 888                 intel_atomic_get_new_crtc_state(state, crtc);
 889         const struct intel_plane_state *plane_state =
 890                 intel_atomic_get_new_plane_state(state, plane);
 891         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 892         struct intel_fbc *fbc = &dev_priv->fbc;
 893         const char *reason = "update pending";
 894         bool need_vblank_wait = false;
 895
 896         if (!plane->has_fbc || !plane_state)
 897                 return need_vblank_wait;
 898
 899         mutex_lock(&fbc->lock);
 900
 901         if (fbc->crtc != crtc)
 902                 goto unlock;
 903
 904         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 905         fbc->flip_pending = true;
 906
 907         if (!intel_fbc_can_flip_nuke(crtc_state)) {
 908                 intel_fbc_deactivate(dev_priv, reason);
 909
 910                 /*
 911                  * Display WA #1198: glk+
 912                  * Need an extra vblank wait between FBC disable and most plane
 913                  * updates. Bspec says this is only needed for plane disable, but
 914                  * that is not true. Touching most plane registers will cause the
 915                  * corruption to appear. Also SKL/derivatives do not seem to be
 916                  * affected.
 917                  *
 918                  * TODO: could optimize this a bit by sampling the frame
 919                  * counter when we disable FBC (if it was already done earlier)
 920                  * and skipping the extra vblank wait before the plane update
 921                  * if at least one frame has already passed.
 922                  */
 923                 if (fbc->activated &&
 924                     (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
 925                         need_vblank_wait = true;
 926                 fbc->activated = false;
 927         }
 928 unlock:
 929         mutex_unlock(&fbc->lock);
 930
 931         return need_vblank_wait;
 932 }
 933
 934 /**
 935  * __intel_fbc_disable - disable FBC
 936  * @dev_priv: i915 device instance
 937  *
 938  * This is the low level function that actually disables FBC. Callers should
 939  * grab the FBC lock.
 940  */
 941 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 942 {
 943         struct intel_fbc *fbc = &dev_priv->fbc;
 944         struct intel_crtc *crtc = fbc->crtc;
 945
 946         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 947         drm_WARN_ON(&dev_priv->drm, !fbc->crtc);
 948         drm_WARN_ON(&dev_priv->drm, fbc->active);
 949
 950         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
 951
 952         __intel_fbc_cleanup_cfb(dev_priv);
 953
 954         fbc->crtc = NULL;
 955 }
 956
 957 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 958 {
 959         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 960         struct intel_fbc *fbc = &dev_priv->fbc;
 961
 962         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 963
 964         if (fbc->crtc != crtc)
 965                 return;
 966
 967         fbc->flip_pending = false;
 968
 969         if (!i915_modparams.enable_fbc) {
 970                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
 971                 __intel_fbc_disable(dev_priv);
 972
 973                 return;
 974         }
 975
 976         intel_fbc_get_reg_params(crtc, &fbc->params);
 977
 978         if (!intel_fbc_can_activate(crtc))
 979                 return;
 980
 981         if (!fbc->busy_bits)
 982                 intel_fbc_hw_activate(dev_priv);
 983         else
 984                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 985 }
 986
 987 void intel_fbc_post_update(struct intel_atomic_state *state,
 988                            struct intel_crtc *crtc)
 989 {
 990         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 991         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 992         const struct intel_plane_state *plane_state =
 993                 intel_atomic_get_new_plane_state(state, plane);
 994         struct intel_fbc *fbc = &dev_priv->fbc;
 995
 996         if (!plane->has_fbc || !plane_state)
 997                 return;
 998
 999         mutex_lock(&fbc->lock);
1000         __intel_fbc_post_update(crtc);
1001         mutex_unlock(&fbc->lock);
1002 }
1003
1004 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1005 {
1006         if (fbc->crtc)
1007                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1008         else
1009                 return fbc->possible_framebuffer_bits;
1010 }
1011
1012 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1013                           unsigned int frontbuffer_bits,
1014                           enum fb_op_origin origin)
1015 {
1016         struct intel_fbc *fbc = &dev_priv->fbc;
1017
1018         if (!HAS_FBC(dev_priv))
1019                 return;
1020
1021         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1022                 return;
1023
1024         mutex_lock(&fbc->lock);
1025
1026         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1027
1028         if (fbc->crtc && fbc->busy_bits)
1029                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1030
1031         mutex_unlock(&fbc->lock);
1032 }
1033
1034 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1035                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1036 {
1037         struct intel_fbc *fbc = &dev_priv->fbc;
1038
1039         if (!HAS_FBC(dev_priv))
1040                 return;
1041
1042         mutex_lock(&fbc->lock);
1043
1044         fbc->busy_bits &= ~frontbuffer_bits;
1045
1046         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1047                 goto out;
1048
1049         if (!fbc->busy_bits && fbc->crtc &&
1050             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1051                 if (fbc->active)
1052                         intel_fbc_recompress(dev_priv);
1053                 else if (!fbc->flip_pending)
1054                         __intel_fbc_post_update(fbc->crtc);
1055         }
1056
1057 out:
1058         mutex_unlock(&fbc->lock);
1059 }
1060
1061 /**
1062  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1063  * @dev_priv: i915 device instance
1064  * @state: the atomic state structure
1065  *
1066  * This function looks at the proposed state for CRTCs and planes, then chooses
1067  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1068  * true.
1069  *
1070  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1071  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1072  */
1073 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1074                            struct intel_atomic_state *state)
1075 {
1076         struct intel_fbc *fbc = &dev_priv->fbc;
1077         struct intel_plane *plane;
1078         struct intel_plane_state *plane_state;
1079         bool crtc_chosen = false;
1080         int i;
1081
1082         mutex_lock(&fbc->lock);
1083
1084         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1085         if (fbc->crtc &&
1086             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1087                 goto out;
1088
1089         if (!intel_fbc_can_enable(dev_priv))
1090                 goto out;
1091
1092         /* Simply choose the first CRTC that is compatible and has a visible
1093          * plane. We could go for fancier schemes such as checking the plane
1094          * size, but this would just affect the few platforms that don't tie FBC
1095          * to pipe or plane A. */
1096         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1097                 struct intel_crtc_state *crtc_state;
1098                 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1099
1100                 if (!plane->has_fbc)
1101                         continue;
1102
1103                 if (!plane_state->uapi.visible)
1104                         continue;
1105
1106                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1107
1108                 crtc_state->enable_fbc = true;
1109                 crtc_chosen = true;
1110                 break;
1111         }
1112
1113         if (!crtc_chosen)
1114                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1115
1116 out:
1117         mutex_unlock(&fbc->lock);
1118 }
1119
1120 /**
1121  * intel_fbc_enable: tries to enable FBC on the CRTC
1122  * @crtc: the CRTC
1123  * @state: corresponding &drm_crtc_state for @crtc
1124  *
1125  * This function checks if the given CRTC was chosen for FBC, then enables it if
1126  * possible. Notice that it doesn't activate FBC. It is valid to call
1127  * intel_fbc_enable multiple times for the same pipe without an
1128  * intel_fbc_disable in the middle, as long as it is deactivated.
1129  */
1130 void intel_fbc_enable(struct intel_atomic_state *state,
1131                       struct intel_crtc *crtc)
1132 {
1133         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1134         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1135         const struct intel_crtc_state *crtc_state =
1136                 intel_atomic_get_new_crtc_state(state, crtc);
1137         const struct intel_plane_state *plane_state =
1138                 intel_atomic_get_new_plane_state(state, plane);
1139         struct intel_fbc *fbc = &dev_priv->fbc;
1140         struct intel_fbc_state_cache *cache = &fbc->state_cache;
1141
1142         if (!plane->has_fbc || !plane_state)
1143                 return;
1144
1145         mutex_lock(&fbc->lock);
1146
1147         if (fbc->crtc) {
1148                 if (fbc->crtc != crtc ||
1149                     !intel_fbc_cfb_size_changed(dev_priv))
1150                         goto out;
1151
1152                 __intel_fbc_disable(dev_priv);
1153         }
1154
1155         drm_WARN_ON(&dev_priv->drm, fbc->active);
1156
1157         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1158
1159         /* FIXME crtc_state->enable_fbc lies :( */
1160         if (!cache->plane.visible)
1161                 goto out;
1162
1163         if (intel_fbc_alloc_cfb(dev_priv,
1164                                 intel_fbc_calculate_cfb_size(dev_priv, cache),
1165                                 plane_state->hw.fb->format->cpp[0])) {
1166                 cache->plane.visible = false;
1167                 fbc->no_fbc_reason = "not enough stolen memory";
1168                 goto out;
1169         }
1170
1171         if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
1172             plane_state->hw.fb->modifier != I915_FORMAT_MOD_X_TILED)
1173                 cache->gen9_wa_cfb_stride =
1174                         DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
1175         else
1176                 cache->gen9_wa_cfb_stride = 0;
1177
1178         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1179         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1180
1181         fbc->crtc = crtc;
1182 out:
1183         mutex_unlock(&fbc->lock);
1184 }
1185
1186 /**
1187  * intel_fbc_disable - disable FBC if it's associated with crtc
1188  * @crtc: the CRTC
1189  *
1190  * This function disables FBC if it's associated with the provided CRTC.
1191  */
1192 void intel_fbc_disable(struct intel_crtc *crtc)
1193 {
1194         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1195         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1196         struct intel_fbc *fbc = &dev_priv->fbc;
1197
1198         if (!plane->has_fbc)
1199                 return;
1200
1201         mutex_lock(&fbc->lock);
1202         if (fbc->crtc == crtc)
1203                 __intel_fbc_disable(dev_priv);
1204         mutex_unlock(&fbc->lock);
1205 }
1206
1207 /**
1208  * intel_fbc_global_disable - globally disable FBC
1209  * @dev_priv: i915 device instance
1210  *
1211  * This function disables FBC regardless of which CRTC is associated with it.
1212  */
1213 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1214 {
1215         struct intel_fbc *fbc = &dev_priv->fbc;
1216
1217         if (!HAS_FBC(dev_priv))
1218                 return;
1219
1220         mutex_lock(&fbc->lock);
1221         if (fbc->crtc) {
1222                 drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);
1223                 __intel_fbc_disable(dev_priv);
1224         }
1225         mutex_unlock(&fbc->lock);
1226 }
1227
1228 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1229 {
1230         struct drm_i915_private *dev_priv =
1231                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1232         struct intel_fbc *fbc = &dev_priv->fbc;
1233
1234         mutex_lock(&fbc->lock);
1235
1236         /* Maybe we were scheduled twice. */
1237         if (fbc->underrun_detected || !fbc->crtc)
1238                 goto out;
1239
1240         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1241         fbc->underrun_detected = true;
1242
1243         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1244 out:
1245         mutex_unlock(&fbc->lock);
1246 }
1247
1248 /*
1249  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1250  * @dev_priv: i915 device instance
1251  *
1252  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1253  * want to re-enable FBC after an underrun to increase test coverage.
1254  */
1255 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1256 {
1257         int ret;
1258
1259         cancel_work_sync(&dev_priv->fbc.underrun_work);
1260
1261         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1262         if (ret)
1263                 return ret;
1264
1265         if (dev_priv->fbc.underrun_detected) {
1266                 DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
1267                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1268         }
1269
1270         dev_priv->fbc.underrun_detected = false;
1271         mutex_unlock(&dev_priv->fbc.lock);
1272
1273         return 0;
1274 }
1275
1276 /**
1277  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1278  * @dev_priv: i915 device instance
1279  *
1280  * Without FBC, most underruns are harmless and don't really cause too many
1281  * problems, except for an annoying message on dmesg. With FBC, underruns can
1282  * become black screens or even worse, especially when paired with bad
1283  * watermarks. So in order for us to be on the safe side, completely disable FBC
1284  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1285  * already suggests that watermarks may be bad, so try to be as safe as
1286  * possible.
1287  *
1288  * This function is called from the IRQ handler.
1289  */
1290 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1291 {
1292         struct intel_fbc *fbc = &dev_priv->fbc;
1293
1294         if (!HAS_FBC(dev_priv))
1295                 return;
1296
1297         /* There's no guarantee that underrun_detected won't be set to true
1298          * right after this check and before the work is scheduled, but that's
1299          * not a problem since we'll check it again under the work function
1300          * while FBC is locked. This check here is just to prevent us from
1301          * unnecessarily scheduling the work, and it relies on the fact that we
1302          * never switch underrun_detect back to false after it's true. */
1303         if (READ_ONCE(fbc->underrun_detected))
1304                 return;
1305
1306         schedule_work(&fbc->underrun_work);
1307 }
1308
1309 /*
1310  * The DDX driver changes its behavior depending on the value it reads from
1311  * i915.enable_fbc, so sanitize it by translating the default value into either
1312  * 0 or 1 in order to allow it to know what's going on.
1313  *
1314  * Notice that this is done at driver initialization and we still allow user
1315  * space to change the value during runtime without sanitizing it again. IGT
1316  * relies on being able to change i915.enable_fbc at runtime.
1317  */
1318 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1319 {
1320         if (i915_modparams.enable_fbc >= 0)
1321                 return !!i915_modparams.enable_fbc;
1322
1323         if (!HAS_FBC(dev_priv))
1324                 return 0;
1325
1326         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1327                 return 1;
1328
1329         return 0;
1330 }
1331
1332 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1333 {
1334         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1335         if (intel_vtd_active() &&
1336             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1337                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1338                 return true;
1339         }
1340
1341         return false;
1342 }
1343
1344 /**
1345  * intel_fbc_init - Initialize FBC
1346  * @dev_priv: the i915 device
1347  *
1348  * This function might be called during PM init process.
1349  */
1350 void intel_fbc_init(struct drm_i915_private *dev_priv)
1351 {
1352         struct intel_fbc *fbc = &dev_priv->fbc;
1353
1354         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1355         mutex_init(&fbc->lock);
1356         fbc->active = false;
1357
1358         if (!drm_mm_initialized(&dev_priv->mm.stolen))
1359                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1360
1361         if (need_fbc_vtd_wa(dev_priv))
1362                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1363
1364         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1365         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1366                       i915_modparams.enable_fbc);
1367
1368         if (!HAS_FBC(dev_priv)) {
1369                 fbc->no_fbc_reason = "unsupported by this chipset";
1370                 return;
1371         }
1372
1373         /* This value was pulled out of someone's hat */
1374         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1375                 intel_de_write(dev_priv, FBC_CONTROL,
1376                                500 << FBC_CTL_INTERVAL_SHIFT);
1377
1378         /* We still don't have any sort of hardware state readout for FBC, so
1379          * deactivate it in case the BIOS activated it to make sure software
1380          * matches the hardware state. */
1381         if (intel_fbc_hw_is_active(dev_priv))
1382                 intel_fbc_hw_deactivate(dev_priv);
1383 }