drivers/gpu/drm/i915/display/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <drm/drm_fourcc.h>
  42
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "i915_vgpu.h"
  46 #include "intel_display_types.h"
  47 #include "intel_fbc.h"
  48 #include "intel_frontbuffer.h"
  49
  50 /*
  51  * For SKL+, the plane source size used by the hardware is based on the value we
  52  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  53  * we wrote to PIPESRC.
  54  */
  55 static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
  56                                             int *width, int *height)
  57 {
  58         if (width)
  59                 *width = cache->plane.src_w;
  60         if (height)
  61                 *height = cache->plane.src_h;
  62 }
  63
  64 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  65                                         const struct intel_fbc_state_cache *cache)
  66 {
  67         int lines;
  68
  69         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  70         if (IS_GEN(dev_priv, 7))
  71                 lines = min(lines, 2048);
  72         else if (INTEL_GEN(dev_priv) >= 8)
  73                 lines = min(lines, 2560);
  74
  75         /* Hardware needs the full buffer stride, not just the active area. */
  76         return lines * cache->fb.stride;
  77 }
  78
  79 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  80 {
  81         u32 fbc_ctl;
  82
  83         /* Disable compression */
  84         fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
  85         if ((fbc_ctl & FBC_CTL_EN) == 0)
  86                 return;
  87
  88         fbc_ctl &= ~FBC_CTL_EN;
  89         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
  90
  91         /* Wait for compressing bit to clear */
  92         if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
  93                                     FBC_STAT_COMPRESSING, 10)) {
  94                 drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n");
  95                 return;
  96         }
  97 }
  98
  99 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 100 {
 101         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 102         int cfb_pitch;
 103         int i;
 104         u32 fbc_ctl;
 105
 106         /* Note: fbc.threshold == 1 for i8xx */
 107         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 108         if (params->fb.stride < cfb_pitch)
 109                 cfb_pitch = params->fb.stride;
 110
 111         /* FBC_CTL wants 32B or 64B units */
 112         if (IS_GEN(dev_priv, 2))
 113                 cfb_pitch = (cfb_pitch / 32) - 1;
 114         else
 115                 cfb_pitch = (cfb_pitch / 64) - 1;
 116
 117         /* Clear old tags */
 118         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 119                 intel_de_write(dev_priv, FBC_TAG(i), 0);
 120
 121         if (IS_GEN(dev_priv, 4)) {
 122                 u32 fbc_ctl2;
 123
 124                 /* Set it up... */
 125                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
 126                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 127                 if (params->fence_id >= 0)
 128                         fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 129                 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
 130                 intel_de_write(dev_priv, FBC_FENCE_OFF,
 131                                params->fence_y_offset);
 132         }
 133
 134         /* enable it... */
 135         fbc_ctl = FBC_CTL_INTERVAL(params->interval);
 136         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 137         if (IS_I945GM(dev_priv))
 138                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 139         fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff);
 140         if (params->fence_id >= 0)
 141                 fbc_ctl |= FBC_CTL_FENCENO(params->fence_id);
 142         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
 143 }
 144
 145 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 146 {
 147         return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
 148 }
 149
 150 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 151 {
 152         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 153         u32 dpfc_ctl;
 154
 155         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 156         if (params->fb.format->cpp[0] == 2)
 157                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 158         else
 159                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 160
 161         if (params->fence_id >= 0) {
 162                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
 163                 intel_de_write(dev_priv, DPFC_FENCE_YOFF,
 164                                params->fence_y_offset);
 165         } else {
 166                 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
 167         }
 168
 169         /* enable it... */
 170         intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 171 }
 172
 173 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 174 {
 175         u32 dpfc_ctl;
 176
 177         /* Disable compression */
 178         dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL);
 179         if (dpfc_ctl & DPFC_CTL_EN) {
 180                 dpfc_ctl &= ~DPFC_CTL_EN;
 181                 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl);
 182         }
 183 }
 184
 185 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 186 {
 187         return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
 188 }
 189
 190 static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
 191 {
 192         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 193         enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
 194
 195         spin_lock_irq(&dev_priv->uncore.lock);
 196         intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
 197                           intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
 198         spin_unlock_irq(&dev_priv->uncore.lock);
 199 }
 200
 201 static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
 202 {
 203         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 204         enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
 205
 206         spin_lock_irq(&dev_priv->uncore.lock);
 207         intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
 208                           intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
 209         spin_unlock_irq(&dev_priv->uncore.lock);
 210 }
 211
 212 /* This function forces a CFB recompression through the nuke operation. */
 213 static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
 214 {
 215         struct intel_fbc *fbc = &dev_priv->fbc;
 216
 217         trace_intel_fbc_nuke(fbc->crtc);
 218
 219         intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
 220         intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
 221 }
 222
 223 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 224 {
 225         if (INTEL_GEN(dev_priv) >= 6)
 226                 snb_fbc_recompress(dev_priv);
 227         else if (INTEL_GEN(dev_priv) >= 4)
 228                 i965_fbc_recompress(dev_priv);
 229         else
 230                 i8xx_fbc_recompress(dev_priv);
 231 }
 232
 233 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 234 {
 235         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 236         u32 dpfc_ctl;
 237         int threshold = dev_priv->fbc.threshold;
 238
 239         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 240         if (params->fb.format->cpp[0] == 2)
 241                 threshold++;
 242
 243         switch (threshold) {
 244         case 4:
 245         case 3:
 246                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 247                 break;
 248         case 2:
 249                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 250                 break;
 251         case 1:
 252                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 253                 break;
 254         }
 255
 256         if (params->fence_id >= 0) {
 257                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 258                 if (IS_GEN(dev_priv, 5))
 259                         dpfc_ctl |= params->fence_id;
 260                 if (IS_GEN(dev_priv, 6)) {
 261                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 262                                        SNB_CPU_FENCE_ENABLE | params->fence_id);
 263                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 264                                        params->fence_y_offset);
 265                 }
 266         } else {
 267                 if (IS_GEN(dev_priv, 6)) {
 268                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 269                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 270                 }
 271         }
 272
 273         intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
 274                        params->fence_y_offset);
 275         /* enable it... */
 276         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 277
 278         intel_fbc_recompress(dev_priv);
 279 }
 280
 281 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 282 {
 283         u32 dpfc_ctl;
 284
 285         /* Disable compression */
 286         dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
 287         if (dpfc_ctl & DPFC_CTL_EN) {
 288                 dpfc_ctl &= ~DPFC_CTL_EN;
 289                 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl);
 290         }
 291 }
 292
 293 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 294 {
 295         return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 296 }
 297
 298 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 299 {
 300         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 301         u32 dpfc_ctl;
 302         int threshold = dev_priv->fbc.threshold;
 303
 304         /* Display WA #0529: skl, kbl, bxt. */
 305         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
 306                 u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
 307
 308                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 309
 310                 if (params->gen9_wa_cfb_stride)
 311                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 312
 313                 intel_de_write(dev_priv, CHICKEN_MISC_4, val);
 314         }
 315
 316         dpfc_ctl = 0;
 317         if (IS_IVYBRIDGE(dev_priv))
 318                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 319
 320         if (params->fb.format->cpp[0] == 2)
 321                 threshold++;
 322
 323         switch (threshold) {
 324         case 4:
 325         case 3:
 326                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 327                 break;
 328         case 2:
 329                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 330                 break;
 331         case 1:
 332                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 333                 break;
 334         }
 335
 336         if (params->fence_id >= 0) {
 337                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 338                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 339                                SNB_CPU_FENCE_ENABLE | params->fence_id);
 340                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 341                                params->fence_y_offset);
 342         } else if (dev_priv->ggtt.num_fences) {
 343                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 344                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 345         }
 346
 347         if (dev_priv->fbc.false_color)
 348                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 349
 350         if (IS_IVYBRIDGE(dev_priv)) {
 351                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 352                 intel_de_write(dev_priv, ILK_DISPLAY_CHICKEN1,
 353                                intel_de_read(dev_priv, ILK_DISPLAY_CHICKEN1) | ILK_FBCQ_DIS);
 354         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 355                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 356                 intel_de_write(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe),
 357                                intel_de_read(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe)) | HSW_FBCQ_DIS);
 358         }
 359
 360         if (INTEL_GEN(dev_priv) >= 11)
 361                 /* Wa_1409120013:icl,ehl,tgl */
 362                 intel_de_write(dev_priv, ILK_DPFC_CHICKEN,
 363                                ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 364
 365         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 366
 367         intel_fbc_recompress(dev_priv);
 368 }
 369
 370 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 371 {
 372         if (INTEL_GEN(dev_priv) >= 5)
 373                 return ilk_fbc_is_active(dev_priv);
 374         else if (IS_GM45(dev_priv))
 375                 return g4x_fbc_is_active(dev_priv);
 376         else
 377                 return i8xx_fbc_is_active(dev_priv);
 378 }
 379
 380 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 381 {
 382         struct intel_fbc *fbc = &dev_priv->fbc;
 383
 384         trace_intel_fbc_activate(fbc->crtc);
 385
 386         fbc->active = true;
 387         fbc->activated = true;
 388
 389         if (INTEL_GEN(dev_priv) >= 7)
 390                 gen7_fbc_activate(dev_priv);
 391         else if (INTEL_GEN(dev_priv) >= 5)
 392                 ilk_fbc_activate(dev_priv);
 393         else if (IS_GM45(dev_priv))
 394                 g4x_fbc_activate(dev_priv);
 395         else
 396                 i8xx_fbc_activate(dev_priv);
 397 }
 398
 399 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 400 {
 401         struct intel_fbc *fbc = &dev_priv->fbc;
 402
 403         trace_intel_fbc_deactivate(fbc->crtc);
 404
 405         fbc->active = false;
 406
 407         if (INTEL_GEN(dev_priv) >= 5)
 408                 ilk_fbc_deactivate(dev_priv);
 409         else if (IS_GM45(dev_priv))
 410                 g4x_fbc_deactivate(dev_priv);
 411         else
 412                 i8xx_fbc_deactivate(dev_priv);
 413 }
 414
 415 /**
 416  * intel_fbc_is_active - Is FBC active?
 417  * @dev_priv: i915 device instance
 418  *
 419  * This function is used to verify the current state of FBC.
 420  *
 421  * FIXME: This should be tracked in the plane config eventually
 422  * instead of queried at runtime for most callers.
 423  */
 424 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 425 {
 426         return dev_priv->fbc.active;
 427 }
 428
 429 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 430                                  const char *reason)
 431 {
 432         struct intel_fbc *fbc = &dev_priv->fbc;
 433
 434         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 435
 436         if (fbc->active)
 437                 intel_fbc_hw_deactivate(dev_priv);
 438
 439         fbc->no_fbc_reason = reason;
 440 }
 441
 442 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 443                                       struct drm_mm_node *node,
 444                                       unsigned int size,
 445                                       unsigned int fb_cpp)
 446 {
 447         int compression_threshold = 1;
 448         int ret;
 449         u64 end;
 450
 451         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 452          * reserved range size, so it always assumes the maximum (8mb) is used.
 453          * If we enable FBC using a CFB on that memory range we'll get FIFO
 454          * underruns, even if that range is not reserved by the BIOS. */
 455         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 456                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 457         else
 458                 end = U64_MAX;
 459
 460         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 461          * code changes, this code needs to change as well.
 462          *
 463          * The enable_fbc code will attempt to use one of our 2 compression
 464          * thresholds, therefore, in that case, we only have 1 resort.
 465          */
 466
 467         /* Try to over-allocate to reduce reallocations and fragmentation. */
 468         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 469                                                    4096, 0, end);
 470         if (ret == 0)
 471                 return compression_threshold;
 472
 473 again:
 474         /* HW's ability to limit the CFB is 1:4 */
 475         if (compression_threshold > 4 ||
 476             (fb_cpp == 2 && compression_threshold == 2))
 477                 return 0;
 478
 479         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 480                                                    4096, 0, end);
 481         if (ret && INTEL_GEN(dev_priv) <= 4) {
 482                 return 0;
 483         } else if (ret) {
 484                 compression_threshold <<= 1;
 485                 goto again;
 486         } else {
 487                 return compression_threshold;
 488         }
 489 }
 490
 491 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
 492                                unsigned int size, unsigned int fb_cpp)
 493 {
 494         struct intel_fbc *fbc = &dev_priv->fbc;
 495         struct drm_mm_node *uninitialized_var(compressed_llb);
 496         int ret;
 497
 498         drm_WARN_ON(&dev_priv->drm,
 499                     drm_mm_node_allocated(&fbc->compressed_fb));
 500
 501         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 502                                          size, fb_cpp);
 503         if (!ret)
 504                 goto err_llb;
 505         else if (ret > 1) {
 506                 drm_info_once(&dev_priv->drm,
 507                               "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 508         }
 509
 510         fbc->threshold = ret;
 511
 512         if (INTEL_GEN(dev_priv) >= 5)
 513                 intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
 514                                fbc->compressed_fb.start);
 515         else if (IS_GM45(dev_priv)) {
 516                 intel_de_write(dev_priv, DPFC_CB_BASE,
 517                                fbc->compressed_fb.start);
 518         } else {
 519                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 520                 if (!compressed_llb)
 521                         goto err_fb;
 522
 523                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 524                                                   4096, 4096);
 525                 if (ret)
 526                         goto err_fb;
 527
 528                 fbc->compressed_llb = compressed_llb;
 529
 530                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 531                                                  fbc->compressed_fb.start,
 532                                                  U32_MAX));
 533                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 534                                                  fbc->compressed_llb->start,
 535                                                  U32_MAX));
 536                 intel_de_write(dev_priv, FBC_CFB_BASE,
 537                                dev_priv->dsm.start + fbc->compressed_fb.start);
 538                 intel_de_write(dev_priv, FBC_LL_BASE,
 539                                dev_priv->dsm.start + compressed_llb->start);
 540         }
 541
 542         drm_dbg_kms(&dev_priv->drm,
 543                     "reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 544                     fbc->compressed_fb.size, fbc->threshold);
 545
 546         return 0;
 547
 548 err_fb:
 549         kfree(compressed_llb);
 550         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 551 err_llb:
 552         if (drm_mm_initialized(&dev_priv->mm.stolen))
 553                 drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 554         return -ENOSPC;
 555 }
 556
 557 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 558 {
 559         struct intel_fbc *fbc = &dev_priv->fbc;
 560
 561         if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
 562                 return;
 563
 564         if (!drm_mm_node_allocated(&fbc->compressed_fb))
 565                 return;
 566
 567         if (fbc->compressed_llb) {
 568                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 569                 kfree(fbc->compressed_llb);
 570         }
 571
 572         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 573 }
 574
 575 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 576 {
 577         struct intel_fbc *fbc = &dev_priv->fbc;
 578
 579         if (!HAS_FBC(dev_priv))
 580                 return;
 581
 582         mutex_lock(&fbc->lock);
 583         __intel_fbc_cleanup_cfb(dev_priv);
 584         mutex_unlock(&fbc->lock);
 585 }
 586
 587 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 588                             u64 modifier, unsigned int stride)
 589 {
 590         /* This should have been caught earlier. */
 591         if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
 592                 return false;
 593
 594         /* Below are the additional FBC restrictions. */
 595         if (stride < 512)
 596                 return false;
 597
 598         if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
 599                 return stride == 4096 || stride == 8192;
 600
 601         if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
 602                 return false;
 603
 604         /* Display WA #1105: skl,bxt,kbl,cfl,glk */
 605         if (IS_GEN(dev_priv, 9) &&
 606             modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
 607                 return false;
 608
 609         if (stride > 16384)
 610                 return false;
 611
 612         return true;
 613 }
 614
 615 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 616                                   u32 pixel_format)
 617 {
 618         switch (pixel_format) {
 619         case DRM_FORMAT_XRGB8888:
 620         case DRM_FORMAT_XBGR8888:
 621                 return true;
 622         case DRM_FORMAT_XRGB1555:
 623         case DRM_FORMAT_RGB565:
 624                 /* 16bpp not supported on gen2 */
 625                 if (IS_GEN(dev_priv, 2))
 626                         return false;
 627                 /* WaFbcOnly1to1Ratio:ctg */
 628                 if (IS_G4X(dev_priv))
 629                         return false;
 630                 return true;
 631         default:
 632                 return false;
 633         }
 634 }
 635
 636 static bool rotation_is_valid(struct drm_i915_private *dev_priv,
 637                               u32 pixel_format, unsigned int rotation)
 638 {
 639         if (INTEL_GEN(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
 640             drm_rotation_90_or_270(rotation))
 641                 return false;
 642         else if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 643                  rotation != DRM_MODE_ROTATE_0)
 644                 return false;
 645
 646         return true;
 647 }
 648
 649 /*
 650  * For some reason, the hardware tracking starts looking at whatever we
 651  * programmed as the display plane base address register. It does not look at
 652  * the X and Y offset registers. That's why we include the src x/y offsets
 653  * instead of just looking at the plane size.
 654  */
 655 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 656 {
 657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 658         struct intel_fbc *fbc = &dev_priv->fbc;
 659         unsigned int effective_w, effective_h, max_w, max_h;
 660
 661         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 662                 max_w = 5120;
 663                 max_h = 4096;
 664         } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 665                 max_w = 4096;
 666                 max_h = 4096;
 667         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 668                 max_w = 4096;
 669                 max_h = 2048;
 670         } else {
 671                 max_w = 2048;
 672                 max_h = 1536;
 673         }
 674
 675         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 676                                         &effective_h);
 677         effective_w += fbc->state_cache.plane.adjusted_x;
 678         effective_h += fbc->state_cache.plane.adjusted_y;
 679
 680         return effective_w <= max_w && effective_h <= max_h;
 681 }
 682
 683 static bool tiling_is_valid(struct drm_i915_private *dev_priv,
 684                             uint64_t modifier)
 685 {
 686         switch (modifier) {
 687         case DRM_FORMAT_MOD_LINEAR:
 688                 if (INTEL_GEN(dev_priv) >= 9)
 689                         return true;
 690                 return false;
 691         case I915_FORMAT_MOD_X_TILED:
 692         case I915_FORMAT_MOD_Y_TILED:
 693                 return true;
 694         default:
 695                 return false;
 696         }
 697 }
 698
 699 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 700                                          const struct intel_crtc_state *crtc_state,
 701                                          const struct intel_plane_state *plane_state)
 702 {
 703         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 704         struct intel_fbc *fbc = &dev_priv->fbc;
 705         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 706         struct drm_framebuffer *fb = plane_state->hw.fb;
 707
 708         cache->plane.visible = plane_state->uapi.visible;
 709         if (!cache->plane.visible)
 710                 return;
 711
 712         cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
 713         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 714                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 715
 716         cache->plane.rotation = plane_state->hw.rotation;
 717         /*
 718          * Src coordinates are already rotated by 270 degrees for
 719          * the 90/270 degree plane rotation cases (to match the
 720          * GTT mapping), hence no need to account for rotation here.
 721          */
 722         cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 723         cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 724         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 725         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 726
 727         cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 728
 729         cache->fb.format = fb->format;
 730         cache->fb.modifier = fb->modifier;
 731
 732         /* FIXME is this correct? */
 733         cache->fb.stride = plane_state->color_plane[0].stride;
 734         if (drm_rotation_90_or_270(plane_state->hw.rotation))
 735                 cache->fb.stride *= fb->format->cpp[0];
 736
 737         /* FBC1 compression interval: arbitrary choice of 1 second */
 738         cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
 739
 740         cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
 741
 742         drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
 743                     !plane_state->vma->fence);
 744
 745         if (plane_state->flags & PLANE_HAS_FENCE &&
 746             plane_state->vma->fence)
 747                 cache->fence_id = plane_state->vma->fence->id;
 748         else
 749                 cache->fence_id = -1;
 750 }
 751
 752 static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
 753 {
 754         struct intel_fbc *fbc = &dev_priv->fbc;
 755
 756         return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 757                 fbc->compressed_fb.size * fbc->threshold;
 758 }
 759
 760 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 761 {
 762         struct intel_fbc *fbc = &dev_priv->fbc;
 763
 764         if (intel_vgpu_active(dev_priv)) {
 765                 fbc->no_fbc_reason = "VGPU is active";
 766                 return false;
 767         }
 768
 769         if (!dev_priv->params.enable_fbc) {
 770                 fbc->no_fbc_reason = "disabled per module param or by default";
 771                 return false;
 772         }
 773
 774         if (fbc->underrun_detected) {
 775                 fbc->no_fbc_reason = "underrun detected";
 776                 return false;
 777         }
 778
 779         return true;
 780 }
 781
 782 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 783 {
 784         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 785         struct intel_fbc *fbc = &dev_priv->fbc;
 786         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 787
 788         if (!intel_fbc_can_enable(dev_priv))
 789                 return false;
 790
 791         if (!cache->plane.visible) {
 792                 fbc->no_fbc_reason = "primary plane not visible";
 793                 return false;
 794         }
 795
 796         /* We don't need to use a state cache here since this information is
 797          * global for all CRTC.
 798          */
 799         if (fbc->underrun_detected) {
 800                 fbc->no_fbc_reason = "underrun detected";
 801                 return false;
 802         }
 803
 804         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 805                 fbc->no_fbc_reason = "incompatible mode";
 806                 return false;
 807         }
 808
 809         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 810                 fbc->no_fbc_reason = "mode too large for compression";
 811                 return false;
 812         }
 813
 814         /* The use of a CPU fence is one of two ways to detect writes by the
 815          * CPU to the scanout and trigger updates to the FBC.
 816          *
 817          * The other method is by software tracking (see
 818          * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
 819          * the current compressed buffer and recompress it.
 820          *
 821          * Note that is possible for a tiled surface to be unmappable (and
 822          * so have no fence associated with it) due to aperture constraints
 823          * at the time of pinning.
 824          *
 825          * FIXME with 90/270 degree rotation we should use the fence on
 826          * the normal GTT view (the rotated view doesn't even have a
 827          * fence). Would need changes to the FBC fence Y offset as well.
 828          * For now this will effectively disable FBC with 90/270 degree
 829          * rotation.
 830          */
 831         if (INTEL_GEN(dev_priv) < 9 && cache->fence_id < 0) {
 832                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 833                 return false;
 834         }
 835
 836         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 837                 fbc->no_fbc_reason = "pixel format is invalid";
 838                 return false;
 839         }
 840
 841         if (!rotation_is_valid(dev_priv, cache->fb.format->format,
 842                                cache->plane.rotation)) {
 843                 fbc->no_fbc_reason = "rotation unsupported";
 844                 return false;
 845         }
 846
 847         if (!tiling_is_valid(dev_priv, cache->fb.modifier)) {
 848                 fbc->no_fbc_reason = "tiling unsupported";
 849                 return false;
 850         }
 851
 852         if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
 853                 fbc->no_fbc_reason = "framebuffer stride not supported";
 854                 return false;
 855         }
 856
 857         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 858             cache->fb.format->has_alpha) {
 859                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 860                 return false;
 861         }
 862
 863         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 864         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 865             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 866                 fbc->no_fbc_reason = "pixel rate is too big";
 867                 return false;
 868         }
 869
 870         /* It is possible for the required CFB size change without a
 871          * crtc->disable + crtc->enable since it is possible to change the
 872          * stride without triggering a full modeset. Since we try to
 873          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 874          * if this happens, but if we exceed the current CFB size we'll have to
 875          * disable FBC. Notice that it would be possible to disable FBC, wait
 876          * for a frame, free the stolen node, then try to reenable FBC in case
 877          * we didn't get any invalidate/deactivate calls, but this would require
 878          * a lot of tracking just for a specific case. If we conclude it's an
 879          * important case, we can implement it later. */
 880         if (intel_fbc_cfb_size_changed(dev_priv)) {
 881                 fbc->no_fbc_reason = "CFB requirements changed";
 882                 return false;
 883         }
 884
 885         /*
 886          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 887          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 888          * and screen flicker.
 889          */
 890         if (INTEL_GEN(dev_priv) >= 9 &&
 891             (fbc->state_cache.plane.adjusted_y & 3)) {
 892                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 893                 return false;
 894         }
 895
 896         return true;
 897 }
 898
 899 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 900                                      struct intel_fbc_reg_params *params)
 901 {
 902         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 903         struct intel_fbc *fbc = &dev_priv->fbc;
 904         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 905
 906         /* Since all our fields are integer types, use memset here so the
 907          * comparison function can rely on memcmp because the padding will be
 908          * zero. */
 909         memset(params, 0, sizeof(*params));
 910
 911         params->fence_id = cache->fence_id;
 912         params->fence_y_offset = cache->fence_y_offset;
 913
 914         params->interval = cache->interval;
 915
 916         params->crtc.pipe = crtc->pipe;
 917         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 918
 919         params->fb.format = cache->fb.format;
 920         params->fb.stride = cache->fb.stride;
 921
 922         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 923
 924         params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
 925
 926         params->plane_visible = cache->plane.visible;
 927 }
 928
 929 static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
 930 {
 931         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 932         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 933         const struct intel_fbc *fbc = &dev_priv->fbc;
 934         const struct intel_fbc_state_cache *cache = &fbc->state_cache;
 935         const struct intel_fbc_reg_params *params = &fbc->params;
 936
 937         if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
 938                 return false;
 939
 940         if (!params->plane_visible)
 941                 return false;
 942
 943         if (!intel_fbc_can_activate(crtc))
 944                 return false;
 945
 946         if (params->fb.format != cache->fb.format)
 947                 return false;
 948
 949         if (params->fb.stride != cache->fb.stride)
 950                 return false;
 951
 952         if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
 953                 return false;
 954
 955         if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
 956                 return false;
 957
 958         return true;
 959 }
 960
 961 bool intel_fbc_pre_update(struct intel_atomic_state *state,
 962                           struct intel_crtc *crtc)
 963 {
 964         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 965         const struct intel_crtc_state *crtc_state =
 966                 intel_atomic_get_new_crtc_state(state, crtc);
 967         const struct intel_plane_state *plane_state =
 968                 intel_atomic_get_new_plane_state(state, plane);
 969         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 970         struct intel_fbc *fbc = &dev_priv->fbc;
 971         const char *reason = "update pending";
 972         bool need_vblank_wait = false;
 973
 974         if (!plane->has_fbc || !plane_state)
 975                 return need_vblank_wait;
 976
 977         mutex_lock(&fbc->lock);
 978
 979         if (fbc->crtc != crtc)
 980                 goto unlock;
 981
 982         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 983         fbc->flip_pending = true;
 984
 985         if (!intel_fbc_can_flip_nuke(crtc_state)) {
 986                 intel_fbc_deactivate(dev_priv, reason);
 987
 988                 /*
 989                  * Display WA #1198: glk+
 990                  * Need an extra vblank wait between FBC disable and most plane
 991                  * updates. Bspec says this is only needed for plane disable, but
 992                  * that is not true. Touching most plane registers will cause the
 993                  * corruption to appear. Also SKL/derivatives do not seem to be
 994                  * affected.
 995                  *
 996                  * TODO: could optimize this a bit by sampling the frame
 997                  * counter when we disable FBC (if it was already done earlier)
 998                  * and skipping the extra vblank wait before the plane update
 999                  * if at least one frame has already passed.
1000                  */
1001                 if (fbc->activated &&
1002                     (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
1003                         need_vblank_wait = true;
1004                 fbc->activated = false;
1005         }
1006 unlock:
1007         mutex_unlock(&fbc->lock);
1008
1009         return need_vblank_wait;
1010 }
1011
1012 /**
1013  * __intel_fbc_disable - disable FBC
1014  * @dev_priv: i915 device instance
1015  *
1016  * This is the low level function that actually disables FBC. Callers should
1017  * grab the FBC lock.
1018  */
1019 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1020 {
1021         struct intel_fbc *fbc = &dev_priv->fbc;
1022         struct intel_crtc *crtc = fbc->crtc;
1023
1024         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1025         drm_WARN_ON(&dev_priv->drm, !fbc->crtc);
1026         drm_WARN_ON(&dev_priv->drm, fbc->active);
1027
1028         drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n",
1029                     pipe_name(crtc->pipe));
1030
1031         __intel_fbc_cleanup_cfb(dev_priv);
1032
1033         fbc->crtc = NULL;
1034 }
1035
1036 static void __intel_fbc_post_update(struct intel_crtc *crtc)
1037 {
1038         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1039         struct intel_fbc *fbc = &dev_priv->fbc;
1040
1041         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1042
1043         if (fbc->crtc != crtc)
1044                 return;
1045
1046         fbc->flip_pending = false;
1047
1048         if (!dev_priv->params.enable_fbc) {
1049                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
1050                 __intel_fbc_disable(dev_priv);
1051
1052                 return;
1053         }
1054
1055         intel_fbc_get_reg_params(crtc, &fbc->params);
1056
1057         if (!intel_fbc_can_activate(crtc))
1058                 return;
1059
1060         if (!fbc->busy_bits)
1061                 intel_fbc_hw_activate(dev_priv);
1062         else
1063                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1064 }
1065
1066 void intel_fbc_post_update(struct intel_atomic_state *state,
1067                            struct intel_crtc *crtc)
1068 {
1069         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1070         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1071         const struct intel_plane_state *plane_state =
1072                 intel_atomic_get_new_plane_state(state, plane);
1073         struct intel_fbc *fbc = &dev_priv->fbc;
1074
1075         if (!plane->has_fbc || !plane_state)
1076                 return;
1077
1078         mutex_lock(&fbc->lock);
1079         __intel_fbc_post_update(crtc);
1080         mutex_unlock(&fbc->lock);
1081 }
1082
1083 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1084 {
1085         if (fbc->crtc)
1086                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1087         else
1088                 return fbc->possible_framebuffer_bits;
1089 }
1090
1091 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1092                           unsigned int frontbuffer_bits,
1093                           enum fb_op_origin origin)
1094 {
1095         struct intel_fbc *fbc = &dev_priv->fbc;
1096
1097         if (!HAS_FBC(dev_priv))
1098                 return;
1099
1100         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1101                 return;
1102
1103         mutex_lock(&fbc->lock);
1104
1105         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1106
1107         if (fbc->crtc && fbc->busy_bits)
1108                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1109
1110         mutex_unlock(&fbc->lock);
1111 }
1112
1113 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1114                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1115 {
1116         struct intel_fbc *fbc = &dev_priv->fbc;
1117
1118         if (!HAS_FBC(dev_priv))
1119                 return;
1120
1121         /*
1122          * GTT tracking does not nuke the entire cfb
1123          * so don't clear busy_bits set for some other
1124          * reason.
1125          */
1126         if (origin == ORIGIN_GTT)
1127                 return;
1128
1129         mutex_lock(&fbc->lock);
1130
1131         fbc->busy_bits &= ~frontbuffer_bits;
1132
1133         if (origin == ORIGIN_FLIP)
1134                 goto out;
1135
1136         if (!fbc->busy_bits && fbc->crtc &&
1137             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1138                 if (fbc->active)
1139                         intel_fbc_recompress(dev_priv);
1140                 else if (!fbc->flip_pending)
1141                         __intel_fbc_post_update(fbc->crtc);
1142         }
1143
1144 out:
1145         mutex_unlock(&fbc->lock);
1146 }
1147
1148 /**
1149  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1150  * @dev_priv: i915 device instance
1151  * @state: the atomic state structure
1152  *
1153  * This function looks at the proposed state for CRTCs and planes, then chooses
1154  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1155  * true.
1156  *
1157  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1158  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1159  */
1160 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1161                            struct intel_atomic_state *state)
1162 {
1163         struct intel_fbc *fbc = &dev_priv->fbc;
1164         struct intel_plane *plane;
1165         struct intel_plane_state *plane_state;
1166         bool crtc_chosen = false;
1167         int i;
1168
1169         mutex_lock(&fbc->lock);
1170
1171         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1172         if (fbc->crtc &&
1173             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1174                 goto out;
1175
1176         if (!intel_fbc_can_enable(dev_priv))
1177                 goto out;
1178
1179         /* Simply choose the first CRTC that is compatible and has a visible
1180          * plane. We could go for fancier schemes such as checking the plane
1181          * size, but this would just affect the few platforms that don't tie FBC
1182          * to pipe or plane A. */
1183         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1184                 struct intel_crtc_state *crtc_state;
1185                 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1186
1187                 if (!plane->has_fbc)
1188                         continue;
1189
1190                 if (!plane_state->uapi.visible)
1191                         continue;
1192
1193                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1194
1195                 crtc_state->enable_fbc = true;
1196                 crtc_chosen = true;
1197                 break;
1198         }
1199
1200         if (!crtc_chosen)
1201                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1202
1203 out:
1204         mutex_unlock(&fbc->lock);
1205 }
1206
1207 /**
1208  * intel_fbc_enable: tries to enable FBC on the CRTC
1209  * @crtc: the CRTC
1210  * @state: corresponding &drm_crtc_state for @crtc
1211  *
1212  * This function checks if the given CRTC was chosen for FBC, then enables it if
1213  * possible. Notice that it doesn't activate FBC. It is valid to call
1214  * intel_fbc_enable multiple times for the same pipe without an
1215  * intel_fbc_disable in the middle, as long as it is deactivated.
1216  */
1217 void intel_fbc_enable(struct intel_atomic_state *state,
1218                       struct intel_crtc *crtc)
1219 {
1220         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1221         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1222         const struct intel_crtc_state *crtc_state =
1223                 intel_atomic_get_new_crtc_state(state, crtc);
1224         const struct intel_plane_state *plane_state =
1225                 intel_atomic_get_new_plane_state(state, plane);
1226         struct intel_fbc *fbc = &dev_priv->fbc;
1227         struct intel_fbc_state_cache *cache = &fbc->state_cache;
1228
1229         if (!plane->has_fbc || !plane_state)
1230                 return;
1231
1232         mutex_lock(&fbc->lock);
1233
1234         if (fbc->crtc) {
1235                 if (fbc->crtc != crtc ||
1236                     !intel_fbc_cfb_size_changed(dev_priv))
1237                         goto out;
1238
1239                 __intel_fbc_disable(dev_priv);
1240         }
1241
1242         drm_WARN_ON(&dev_priv->drm, fbc->active);
1243
1244         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1245
1246         /* FIXME crtc_state->enable_fbc lies :( */
1247         if (!cache->plane.visible)
1248                 goto out;
1249
1250         if (intel_fbc_alloc_cfb(dev_priv,
1251                                 intel_fbc_calculate_cfb_size(dev_priv, cache),
1252                                 plane_state->hw.fb->format->cpp[0])) {
1253                 cache->plane.visible = false;
1254                 fbc->no_fbc_reason = "not enough stolen memory";
1255                 goto out;
1256         }
1257
1258         if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
1259             plane_state->hw.fb->modifier != I915_FORMAT_MOD_X_TILED)
1260                 cache->gen9_wa_cfb_stride =
1261                         DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
1262         else
1263                 cache->gen9_wa_cfb_stride = 0;
1264
1265         drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
1266                     pipe_name(crtc->pipe));
1267         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1268
1269         fbc->crtc = crtc;
1270 out:
1271         mutex_unlock(&fbc->lock);
1272 }
1273
1274 /**
1275  * intel_fbc_disable - disable FBC if it's associated with crtc
1276  * @crtc: the CRTC
1277  *
1278  * This function disables FBC if it's associated with the provided CRTC.
1279  */
1280 void intel_fbc_disable(struct intel_crtc *crtc)
1281 {
1282         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1283         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1284         struct intel_fbc *fbc = &dev_priv->fbc;
1285
1286         if (!plane->has_fbc)
1287                 return;
1288
1289         mutex_lock(&fbc->lock);
1290         if (fbc->crtc == crtc)
1291                 __intel_fbc_disable(dev_priv);
1292         mutex_unlock(&fbc->lock);
1293 }
1294
1295 /**
1296  * intel_fbc_global_disable - globally disable FBC
1297  * @dev_priv: i915 device instance
1298  *
1299  * This function disables FBC regardless of which CRTC is associated with it.
1300  */
1301 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1302 {
1303         struct intel_fbc *fbc = &dev_priv->fbc;
1304
1305         if (!HAS_FBC(dev_priv))
1306                 return;
1307
1308         mutex_lock(&fbc->lock);
1309         if (fbc->crtc) {
1310                 drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);
1311                 __intel_fbc_disable(dev_priv);
1312         }
1313         mutex_unlock(&fbc->lock);
1314 }
1315
1316 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1317 {
1318         struct drm_i915_private *dev_priv =
1319                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1320         struct intel_fbc *fbc = &dev_priv->fbc;
1321
1322         mutex_lock(&fbc->lock);
1323
1324         /* Maybe we were scheduled twice. */
1325         if (fbc->underrun_detected || !fbc->crtc)
1326                 goto out;
1327
1328         drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n");
1329         fbc->underrun_detected = true;
1330
1331         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1332 out:
1333         mutex_unlock(&fbc->lock);
1334 }
1335
1336 /*
1337  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1338  * @dev_priv: i915 device instance
1339  *
1340  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1341  * want to re-enable FBC after an underrun to increase test coverage.
1342  */
1343 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1344 {
1345         int ret;
1346
1347         cancel_work_sync(&dev_priv->fbc.underrun_work);
1348
1349         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1350         if (ret)
1351                 return ret;
1352
1353         if (dev_priv->fbc.underrun_detected) {
1354                 drm_dbg_kms(&dev_priv->drm,
1355                             "Re-allowing FBC after fifo underrun\n");
1356                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1357         }
1358
1359         dev_priv->fbc.underrun_detected = false;
1360         mutex_unlock(&dev_priv->fbc.lock);
1361
1362         return 0;
1363 }
1364
1365 /**
1366  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1367  * @dev_priv: i915 device instance
1368  *
1369  * Without FBC, most underruns are harmless and don't really cause too many
1370  * problems, except for an annoying message on dmesg. With FBC, underruns can
1371  * become black screens or even worse, especially when paired with bad
1372  * watermarks. So in order for us to be on the safe side, completely disable FBC
1373  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1374  * already suggests that watermarks may be bad, so try to be as safe as
1375  * possible.
1376  *
1377  * This function is called from the IRQ handler.
1378  */
1379 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1380 {
1381         struct intel_fbc *fbc = &dev_priv->fbc;
1382
1383         if (!HAS_FBC(dev_priv))
1384                 return;
1385
1386         /* There's no guarantee that underrun_detected won't be set to true
1387          * right after this check and before the work is scheduled, but that's
1388          * not a problem since we'll check it again under the work function
1389          * while FBC is locked. This check here is just to prevent us from
1390          * unnecessarily scheduling the work, and it relies on the fact that we
1391          * never switch underrun_detect back to false after it's true. */
1392         if (READ_ONCE(fbc->underrun_detected))
1393                 return;
1394
1395         schedule_work(&fbc->underrun_work);
1396 }
1397
1398 /*
1399  * The DDX driver changes its behavior depending on the value it reads from
1400  * i915.enable_fbc, so sanitize it by translating the default value into either
1401  * 0 or 1 in order to allow it to know what's going on.
1402  *
1403  * Notice that this is done at driver initialization and we still allow user
1404  * space to change the value during runtime without sanitizing it again. IGT
1405  * relies on being able to change i915.enable_fbc at runtime.
1406  */
1407 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1408 {
1409         if (dev_priv->params.enable_fbc >= 0)
1410                 return !!dev_priv->params.enable_fbc;
1411
1412         if (!HAS_FBC(dev_priv))
1413                 return 0;
1414
1415         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1416                 return 1;
1417
1418         return 0;
1419 }
1420
1421 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1422 {
1423         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1424         if (intel_vtd_active() &&
1425             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1426                 drm_info(&dev_priv->drm,
1427                          "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1428                 return true;
1429         }
1430
1431         return false;
1432 }
1433
1434 /**
1435  * intel_fbc_init - Initialize FBC
1436  * @dev_priv: the i915 device
1437  *
1438  * This function might be called during PM init process.
1439  */
1440 void intel_fbc_init(struct drm_i915_private *dev_priv)
1441 {
1442         struct intel_fbc *fbc = &dev_priv->fbc;
1443
1444         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1445         mutex_init(&fbc->lock);
1446         fbc->active = false;
1447
1448         if (!drm_mm_initialized(&dev_priv->mm.stolen))
1449                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1450
1451         if (need_fbc_vtd_wa(dev_priv))
1452                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1453
1454         dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1455         drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n",
1456                     dev_priv->params.enable_fbc);
1457
1458         if (!HAS_FBC(dev_priv)) {
1459                 fbc->no_fbc_reason = "unsupported by this chipset";
1460                 return;
1461         }
1462
1463         /* We still don't have any sort of hardware state readout for FBC, so
1464          * deactivate it in case the BIOS activated it to make sure software
1465          * matches the hardware state. */
1466         if (intel_fbc_hw_is_active(dev_priv))
1467                 intel_fbc_hw_deactivate(dev_priv);
1468 }