1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021 Intel Corporation
7 * DOC: display pinning helpers
10 #include "gem/i915_gem_domain.h"
11 #include "gem/i915_gem_object.h"
14 #include "intel_display_types.h"
15 #include "intel_dpt.h"
17 #include "intel_fb_pin.h"
19 static struct i915_vma *
20 intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
21 const struct i915_ggtt_view *view,
23 unsigned long *out_flags,
24 struct i915_address_space *vm)
26 struct drm_device *dev = fb->dev;
27 struct drm_i915_private *dev_priv = to_i915(dev);
28 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
33 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
34 return ERR_PTR(-EINVAL);
36 alignment = 4096 * 512;
38 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
40 ret = i915_gem_object_lock_interruptible(obj, NULL);
42 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
43 i915_gem_object_unlock(obj);
50 vma = i915_vma_instance(obj, vm, view);
54 if (i915_vma_misplaced(vma, 0, alignment, 0)) {
55 ret = i915_vma_unbind_unlocked(vma);
62 ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
68 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
70 i915_gem_object_flush_if_display(obj);
74 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
80 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
82 const struct i915_ggtt_view *view,
84 unsigned long *out_flags)
86 struct drm_device *dev = fb->dev;
87 struct drm_i915_private *dev_priv = to_i915(dev);
88 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
89 intel_wakeref_t wakeref;
90 struct i915_gem_ww_ctx ww;
96 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
97 return ERR_PTR(-EINVAL);
100 alignment = intel_cursor_alignment(dev_priv);
102 alignment = intel_surf_alignment(fb, 0);
103 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
104 return ERR_PTR(-EINVAL);
106 /* Note that the w/a also requires 64 PTE of padding following the
107 * bo. We currently fill all unused PTE with the shadow page and so
108 * we should always have valid PTE following the scanout preventing
111 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
112 alignment = 256 * 1024;
115 * Global gtt pte registers are special registers which actually forward
116 * writes to a chunk of system memory. Which means that there is no risk
117 * that the register values disappear as soon as we call
118 * intel_runtime_pm_put(), so it is correct to wrap only the
119 * pin/unpin/fence and not more.
121 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
123 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
126 * Valleyview is definitely limited to scanning out the first
127 * 512MiB. Lets presume this behaviour was inherited from the
128 * g4x display engine and that all earlier gen are similarly
129 * limited. Testing suggests that it is a little more
130 * complicated than this. For example, Cherryview appears quite
131 * happy to scanout from anywhere within its global aperture.
134 if (HAS_GMCH(dev_priv))
135 pinctl |= PIN_MAPPABLE;
137 i915_gem_ww_ctx_init(&ww, true);
139 ret = i915_gem_object_lock(obj, &ww);
140 if (!ret && phys_cursor)
141 ret = i915_gem_object_attach_phys(obj, alignment);
142 else if (!ret && HAS_LMEM(dev_priv))
143 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM);
144 /* TODO: Do we need to sync when migration becomes async? */
146 ret = i915_gem_object_pin_pages(obj);
150 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
157 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
159 * Install a fence for tiled scan-out. Pre-i965 always needs a
160 * fence, whereas 965+ only requires a fence if using
161 * framebuffer compression. For simplicity, we always, when
162 * possible, install a fence as the cost is not that onerous.
164 * If we fail to fence the tiled scanout, then either the
165 * modeset will reject the change (which is highly unlikely as
166 * the affected systems, all but one, do not have unmappable
167 * space) or we will not be able to enable full powersaving
168 * techniques (also likely not to apply due to various limits
169 * FBC and the like impose on the size of the buffer, which
170 * presumably we violated anyway with this unmappable buffer).
171 * Anyway, it is presumably better to stumble onwards with
172 * something and try to run the system in a "less than optimal"
173 * mode that matches the user configuration.
175 ret = i915_vma_pin_fence(vma);
176 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
183 *out_flags |= PLANE_HAS_FENCE;
189 i915_gem_object_unpin_pages(obj);
191 if (ret == -EDEADLK) {
192 ret = i915_gem_ww_ctx_backoff(&ww);
196 i915_gem_ww_ctx_fini(&ww);
200 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
201 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
205 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
207 if (flags & PLANE_HAS_FENCE)
208 i915_vma_unpin_fence(vma);
213 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
215 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
216 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
217 struct drm_framebuffer *fb = plane_state->hw.fb;
218 struct i915_vma *vma;
220 plane->id == PLANE_CURSOR &&
221 INTEL_INFO(dev_priv)->display.cursor_needs_physical;
223 if (!intel_fb_uses_dpt(fb)) {
224 vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
225 &plane_state->view.gtt,
226 intel_plane_uses_fence(plane_state),
227 &plane_state->flags);
231 plane_state->ggtt_vma = vma;
233 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
235 vma = intel_dpt_pin(intel_fb->dpt_vm);
239 plane_state->ggtt_vma = vma;
241 vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
242 &plane_state->flags, intel_fb->dpt_vm);
244 intel_dpt_unpin(intel_fb->dpt_vm);
245 plane_state->ggtt_vma = NULL;
249 plane_state->dpt_vma = vma;
251 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
257 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
259 struct drm_framebuffer *fb = old_plane_state->hw.fb;
260 struct i915_vma *vma;
262 if (!intel_fb_uses_dpt(fb)) {
263 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
265 intel_unpin_fb_vma(vma, old_plane_state->flags);
267 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
269 vma = fetch_and_zero(&old_plane_state->dpt_vma);
271 intel_unpin_fb_vma(vma, old_plane_state->flags);
273 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
275 intel_dpt_unpin(intel_fb->dpt_vm);