2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
27 #include <linux/gpio/consumer.h>
28 #include <linux/gpio/machine.h>
29 #include <linux/mfd/intel_soc_pmic.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/machine.h>
32 #include <linux/slab.h>
34 #include <asm/intel-mid.h>
35 #include <asm/unaligned.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_edid.h>
40 #include <video/mipi_display.h>
43 #include "intel_display_types.h"
44 #include "intel_dsi.h"
45 #include "intel_sideband.h"
47 #define MIPI_TRANSFER_MODE_SHIFT 0
48 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
49 #define MIPI_PORT_SHIFT 3
51 /* base offsets for gpio pads */
52 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
53 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
54 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
55 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
56 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
57 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
58 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
59 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
60 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
61 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
62 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
63 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
65 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
66 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
73 static struct gpio_map vlv_gpio_table[] = {
74 { VLV_GPIO_NC_0_HV_DDI0_HPD },
75 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
76 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
77 { VLV_GPIO_NC_3_PANEL0_VDDEN },
78 { VLV_GPIO_NC_4_PANEL0_BKLTEN },
79 { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
80 { VLV_GPIO_NC_6_HV_DDI1_HPD },
81 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
82 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
83 { VLV_GPIO_NC_9_PANEL1_VDDEN },
84 { VLV_GPIO_NC_10_PANEL1_BKLTEN },
85 { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
88 struct i2c_adapter_lookup {
90 struct intel_dsi *intel_dsi;
91 acpi_handle dev_handle;
94 #define CHV_GPIO_IDX_START_N 0
95 #define CHV_GPIO_IDX_START_E 73
96 #define CHV_GPIO_IDX_START_SW 100
97 #define CHV_GPIO_IDX_START_SE 198
99 #define CHV_VBT_MAX_PINS_PER_FMLY 15
101 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
102 #define CHV_GPIO_GPIOEN (1 << 15)
103 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
104 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
105 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
106 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
107 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
109 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
110 #define CHV_GPIO_CFGLOCK (1 << 31)
112 /* ICL DSI Display GPIO Pins */
113 #define ICL_GPIO_DDSP_HPD_A 0
114 #define ICL_GPIO_L_VDDEN_1 1
115 #define ICL_GPIO_L_BKLTEN_1 2
116 #define ICL_GPIO_DDPA_CTRLCLK_1 3
117 #define ICL_GPIO_DDPA_CTRLDATA_1 4
118 #define ICL_GPIO_DDSP_HPD_B 5
119 #define ICL_GPIO_L_VDDEN_2 6
120 #define ICL_GPIO_L_BKLTEN_2 7
121 #define ICL_GPIO_DDPA_CTRLCLK_2 8
122 #define ICL_GPIO_DDPA_CTRLDATA_2 9
124 static inline enum port intel_dsi_seq_port_to_port(u8 port)
126 return port ? PORT_C : PORT_A;
129 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
132 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
133 struct mipi_dsi_device *dsi_device;
134 u8 type, flags, seq_port;
138 drm_dbg_kms(&dev_priv->drm, "\n");
143 len = *((u16 *) data);
146 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
148 /* For DSI single link on Port A & C, the seq_port value which is
149 * parsed from Sequence Block#53 of VBT has been set to 0
150 * Now, read/write of packets for the DSI single link on Port A and
151 * Port C will based on the DVO port from VBT block 2.
153 if (intel_dsi->ports == (1 << PORT_C))
156 port = intel_dsi_seq_port_to_port(seq_port);
158 dsi_device = intel_dsi->dsi_hosts[port]->device;
160 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
165 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
166 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
168 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
170 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
173 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
174 mipi_dsi_generic_write(dsi_device, NULL, 0);
176 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
177 mipi_dsi_generic_write(dsi_device, data, 1);
179 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
180 mipi_dsi_generic_write(dsi_device, data, 2);
182 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
183 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
184 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
185 drm_dbg(&dev_priv->drm,
186 "Generic Read not yet implemented or used\n");
188 case MIPI_DSI_GENERIC_LONG_WRITE:
189 mipi_dsi_generic_write(dsi_device, data, len);
191 case MIPI_DSI_DCS_SHORT_WRITE:
192 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
194 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
195 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
197 case MIPI_DSI_DCS_READ:
198 drm_dbg(&dev_priv->drm,
199 "DCS Read not yet implemented or used\n");
201 case MIPI_DSI_DCS_LONG_WRITE:
202 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
206 if (INTEL_GEN(dev_priv) < 11)
207 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
215 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
217 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
218 u32 delay = *((const u32 *) data);
220 drm_dbg_kms(&i915->drm, "\n");
222 usleep_range(delay, delay + 10);
228 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
229 u8 gpio_source, u8 gpio_index, bool value)
231 struct gpio_map *map;
236 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
237 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",
242 map = &vlv_gpio_table[gpio_index];
244 if (dev_priv->vbt.dsi.seq_version >= 3) {
245 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
246 port = IOSF_PORT_GPIO_NC;
248 if (gpio_source == 0) {
249 port = IOSF_PORT_GPIO_NC;
250 } else if (gpio_source == 1) {
251 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
254 drm_dbg_kms(&dev_priv->drm,
255 "unknown gpio source %u\n", gpio_source);
260 pconf0 = VLV_GPIO_PCONF0(map->base_offset);
261 padval = VLV_GPIO_PAD_VAL(map->base_offset);
263 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
265 /* FIXME: remove constant below */
266 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
271 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
272 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
275 static void chv_exec_gpio(struct drm_i915_private *dev_priv,
276 u8 gpio_source, u8 gpio_index, bool value)
282 if (dev_priv->vbt.dsi.seq_version >= 3) {
283 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
284 /* XXX: it's unclear whether 255->57 is part of SE. */
285 gpio_index -= CHV_GPIO_IDX_START_SE;
286 port = CHV_IOSF_PORT_GPIO_SE;
287 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
288 gpio_index -= CHV_GPIO_IDX_START_SW;
289 port = CHV_IOSF_PORT_GPIO_SW;
290 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
291 gpio_index -= CHV_GPIO_IDX_START_E;
292 port = CHV_IOSF_PORT_GPIO_E;
294 port = CHV_IOSF_PORT_GPIO_N;
297 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
298 if (gpio_source != 0) {
299 drm_dbg_kms(&dev_priv->drm,
300 "unknown gpio source %u\n", gpio_source);
304 if (gpio_index >= CHV_GPIO_IDX_START_E) {
305 drm_dbg_kms(&dev_priv->drm,
306 "invalid gpio index %u for GPIO N\n",
311 port = CHV_IOSF_PORT_GPIO_N;
314 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
315 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
317 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
318 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
320 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
321 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
322 vlv_iosf_sb_write(dev_priv, port, cfg0,
323 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
324 CHV_GPIO_GPIOTXSTATE(value));
325 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
328 static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
329 u8 gpio_source, u8 gpio_index, bool value)
331 /* XXX: this table is a quick ugly hack. */
332 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
333 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
336 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
338 value ? GPIOD_OUT_LOW :
341 if (IS_ERR_OR_NULL(gpio_desc)) {
342 drm_err(&dev_priv->drm,
343 "GPIO index %u request failed (%ld)\n",
344 gpio_index, PTR_ERR(gpio_desc));
348 bxt_gpio_table[gpio_index] = gpio_desc;
351 gpiod_set_value(gpio_desc, value);
354 static void icl_exec_gpio(struct drm_i915_private *dev_priv,
355 u8 gpio_source, u8 gpio_index, bool value)
357 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
360 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
362 struct drm_device *dev = intel_dsi->base.base.dev;
363 struct drm_i915_private *dev_priv = to_i915(dev);
364 u8 gpio_source, gpio_index = 0, gpio_number;
367 drm_dbg_kms(&dev_priv->drm, "\n");
369 if (dev_priv->vbt.dsi.seq_version >= 3)
370 gpio_index = *data++;
372 gpio_number = *data++;
374 /* gpio source in sequence v2 only */
375 if (dev_priv->vbt.dsi.seq_version == 2)
376 gpio_source = (*data >> 1) & 3;
383 if (INTEL_GEN(dev_priv) >= 11)
384 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
385 else if (IS_VALLEYVIEW(dev_priv))
386 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
387 else if (IS_CHERRYVIEW(dev_priv))
388 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
390 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
396 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
398 struct i2c_adapter_lookup *lookup = data;
399 struct intel_dsi *intel_dsi = lookup->intel_dsi;
400 struct acpi_resource_i2c_serialbus *sb;
401 struct i2c_adapter *adapter;
402 acpi_handle adapter_handle;
405 if (!i2c_acpi_get_i2c_resource(ares, &sb))
408 if (lookup->slave_addr != sb->slave_address)
411 status = acpi_get_handle(lookup->dev_handle,
412 sb->resource_source.string_ptr,
414 if (ACPI_FAILURE(status))
417 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
419 intel_dsi->i2c_bus_num = adapter->nr;
424 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
425 const u16 slave_addr)
427 struct drm_device *drm_dev = intel_dsi->base.base.dev;
428 struct device *dev = &drm_dev->pdev->dev;
429 struct acpi_device *acpi_dev;
430 struct list_head resource_list;
431 struct i2c_adapter_lookup lookup;
433 acpi_dev = ACPI_COMPANION(dev);
435 memset(&lookup, 0, sizeof(lookup));
436 lookup.slave_addr = slave_addr;
437 lookup.intel_dsi = intel_dsi;
438 lookup.dev_handle = acpi_device_handle(acpi_dev);
440 INIT_LIST_HEAD(&resource_list);
441 acpi_dev_get_resources(acpi_dev, &resource_list,
444 acpi_dev_free_resource_list(&resource_list);
448 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
449 const u16 slave_addr)
454 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
456 struct drm_device *drm_dev = intel_dsi->base.base.dev;
457 struct device *dev = &drm_dev->pdev->dev;
458 struct i2c_adapter *adapter;
461 u8 vbt_i2c_bus_num = *(data + 2);
462 u16 slave_addr = *(u16 *)(data + 3);
463 u8 reg_offset = *(data + 5);
464 u8 payload_size = *(data + 6);
467 if (intel_dsi->i2c_bus_num < 0) {
468 intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
469 i2c_acpi_find_adapter(intel_dsi, slave_addr);
472 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
474 DRM_DEV_ERROR(dev, "Cannot find a valid i2c bus for xfer\n");
478 payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
482 payload_data[0] = reg_offset;
483 memcpy(&payload_data[1], (data + 7), payload_size);
485 msg.addr = slave_addr;
487 msg.len = payload_size + 1;
488 msg.buf = payload_data;
490 ret = i2c_transfer(adapter, &msg, 1);
493 "Failed to xfer payload of size (%u) to reg (%u)\n",
494 payload_size, reg_offset);
498 i2c_put_adapter(adapter);
500 return data + payload_size + 7;
503 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
505 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
507 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
509 return data + *(data + 5) + 6;
512 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
514 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
515 #ifdef CONFIG_PMIC_OPREGION
516 u32 value, mask, reg_address;
520 /* byte 0 aka PMIC Flag is reserved */
521 i2c_address = get_unaligned_le16(data + 1);
522 reg_address = get_unaligned_le32(data + 3);
523 value = get_unaligned_le32(data + 7);
524 mask = get_unaligned_le32(data + 11);
526 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
530 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
533 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
539 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
541 static const fn_mipi_elem_exec exec_elem[] = {
542 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
543 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
544 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
545 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
546 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
547 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
551 * MIPI Sequence from VBT #53 parsing logic
552 * We have already separated each seqence during bios parsing
553 * Following is generic execution function for any sequence
556 static const char * const seq_name[] = {
557 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
558 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
559 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
560 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
561 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
562 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
563 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
564 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
565 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
566 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
567 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
570 static const char *sequence_name(enum mipi_seq seq_id)
572 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
573 return seq_name[seq_id];
578 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
579 enum mipi_seq seq_id)
581 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
583 fn_mipi_elem_exec mipi_elem_exec;
585 if (drm_WARN_ON(&dev_priv->drm,
586 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
589 data = dev_priv->vbt.dsi.sequence[seq_id];
593 drm_WARN_ON(&dev_priv->drm, *data != seq_id);
595 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
596 seq_id, sequence_name(seq_id));
598 /* Skip Sequence Byte. */
601 /* Skip Size of Sequence. */
602 if (dev_priv->vbt.dsi.seq_version >= 3)
606 u8 operation_byte = *data++;
607 u8 operation_size = 0;
609 if (operation_byte == MIPI_SEQ_ELEM_END)
612 if (operation_byte < ARRAY_SIZE(exec_elem))
613 mipi_elem_exec = exec_elem[operation_byte];
615 mipi_elem_exec = NULL;
617 /* Size of Operation. */
618 if (dev_priv->vbt.dsi.seq_version >= 3)
619 operation_size = *data++;
621 if (mipi_elem_exec) {
622 const u8 *next = data + operation_size;
624 data = mipi_elem_exec(intel_dsi, data);
626 /* Consistency check if we have size. */
627 if (operation_size && data != next) {
628 drm_err(&dev_priv->drm,
629 "Inconsistent operation size\n");
632 } else if (operation_size) {
633 /* We have size, skip. */
634 drm_dbg_kms(&dev_priv->drm,
635 "Unsupported MIPI operation byte %u\n",
637 data += operation_size;
639 /* No size, can't skip without parsing. */
640 drm_err(&dev_priv->drm,
641 "Unsupported MIPI operation byte %u\n",
648 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
649 enum mipi_seq seq_id)
651 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
652 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
653 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
654 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
656 intel_dsi_vbt_exec(intel_dsi, seq_id);
658 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
659 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
660 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
661 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
664 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
666 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
668 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
669 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
675 void intel_dsi_log_params(struct intel_dsi *intel_dsi)
677 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
679 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
680 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
681 intel_dsi->pixel_overlap);
682 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
683 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
684 drm_dbg_kms(&i915->drm, "Video mode format %s\n",
685 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
686 "non-burst with sync pulse" :
687 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
688 "non-burst with sync events" :
689 intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
690 "burst" : "<unknown>");
691 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
692 intel_dsi->burst_mode_ratio);
693 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
694 drm_dbg_kms(&i915->drm, "Eot %s\n",
695 enableddisabled(intel_dsi->eotp_pkt));
696 drm_dbg_kms(&i915->drm, "Clockstop %s\n",
697 enableddisabled(!intel_dsi->clock_stop));
698 drm_dbg_kms(&i915->drm, "Mode %s\n",
699 intel_dsi->operation_mode ? "command" : "video");
700 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
701 drm_dbg_kms(&i915->drm,
702 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
703 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
704 drm_dbg_kms(&i915->drm,
705 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
707 drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
708 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
709 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
710 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
711 intel_dsi->lp_rx_timeout);
712 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
713 intel_dsi->turn_arnd_val);
714 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
715 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
716 intel_dsi->hs_to_lp_count);
717 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
718 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
719 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
720 intel_dsi->clk_lp_to_hs_count);
721 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
722 intel_dsi->clk_hs_to_lp_count);
723 drm_dbg_kms(&i915->drm, "BTA %s\n",
724 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
727 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
729 struct drm_device *dev = intel_dsi->base.base.dev;
730 struct drm_i915_private *dev_priv = to_i915(dev);
731 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
732 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
733 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
734 u16 burst_mode_ratio;
737 drm_dbg_kms(&dev_priv->drm, "\n");
739 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
740 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
741 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
742 intel_dsi->pixel_format =
743 pixel_format_from_register_bits(
744 mipi_config->videomode_color_format << 7);
746 intel_dsi->dual_link = mipi_config->dual_link;
747 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
748 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
749 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
750 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
751 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
752 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
753 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
754 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
755 intel_dsi->init_count = mipi_config->master_init_timer;
756 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
757 intel_dsi->video_frmt_cfg_bits =
758 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
759 intel_dsi->bgr_enabled = mipi_config->rgb_flip;
761 /* Starting point, adjusted depending on dual link and burst mode */
762 intel_dsi->pclk = mode->clock;
764 /* In dual link mode each port needs half of pixel clock */
765 if (intel_dsi->dual_link) {
766 intel_dsi->pclk /= 2;
768 /* we can enable pixel_overlap if needed by panel. In this
769 * case we need to increase the pixelclock for extra pixels
771 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
772 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
777 * Target ddr frequency from VBT / non burst ddr freq
778 * multiply by 100 to preserve remainder
780 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
781 if (mipi_config->target_burst_mode_freq) {
782 u32 bitrate = intel_dsi_bitrate(intel_dsi);
785 * Sometimes the VBT contains a slightly lower clock,
786 * then the bitrate we have calculated, in this case
787 * just replace it with the calculated bitrate.
789 if (mipi_config->target_burst_mode_freq < bitrate &&
790 intel_fuzzy_clock_check(
791 mipi_config->target_burst_mode_freq,
793 mipi_config->target_burst_mode_freq = bitrate;
795 if (mipi_config->target_burst_mode_freq < bitrate) {
796 drm_err(&dev_priv->drm,
797 "Burst mode freq is less than computed\n");
801 burst_mode_ratio = DIV_ROUND_UP(
802 mipi_config->target_burst_mode_freq * 100,
805 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
807 drm_err(&dev_priv->drm,
808 "Burst mode target is not set\n");
812 burst_mode_ratio = 100;
814 intel_dsi->burst_mode_ratio = burst_mode_ratio;
816 /* delays in VBT are in unit of 100us, so need to convert
818 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
819 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
820 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
821 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
822 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
823 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
825 intel_dsi->i2c_bus_num = -1;
827 /* a regular driver would get the device in probe */
828 for_each_dsi_port(port, intel_dsi->ports) {
829 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
836 * On some BYT/CHT devs some sequences are incomplete and we need to manually
837 * control some GPIOs. We need to add a GPIO lookup table before we get these.
838 * If the GOP did not initialize the panel (HDMI inserted) we may need to also
839 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
841 static struct gpiod_lookup_table pmic_panel_gpio_table = {
842 /* Intel GFX is consumer */
843 .dev_id = "0000:00:02.0",
845 /* Panel EN/DISABLE */
846 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
851 static struct gpiod_lookup_table soc_panel_gpio_table = {
852 .dev_id = "0000:00:02.0",
854 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
855 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
860 static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
861 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
865 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
867 struct drm_device *dev = intel_dsi->base.base.dev;
868 struct drm_i915_private *dev_priv = to_i915(dev);
869 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
870 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
871 bool want_backlight_gpio = false;
872 bool want_panel_gpio = false;
873 struct pinctrl *pinctrl;
876 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
877 mipi_config->pwm_blc == PPS_BLC_PMIC) {
878 gpiod_add_lookup_table(&pmic_panel_gpio_table);
879 want_panel_gpio = true;
882 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
883 gpiod_add_lookup_table(&soc_panel_gpio_table);
884 want_panel_gpio = true;
885 want_backlight_gpio = true;
887 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
888 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
889 ARRAY_SIZE(soc_pwm_pinctrl_map));
891 drm_err(&dev_priv->drm,
892 "Failed to register pwm0 pinmux mapping\n");
894 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
896 drm_err(&dev_priv->drm,
897 "Failed to set pinmux to PWM\n");
900 if (want_panel_gpio) {
901 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
902 if (IS_ERR(intel_dsi->gpio_panel)) {
903 drm_err(&dev_priv->drm,
904 "Failed to own gpio for panel control\n");
905 intel_dsi->gpio_panel = NULL;
909 if (want_backlight_gpio) {
910 intel_dsi->gpio_backlight =
911 gpiod_get(dev->dev, "backlight", flags);
912 if (IS_ERR(intel_dsi->gpio_backlight)) {
913 drm_err(&dev_priv->drm,
914 "Failed to own gpio for backlight control\n");
915 intel_dsi->gpio_backlight = NULL;
920 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
922 struct drm_device *dev = intel_dsi->base.base.dev;
923 struct drm_i915_private *dev_priv = to_i915(dev);
924 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
926 if (intel_dsi->gpio_panel) {
927 gpiod_put(intel_dsi->gpio_panel);
928 intel_dsi->gpio_panel = NULL;
931 if (intel_dsi->gpio_backlight) {
932 gpiod_put(intel_dsi->gpio_backlight);
933 intel_dsi->gpio_backlight = NULL;
936 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
937 mipi_config->pwm_blc == PPS_BLC_PMIC)
938 gpiod_remove_lookup_table(&pmic_panel_gpio_table);
940 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
941 pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
942 gpiod_remove_lookup_table(&soc_panel_gpio_table);