drivers/gpu/drm/i915/display/intel_dsb.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  *
   5  */
   6
   7 #include "i915_drv.h"
   8 #include "intel_display_types.h"
   9
  10 #define DSB_BUF_SIZE    (2 * PAGE_SIZE)
  11
  12 /* DSB opcodes. */
  13 #define DSB_OPCODE_SHIFT                24
  14 #define DSB_OPCODE_MMIO_WRITE           0x1
  15 #define DSB_OPCODE_INDEXED_WRITE        0x9
  16 #define DSB_BYTE_EN                     0xF
  17 #define DSB_BYTE_EN_SHIFT               20
  18 #define DSB_REG_VALUE_MASK              0xfffff
  19
  20 static inline bool is_dsb_busy(struct intel_dsb *dsb)
  21 {
  22         struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
  23         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  24         enum pipe pipe = crtc->pipe;
  25
  26         return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
  27 }
  28
  29 static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
  30 {
  31         struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
  32         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  33         enum pipe pipe = crtc->pipe;
  34         u32 dsb_ctrl;
  35
  36         dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
  37         if (DSB_STATUS & dsb_ctrl) {
  38                 DRM_DEBUG_KMS("DSB engine is busy.\n");
  39                 return false;
  40         }
  41
  42         dsb_ctrl |= DSB_ENABLE;
  43         I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
  44
  45         POSTING_READ(DSB_CTRL(pipe, dsb->id));
  46         return true;
  47 }
  48
  49 static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
  50 {
  51         struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
  52         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  53         enum pipe pipe = crtc->pipe;
  54         u32 dsb_ctrl;
  55
  56         dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
  57         if (DSB_STATUS & dsb_ctrl) {
  58                 DRM_DEBUG_KMS("DSB engine is busy.\n");
  59                 return false;
  60         }
  61
  62         dsb_ctrl &= ~DSB_ENABLE;
  63         I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
  64
  65         POSTING_READ(DSB_CTRL(pipe, dsb->id));
  66         return true;
  67 }
  68
  69 struct intel_dsb *
  70 intel_dsb_get(struct intel_crtc *crtc)
  71 {
  72         struct drm_device *dev = crtc->base.dev;
  73         struct drm_i915_private *i915 = to_i915(dev);
  74         struct intel_dsb *dsb = &crtc->dsb;
  75         struct drm_i915_gem_object *obj;
  76         struct i915_vma *vma;
  77         intel_wakeref_t wakeref;
  78
  79         if (!HAS_DSB(i915))
  80                 return dsb;
  81
  82         if (atomic_add_return(1, &dsb->refcount) != 1)
  83                 return dsb;
  84
  85         dsb->id = DSB1;
  86         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
  87
  88         obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
  89         if (IS_ERR(obj)) {
  90                 DRM_ERROR("Gem object creation failed\n");
  91                 goto err;
  92         }
  93
  94         mutex_lock(&i915->drm.struct_mutex);
  95         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
  96         mutex_unlock(&i915->drm.struct_mutex);
  97         if (IS_ERR(vma)) {
  98                 DRM_ERROR("Vma creation failed\n");
  99                 i915_gem_object_put(obj);
 100                 atomic_dec(&dsb->refcount);
 101                 goto err;
 102         }
 103
 104         dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
 105         if (IS_ERR(dsb->cmd_buf)) {
 106                 DRM_ERROR("Command buffer creation failed\n");
 107                 i915_vma_unpin_and_release(&vma, 0);
 108                 dsb->cmd_buf = NULL;
 109                 atomic_dec(&dsb->refcount);
 110                 goto err;
 111         }
 112         dsb->vma = vma;
 113
 114 err:
 115         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 116         return dsb;
 117 }
 118
 119 void intel_dsb_put(struct intel_dsb *dsb)
 120 {
 121         struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
 122         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 123
 124         if (!HAS_DSB(i915))
 125                 return;
 126
 127         if (WARN_ON(atomic_read(&dsb->refcount) == 0))
 128                 return;
 129
 130         if (atomic_dec_and_test(&dsb->refcount)) {
 131                 mutex_lock(&i915->drm.struct_mutex);
 132                 i915_gem_object_unpin_map(dsb->vma->obj);
 133                 i915_vma_unpin_and_release(&dsb->vma, 0);
 134                 mutex_unlock(&i915->drm.struct_mutex);
 135                 dsb->cmd_buf = NULL;
 136                 dsb->free_pos = 0;
 137                 dsb->ins_start_offset = 0;
 138         }
 139 }
 140
 141 void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
 142                                  u32 val)
 143 {
 144         struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
 145         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 146         u32 *buf = dsb->cmd_buf;
 147         u32 reg_val;
 148
 149         if (!buf) {
 150                 I915_WRITE(reg, val);
 151                 return;
 152         }
 153
 154         if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
 155                 DRM_DEBUG_KMS("DSB buffer overflow\n");
 156                 return;
 157         }
 158
 159         /*
 160          * For example the buffer will look like below for 3 dwords for auto
 161          * increment register:
 162          * +--------------------------------------------------------+
 163          * | size = 3 | offset &| value1 | value2 | value3 | zero   |
 164          * |          | opcode  |        |        |        |        |
 165          * +--------------------------------------------------------+
 166          * +          +         +        +        +        +        +
 167          * 0          4         8        12       16       20       24
 168          * Byte
 169          *
 170          * As every instruction is 8 byte aligned the index of dsb instruction
 171          * will start always from even number while dealing with u32 array. If
 172          * we are writing odd no of dwords, Zeros will be added in the end for
 173          * padding.
 174          */
 175         reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
 176         if (reg_val != i915_mmio_reg_offset(reg)) {
 177                 /* Every instruction should be 8 byte aligned. */
 178                 dsb->free_pos = ALIGN(dsb->free_pos, 2);
 179
 180                 dsb->ins_start_offset = dsb->free_pos;
 181
 182                 /* Update the size. */
 183                 buf[dsb->free_pos++] = 1;
 184
 185                 /* Update the opcode and reg. */
 186                 buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE  <<
 187                                         DSB_OPCODE_SHIFT) |
 188                                         i915_mmio_reg_offset(reg);
 189
 190                 /* Update the value. */
 191                 buf[dsb->free_pos++] = val;
 192         } else {
 193                 /* Update the new value. */
 194                 buf[dsb->free_pos++] = val;
 195
 196                 /* Update the size. */
 197                 buf[dsb->ins_start_offset]++;
 198         }
 199
 200         /* if number of data words is odd, then the last dword should be 0.*/
 201         if (dsb->free_pos & 0x1)
 202                 buf[dsb->free_pos] = 0;
 203 }
 204
 205 void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
 206 {
 207         struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
 208         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 209         u32 *buf = dsb->cmd_buf;
 210
 211         if (!buf) {
 212                 I915_WRITE(reg, val);
 213                 return;
 214         }
 215
 216         if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
 217                 DRM_DEBUG_KMS("DSB buffer overflow\n");
 218                 return;
 219         }
 220
 221         dsb->ins_start_offset = dsb->free_pos;
 222         buf[dsb->free_pos++] = val;
 223         buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE  << DSB_OPCODE_SHIFT) |
 224                                (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
 225                                i915_mmio_reg_offset(reg);
 226 }